Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T5,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	939830081	756502648	0	0
CheckNGreaterZero_A	2820	2820	0	0
GntImpliesReady_A	939830081	4227034	0	0
GntImpliesValid_A	939830081	4227034	0	0
GrantKnown_A	939830081	756502648	0	0
IdxKnown_A	939830081	756502648	0	0
IndexIsCorrect_A	939830081	4227034	0	0
LockArbDecision_A	939830081	0	0	0
NoReadyValidNoGrant_A	939830081	0	0	0
ReadyAndValidImplyGrant_A	939830081	4227034	0	0
ReqAndReadyImplyGrant_A	939830081	4227034	0	0
ReqImpliesValid_A	939830081	4227034	0	0
ReqStaysHighUntilGranted0_M	939830081	0	0	0
RoundRobin_A	939830081	4	0	940
ValidKnown_A	939830081	756502648	0	0
gen_data_port_assertion.DataFlow_A	939830081	4227034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	756502648	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	176239	175526	0	0
T4	11070	10986	0	0
T5	2236973	1371697	0	0
T6	101613	84766	0	0
T7	887	834	0	0
T8	1061448	935653	0	0
T9	161000	138189	0	0
T10	7002	5497	0	0
T11	460706	226096	0	0
T12	214636	214636	0	0
T13	104920	104300	0	0
T14	0	14128	0	0
T15	0	712767	0	0
T16	48580	22992	0	0
T18	381390	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2820	2820	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	756502648	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	176239	175526	0	0
T4	11070	10986	0	0
T5	2236973	1371697	0	0
T6	101613	84766	0	0
T7	887	834	0	0
T8	1061448	935653	0	0
T9	161000	138189	0	0
T10	7002	5497	0	0
T11	460706	226096	0	0
T12	214636	214636	0	0
T13	104920	104300	0	0
T14	0	14128	0	0
T15	0	712767	0	0
T16	48580	22992	0	0
T18	381390	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	756502648	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	176239	175526	0	0
T4	11070	10986	0	0
T5	2236973	1371697	0	0
T6	101613	84766	0	0
T7	887	834	0	0
T8	1061448	935653	0	0
T9	161000	138189	0	0
T10	7002	5497	0	0
T11	460706	226096	0	0
T12	214636	214636	0	0
T13	104920	104300	0	0
T14	0	14128	0	0
T15	0	712767	0	0
T16	48580	22992	0	0
T18	381390	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4	0	940
T44	451339	1	0	1
T45	246968	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	394566	0	0	1
T49	233775	0	0	1
T50	11221	0	0	1
T51	1162	0	0	1
T52	553064	0	0	1
T53	2834	0	0	1
T54	5417	0	0	1
T55	35480	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	756502648	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	176239	175526	0	0
T4	11070	10986	0	0
T5	2236973	1371697	0	0
T6	101613	84766	0	0
T7	887	834	0	0
T8	1061448	935653	0	0
T9	161000	138189	0	0
T10	7002	5497	0	0
T11	460706	226096	0	0
T12	214636	214636	0	0
T13	104920	104300	0	0
T14	0	14128	0	0
T15	0	712767	0	0
T16	48580	22992	0	0
T18	381390	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939830081	4227034	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	2236973	29968	0	0
T6	101613	832	0	0
T7	887	0	0	0
T8	1061448	21449	0	0
T9	161000	1277	0	0
T10	7002	0	0	0
T11	460706	5008	0	0
T12	429272	832	0	0
T13	209840	5376	0	0
T15	0	6335	0	0
T16	87470	0	0	0
T17	1359	0	0	0
T18	381390	10775	0	0
T20	0	38	0	0
T21	0	200	0	0
T27	0	13410	0	0
T28	0	5602	0	0
T29	0	6415	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	9701	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	181381281	40243855	0	0
CheckNGreaterZero_A	940	940	0	0
GntImpliesReady_A	181381281	936168	0	0
GntImpliesValid_A	181381281	936168	0	0
GrantKnown_A	181381281	40243855	0	0
IdxKnown_A	181381281	40243855	0	0
IndexIsCorrect_A	181381281	936168	0	0
LockArbDecision_A	181381281	0	0	0
NoReadyValidNoGrant_A	181381281	0	0	0
ReadyAndValidImplyGrant_A	181381281	936168	0	0
ReqAndReadyImplyGrant_A	181381281	936168	0	0
ReqImpliesValid_A	181381281	936168	0	0
ReqStaysHighUntilGranted0_M	181381281	0	0	0
RoundRobin_A	181381281	0	0	0
ValidKnown_A	181381281	40243855	0	0
gen_data_port_assertion.DataFlow_A	181381281	936168	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	40243855	0	0
T5	857134	97680	0	0
T6	16400	0	0	0
T8	131561	6928	0	0
T9	22396	22072	0	0
T10	1403	1368	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	444776	0	0
T16	24290	22992	0	0
T18	190695	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940	940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	40243855	0	0
T5	857134	97680	0	0
T6	16400	0	0	0
T8	131561	6928	0	0
T9	22396	22072	0	0
T10	1403	1368	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	444776	0	0
T16	24290	22992	0	0
T18	190695	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	40243855	0	0
T5	857134	97680	0	0
T6	16400	0	0	0
T8	131561	6928	0	0
T9	22396	22072	0	0
T10	1403	1368	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	444776	0	0
T16	24290	22992	0	0
T18	190695	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	40243855	0	0
T5	857134	97680	0	0
T6	16400	0	0	0
T8	131561	6928	0	0
T9	22396	22072	0	0
T10	1403	1368	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	444776	0	0
T16	24290	22992	0	0
T18	190695	181160	0	0
T19	0	936	0	0
T20	0	2888	0	0
T42	0	648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	936168	0	0
T5	857134	4667	0	0
T6	16400	0	0	0
T8	131561	359	0	0
T9	22396	851	0	0
T10	1403	0	0	0
T11	230353	0	0	0
T12	214636	0	0	0
T13	104920	0	0	0
T15	0	5722	0	0
T16	24290	0	0	0
T18	190695	7435	0	0
T20	0	38	0	0
T27	0	7728	0	0
T28	0	5602	0	0
T29	0	6404	0	0
T43	0	6365	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T11
1	0	Covered	T5,T8,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Unreachable
1	1	Covered	T5,T8,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T11
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	181381281	139278047	0	0
CheckNGreaterZero_A	940	940	0	0
GntImpliesReady_A	181381281	649798	0	0
GntImpliesValid_A	181381281	649798	0	0
GrantKnown_A	181381281	139278047	0	0
IdxKnown_A	181381281	139278047	0	0
IndexIsCorrect_A	181381281	649798	0	0
LockArbDecision_A	181381281	0	0	0
NoReadyValidNoGrant_A	181381281	0	0	0
ReadyAndValidImplyGrant_A	181381281	649798	0	0
ReqAndReadyImplyGrant_A	181381281	649798	0	0
ReqImpliesValid_A	181381281	649798	0	0
ReqStaysHighUntilGranted0_M	181381281	0	0	0
RoundRobin_A	181381281	0	0	0
ValidKnown_A	181381281	139278047	0	0
gen_data_port_assertion.DataFlow_A	181381281	649798	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	139278047	0	0
T3	137292	136636	0	0
T4	96	96	0	0
T5	857134	751320	0	0
T6	16400	16032	0	0
T8	131561	130406	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	226096	0	0
T12	0	214636	0	0
T13	0	104300	0	0
T14	0	14128	0	0
T15	0	267991	0	0
T16	24290	0	0	0
T18	190695	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940	940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	139278047	0	0
T3	137292	136636	0	0
T4	96	96	0	0
T5	857134	751320	0	0
T6	16400	16032	0	0
T8	131561	130406	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	226096	0	0
T12	0	214636	0	0
T13	0	104300	0	0
T14	0	14128	0	0
T15	0	267991	0	0
T16	24290	0	0	0
T18	190695	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	139278047	0	0
T3	137292	136636	0	0
T4	96	96	0	0
T5	857134	751320	0	0
T6	16400	16032	0	0
T8	131561	130406	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	226096	0	0
T12	0	214636	0	0
T13	0	104300	0	0
T14	0	14128	0	0
T15	0	267991	0	0
T16	24290	0	0	0
T18	190695	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	139278047	0	0
T3	137292	136636	0	0
T4	96	96	0	0
T5	857134	751320	0	0
T6	16400	16032	0	0
T8	131561	130406	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	226096	0	0
T12	0	214636	0	0
T13	0	104300	0	0
T14	0	14128	0	0
T15	0	267991	0	0
T16	24290	0	0	0
T18	190695	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181381281	649798	0	0
T5	857134	7195	0	0
T6	16400	0	0	0
T8	131561	6393	0	0
T9	22396	0	0	0
T10	1403	0	0	0
T11	230353	8	0	0
T12	214636	0	0	0
T13	104920	5376	0	0
T15	0	613	0	0
T16	24290	0	0	0
T18	190695	0	0	0
T27	0	5682	0	0
T29	0	11	0	0
T30	0	2997	0	0
T31	0	7596	0	0
T43	0	3336	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T3,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	577067519	576980746	0	0
CheckNGreaterZero_A	940	940	0	0
GntImpliesReady_A	577067519	2641068	0	0
GntImpliesValid_A	577067519	2641068	0	0
GrantKnown_A	577067519	576980746	0	0
IdxKnown_A	577067519	576980746	0	0
IndexIsCorrect_A	577067519	2641068	0	0
LockArbDecision_A	577067519	0	0	0
NoReadyValidNoGrant_A	577067519	0	0	0
ReadyAndValidImplyGrant_A	577067519	2641068	0	0
ReqAndReadyImplyGrant_A	577067519	2641068	0	0
ReqImpliesValid_A	577067519	2641068	0	0
ReqStaysHighUntilGranted0_M	577067519	0	0	0
RoundRobin_A	577067519	4	0	940
ValidKnown_A	577067519	576980746	0	0
gen_data_port_assertion.DataFlow_A	577067519	2641068	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	576980746	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	38947	38890	0	0
T4	10974	10890	0	0
T5	522705	522697	0	0
T6	68813	68734	0	0
T7	887	834	0	0
T8	798326	798319	0	0
T9	116208	116117	0	0
T10	4196	4129	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	940	940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	576980746	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	38947	38890	0	0
T4	10974	10890	0	0
T5	522705	522697	0	0
T6	68813	68734	0	0
T7	887	834	0	0
T8	798326	798319	0	0
T9	116208	116117	0	0
T10	4196	4129	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	576980746	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	38947	38890	0	0
T4	10974	10890	0	0
T5	522705	522697	0	0
T6	68813	68734	0	0
T7	887	834	0	0
T8	798326	798319	0	0
T9	116208	116117	0	0
T10	4196	4129	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	4	0	940
T44	451339	1	0	1
T45	246968	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	394566	0	0	1
T49	233775	0	0	1
T50	11221	0	0	1
T51	1162	0	0	1
T52	553064	0	0	1
T53	2834	0	0	1
T54	5417	0	0	1
T55	35480	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	576980746	0	0
T1	903	848	0	0
T2	981	883	0	0
T3	38947	38890	0	0
T4	10974	10890	0	0
T5	522705	522697	0	0
T6	68813	68734	0	0
T7	887	834	0	0
T8	798326	798319	0	0
T9	116208	116117	0	0
T10	4196	4129	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577067519	2641068	0	0
T3	38947	832	0	0
T4	10974	832	0	0
T5	522705	18106	0	0
T6	68813	832	0	0
T7	887	0	0	0
T8	798326	14697	0	0
T9	116208	426	0	0
T10	4196	0	0	0
T11	0	5000	0	0
T12	0	832	0	0
T16	38890	0	0	0
T17	1359	0	0	0
T18	0	3340	0	0
T21	0	200	0	0