Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
3457 |
0 |
0 |
T82 |
20350 |
1 |
0 |
0 |
T83 |
9311 |
2 |
0 |
0 |
T84 |
2021 |
1 |
0 |
0 |
T85 |
6058 |
368 |
0 |
0 |
T86 |
2276 |
3 |
0 |
0 |
T87 |
26248 |
1 |
0 |
0 |
T88 |
65980 |
5 |
0 |
0 |
T91 |
10758 |
4 |
0 |
0 |
T92 |
95649 |
2 |
0 |
0 |
T105 |
28593 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1785 |
0 |
0 |
T72 |
4067 |
15 |
0 |
0 |
T88 |
65980 |
83 |
0 |
0 |
T91 |
10758 |
19 |
0 |
0 |
T92 |
95649 |
136 |
0 |
0 |
T106 |
14699 |
36 |
0 |
0 |
T109 |
76071 |
549 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
36 |
0 |
0 |
T130 |
10509 |
23 |
0 |
0 |
T131 |
10866 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1772 |
0 |
0 |
T72 |
4067 |
8 |
0 |
0 |
T88 |
65980 |
86 |
0 |
0 |
T91 |
10758 |
18 |
0 |
0 |
T92 |
95649 |
105 |
0 |
0 |
T106 |
14699 |
27 |
0 |
0 |
T109 |
76071 |
521 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
42 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2428 |
0 |
0 |
T72 |
4067 |
15 |
0 |
0 |
T88 |
65980 |
163 |
0 |
0 |
T91 |
10758 |
34 |
0 |
0 |
T92 |
95649 |
255 |
0 |
0 |
T106 |
14699 |
27 |
0 |
0 |
T109 |
76071 |
503 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
50 |
0 |
0 |
T130 |
10509 |
18 |
0 |
0 |
T132 |
5897 |
12 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10176 |
0 |
0 |
T72 |
4067 |
6 |
0 |
0 |
T88 |
65980 |
1191 |
0 |
0 |
T91 |
10758 |
18 |
0 |
0 |
T92 |
95649 |
1861 |
0 |
0 |
T106 |
14699 |
28 |
0 |
0 |
T109 |
76071 |
484 |
0 |
0 |
T116 |
8928 |
113 |
0 |
0 |
T129 |
34730 |
465 |
0 |
0 |
T130 |
10509 |
157 |
0 |
0 |
T131 |
10866 |
372 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10119 |
0 |
0 |
T72 |
4067 |
10 |
0 |
0 |
T88 |
65980 |
1663 |
0 |
0 |
T91 |
10758 |
14 |
0 |
0 |
T92 |
95649 |
1090 |
0 |
0 |
T98 |
10764 |
1 |
0 |
0 |
T106 |
14699 |
119 |
0 |
0 |
T109 |
76071 |
526 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
612 |
0 |
0 |
T132 |
5897 |
8 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10734 |
0 |
0 |
T72 |
4067 |
13 |
0 |
0 |
T88 |
65980 |
1208 |
0 |
0 |
T91 |
10758 |
13 |
0 |
0 |
T92 |
95649 |
1968 |
0 |
0 |
T106 |
14699 |
269 |
0 |
0 |
T109 |
76071 |
534 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
776 |
0 |
0 |
T130 |
10509 |
328 |
0 |
0 |
T132 |
5897 |
9 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10522 |
0 |
0 |
T72 |
4067 |
11 |
0 |
0 |
T88 |
65980 |
1230 |
0 |
0 |
T91 |
10758 |
141 |
0 |
0 |
T92 |
95649 |
1490 |
0 |
0 |
T106 |
14699 |
291 |
0 |
0 |
T109 |
76071 |
473 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
677 |
0 |
0 |
T130 |
10509 |
134 |
0 |
0 |
T132 |
5897 |
11 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
11705 |
0 |
0 |
T72 |
4067 |
14 |
0 |
0 |
T88 |
65980 |
1083 |
0 |
0 |
T91 |
10758 |
9 |
0 |
0 |
T92 |
95649 |
1768 |
0 |
0 |
T106 |
14699 |
301 |
0 |
0 |
T109 |
76071 |
485 |
0 |
0 |
T111 |
2154 |
5 |
0 |
0 |
T129 |
34730 |
894 |
0 |
0 |
T130 |
10509 |
143 |
0 |
0 |
T132 |
5897 |
2 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10178 |
0 |
0 |
T72 |
4067 |
10 |
0 |
0 |
T88 |
65980 |
1133 |
0 |
0 |
T91 |
10758 |
228 |
0 |
0 |
T92 |
95649 |
2043 |
0 |
0 |
T106 |
14699 |
168 |
0 |
0 |
T109 |
76071 |
524 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
129 |
0 |
0 |
T130 |
10509 |
155 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10994 |
0 |
0 |
T72 |
4067 |
16 |
0 |
0 |
T88 |
65980 |
1571 |
0 |
0 |
T91 |
10758 |
106 |
0 |
0 |
T92 |
95649 |
1701 |
0 |
0 |
T106 |
14699 |
113 |
0 |
0 |
T109 |
76071 |
492 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
594 |
0 |
0 |
T130 |
10509 |
26 |
0 |
0 |
T132 |
5897 |
12 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
10419 |
0 |
0 |
T72 |
4067 |
16 |
0 |
0 |
T88 |
65980 |
937 |
0 |
0 |
T91 |
10758 |
247 |
0 |
0 |
T92 |
95649 |
1961 |
0 |
0 |
T106 |
14699 |
33 |
0 |
0 |
T109 |
76071 |
478 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
705 |
0 |
0 |
T130 |
10509 |
273 |
0 |
0 |
T131 |
10866 |
12 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5198 |
0 |
0 |
T72 |
4067 |
11 |
0 |
0 |
T88 |
65980 |
608 |
0 |
0 |
T91 |
10758 |
59 |
0 |
0 |
T92 |
95649 |
810 |
0 |
0 |
T106 |
14699 |
136 |
0 |
0 |
T109 |
76071 |
497 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
184 |
0 |
0 |
T130 |
10509 |
68 |
0 |
0 |
T132 |
5897 |
6 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
4928 |
0 |
0 |
T72 |
4067 |
5 |
0 |
0 |
T88 |
65980 |
553 |
0 |
0 |
T91 |
10758 |
69 |
0 |
0 |
T92 |
95649 |
681 |
0 |
0 |
T106 |
14699 |
86 |
0 |
0 |
T109 |
76071 |
500 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
249 |
0 |
0 |
T130 |
10509 |
75 |
0 |
0 |
T132 |
5897 |
7 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5381 |
0 |
0 |
T72 |
4067 |
23 |
0 |
0 |
T88 |
65980 |
667 |
0 |
0 |
T91 |
10758 |
60 |
0 |
0 |
T92 |
95649 |
841 |
0 |
0 |
T106 |
14699 |
71 |
0 |
0 |
T109 |
76071 |
480 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
243 |
0 |
0 |
T130 |
10509 |
8 |
0 |
0 |
T132 |
5897 |
31 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5318 |
0 |
0 |
T72 |
4067 |
25 |
0 |
0 |
T88 |
65980 |
654 |
0 |
0 |
T91 |
10758 |
84 |
0 |
0 |
T92 |
95649 |
871 |
0 |
0 |
T106 |
14699 |
110 |
0 |
0 |
T109 |
76071 |
543 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
271 |
0 |
0 |
T130 |
10509 |
120 |
0 |
0 |
T132 |
5897 |
20 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5234 |
0 |
0 |
T72 |
4067 |
11 |
0 |
0 |
T88 |
65980 |
596 |
0 |
0 |
T91 |
10758 |
97 |
0 |
0 |
T92 |
95649 |
512 |
0 |
0 |
T106 |
14699 |
116 |
0 |
0 |
T109 |
76071 |
503 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
311 |
0 |
0 |
T130 |
10509 |
63 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5236 |
0 |
0 |
T72 |
4067 |
6 |
0 |
0 |
T88 |
65980 |
510 |
0 |
0 |
T89 |
7441 |
4 |
0 |
0 |
T91 |
10758 |
60 |
0 |
0 |
T92 |
95649 |
815 |
0 |
0 |
T106 |
14699 |
57 |
0 |
0 |
T109 |
76071 |
560 |
0 |
0 |
T129 |
34730 |
460 |
0 |
0 |
T130 |
10509 |
18 |
0 |
0 |
T132 |
5897 |
15 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5841 |
0 |
0 |
T72 |
4067 |
8 |
0 |
0 |
T88 |
65980 |
645 |
0 |
0 |
T91 |
10758 |
55 |
0 |
0 |
T92 |
95649 |
1004 |
0 |
0 |
T106 |
14699 |
107 |
0 |
0 |
T109 |
76071 |
532 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
390 |
0 |
0 |
T130 |
10509 |
59 |
0 |
0 |
T131 |
10866 |
53 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5698 |
0 |
0 |
T72 |
4067 |
5 |
0 |
0 |
T88 |
65980 |
602 |
0 |
0 |
T91 |
10758 |
55 |
0 |
0 |
T92 |
95649 |
802 |
0 |
0 |
T106 |
14699 |
158 |
0 |
0 |
T109 |
76071 |
540 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
420 |
0 |
0 |
T130 |
10509 |
88 |
0 |
0 |
T131 |
10866 |
103 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5295 |
0 |
0 |
T72 |
4067 |
20 |
0 |
0 |
T88 |
65980 |
442 |
0 |
0 |
T91 |
10758 |
38 |
0 |
0 |
T92 |
95649 |
681 |
0 |
0 |
T106 |
14699 |
92 |
0 |
0 |
T109 |
76071 |
520 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
335 |
0 |
0 |
T130 |
10509 |
67 |
0 |
0 |
T132 |
5897 |
7 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5259 |
0 |
0 |
T72 |
4067 |
13 |
0 |
0 |
T88 |
65980 |
680 |
0 |
0 |
T91 |
10758 |
72 |
0 |
0 |
T92 |
95649 |
596 |
0 |
0 |
T106 |
14699 |
124 |
0 |
0 |
T109 |
76071 |
506 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
315 |
0 |
0 |
T130 |
10509 |
29 |
0 |
0 |
T132 |
5897 |
25 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5178 |
0 |
0 |
T72 |
4067 |
5 |
0 |
0 |
T88 |
65980 |
596 |
0 |
0 |
T91 |
10758 |
7 |
0 |
0 |
T92 |
95649 |
739 |
0 |
0 |
T106 |
14699 |
36 |
0 |
0 |
T109 |
76071 |
506 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
226 |
0 |
0 |
T130 |
10509 |
119 |
0 |
0 |
T132 |
5897 |
19 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5903 |
0 |
0 |
T72 |
4067 |
18 |
0 |
0 |
T88 |
65980 |
578 |
0 |
0 |
T91 |
10758 |
57 |
0 |
0 |
T92 |
95649 |
937 |
0 |
0 |
T106 |
14699 |
169 |
0 |
0 |
T109 |
76071 |
527 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
304 |
0 |
0 |
T130 |
10509 |
72 |
0 |
0 |
T132 |
5897 |
9 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5430 |
0 |
0 |
T72 |
4067 |
14 |
0 |
0 |
T88 |
65980 |
353 |
0 |
0 |
T91 |
10758 |
86 |
0 |
0 |
T92 |
95649 |
917 |
0 |
0 |
T106 |
14699 |
136 |
0 |
0 |
T109 |
76071 |
491 |
0 |
0 |
T129 |
34730 |
277 |
0 |
0 |
T130 |
10509 |
55 |
0 |
0 |
T131 |
10866 |
54 |
0 |
0 |
T132 |
5897 |
5 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5241 |
0 |
0 |
T72 |
4067 |
6 |
0 |
0 |
T88 |
65980 |
697 |
0 |
0 |
T91 |
10758 |
89 |
0 |
0 |
T92 |
95649 |
626 |
0 |
0 |
T106 |
14699 |
143 |
0 |
0 |
T109 |
76071 |
541 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
261 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
6 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
4808 |
0 |
0 |
T72 |
4067 |
2 |
0 |
0 |
T88 |
65980 |
481 |
0 |
0 |
T91 |
10758 |
17 |
0 |
0 |
T92 |
95649 |
472 |
0 |
0 |
T106 |
14699 |
99 |
0 |
0 |
T109 |
76071 |
489 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
244 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
25 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5471 |
0 |
0 |
T72 |
4067 |
8 |
0 |
0 |
T88 |
65980 |
418 |
0 |
0 |
T91 |
10758 |
50 |
0 |
0 |
T92 |
95649 |
1052 |
0 |
0 |
T106 |
14699 |
80 |
0 |
0 |
T109 |
76071 |
523 |
0 |
0 |
T129 |
34730 |
218 |
0 |
0 |
T130 |
10509 |
65 |
0 |
0 |
T131 |
10866 |
116 |
0 |
0 |
T132 |
5897 |
4 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5282 |
0 |
0 |
T88 |
65980 |
489 |
0 |
0 |
T91 |
10758 |
100 |
0 |
0 |
T92 |
95649 |
842 |
0 |
0 |
T106 |
14699 |
114 |
0 |
0 |
T109 |
76071 |
580 |
0 |
0 |
T111 |
2154 |
9 |
0 |
0 |
T129 |
34730 |
204 |
0 |
0 |
T130 |
10509 |
60 |
0 |
0 |
T131 |
10866 |
76 |
0 |
0 |
T132 |
5897 |
22 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5394 |
0 |
0 |
T72 |
4067 |
8 |
0 |
0 |
T88 |
65980 |
303 |
0 |
0 |
T91 |
10758 |
50 |
0 |
0 |
T92 |
95649 |
1004 |
0 |
0 |
T106 |
14699 |
72 |
0 |
0 |
T109 |
76071 |
537 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
285 |
0 |
0 |
T130 |
10509 |
80 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5379 |
0 |
0 |
T72 |
4067 |
3 |
0 |
0 |
T88 |
65980 |
745 |
0 |
0 |
T91 |
10758 |
37 |
0 |
0 |
T92 |
95649 |
796 |
0 |
0 |
T106 |
14699 |
28 |
0 |
0 |
T109 |
76071 |
497 |
0 |
0 |
T111 |
2154 |
5 |
0 |
0 |
T129 |
34730 |
264 |
0 |
0 |
T130 |
10509 |
19 |
0 |
0 |
T132 |
5897 |
9 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
4969 |
0 |
0 |
T72 |
4067 |
20 |
0 |
0 |
T88 |
65980 |
501 |
0 |
0 |
T91 |
10758 |
51 |
0 |
0 |
T92 |
95649 |
778 |
0 |
0 |
T106 |
14699 |
14 |
0 |
0 |
T109 |
76071 |
561 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
450 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
25 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5449 |
0 |
0 |
T72 |
4067 |
7 |
0 |
0 |
T88 |
65980 |
471 |
0 |
0 |
T91 |
10758 |
47 |
0 |
0 |
T92 |
95649 |
852 |
0 |
0 |
T106 |
14699 |
115 |
0 |
0 |
T109 |
76071 |
495 |
0 |
0 |
T111 |
2154 |
5 |
0 |
0 |
T129 |
34730 |
344 |
0 |
0 |
T130 |
10509 |
82 |
0 |
0 |
T131 |
10866 |
120 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5013 |
0 |
0 |
T72 |
4067 |
5 |
0 |
0 |
T88 |
65980 |
693 |
0 |
0 |
T91 |
10758 |
89 |
0 |
0 |
T92 |
95649 |
678 |
0 |
0 |
T106 |
14699 |
84 |
0 |
0 |
T109 |
76071 |
531 |
0 |
0 |
T129 |
34730 |
454 |
0 |
0 |
T130 |
10509 |
20 |
0 |
0 |
T131 |
10866 |
57 |
0 |
0 |
T132 |
5897 |
4 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5183 |
0 |
0 |
T72 |
4067 |
10 |
0 |
0 |
T88 |
65980 |
448 |
0 |
0 |
T91 |
10758 |
72 |
0 |
0 |
T92 |
95649 |
827 |
0 |
0 |
T106 |
14699 |
154 |
0 |
0 |
T109 |
76071 |
499 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
163 |
0 |
0 |
T130 |
10509 |
122 |
0 |
0 |
T131 |
10866 |
130 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
5140 |
0 |
0 |
T72 |
4067 |
3 |
0 |
0 |
T88 |
65980 |
549 |
0 |
0 |
T91 |
10758 |
119 |
0 |
0 |
T92 |
95649 |
673 |
0 |
0 |
T93 |
10443 |
5 |
0 |
0 |
T106 |
14699 |
136 |
0 |
0 |
T109 |
76071 |
480 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
206 |
0 |
0 |
T132 |
5897 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2100 |
0 |
0 |
T72 |
4067 |
8 |
0 |
0 |
T88 |
65980 |
111 |
0 |
0 |
T91 |
10758 |
6 |
0 |
0 |
T92 |
95649 |
158 |
0 |
0 |
T106 |
14699 |
39 |
0 |
0 |
T109 |
76071 |
544 |
0 |
0 |
T111 |
2154 |
3 |
0 |
0 |
T129 |
34730 |
86 |
0 |
0 |
T130 |
10509 |
20 |
0 |
0 |
T132 |
5897 |
9 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2075 |
0 |
0 |
T72 |
4067 |
15 |
0 |
0 |
T88 |
65980 |
99 |
0 |
0 |
T91 |
10758 |
26 |
0 |
0 |
T92 |
95649 |
166 |
0 |
0 |
T106 |
14699 |
38 |
0 |
0 |
T109 |
76071 |
500 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
59 |
0 |
0 |
T130 |
10509 |
18 |
0 |
0 |
T132 |
5897 |
13 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1961 |
0 |
0 |
T72 |
4067 |
13 |
0 |
0 |
T88 |
65980 |
116 |
0 |
0 |
T91 |
10758 |
27 |
0 |
0 |
T92 |
95649 |
172 |
0 |
0 |
T106 |
14699 |
35 |
0 |
0 |
T109 |
76071 |
500 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
69 |
0 |
0 |
T130 |
10509 |
16 |
0 |
0 |
T132 |
5897 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2030 |
0 |
0 |
T72 |
4067 |
10 |
0 |
0 |
T88 |
65980 |
116 |
0 |
0 |
T91 |
10758 |
12 |
0 |
0 |
T92 |
95649 |
114 |
0 |
0 |
T106 |
14699 |
25 |
0 |
0 |
T109 |
76071 |
537 |
0 |
0 |
T129 |
34730 |
65 |
0 |
0 |
T130 |
10509 |
22 |
0 |
0 |
T131 |
10866 |
26 |
0 |
0 |
T132 |
5897 |
4 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2718 |
0 |
0 |
T72 |
4067 |
12 |
0 |
0 |
T88 |
65980 |
226 |
0 |
0 |
T91 |
10758 |
24 |
0 |
0 |
T92 |
95649 |
361 |
0 |
0 |
T106 |
14699 |
17 |
0 |
0 |
T109 |
76071 |
491 |
0 |
0 |
T129 |
34730 |
77 |
0 |
0 |
T130 |
10509 |
35 |
0 |
0 |
T131 |
10866 |
47 |
0 |
0 |
T132 |
5897 |
4 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
4252 |
0 |
0 |
T22 |
106625 |
0 |
0 |
0 |
T35 |
727552 |
0 |
0 |
0 |
T57 |
1352 |
0 |
0 |
0 |
T61 |
405988 |
62 |
0 |
0 |
T77 |
0 |
29 |
0 |
0 |
T126 |
17794 |
0 |
0 |
0 |
T127 |
991369 |
0 |
0 |
0 |
T133 |
0 |
60 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T135 |
0 |
20 |
0 |
0 |
T136 |
0 |
13 |
0 |
0 |
T137 |
0 |
11 |
0 |
0 |
T138 |
0 |
45 |
0 |
0 |
T139 |
0 |
43 |
0 |
0 |
T140 |
0 |
30 |
0 |
0 |
T141 |
29713 |
0 |
0 |
0 |
T142 |
24054 |
0 |
0 |
0 |
T143 |
98024 |
0 |
0 |
0 |
T144 |
195437 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1960 |
0 |
0 |
T72 |
4067 |
7 |
0 |
0 |
T88 |
65980 |
101 |
0 |
0 |
T91 |
10758 |
19 |
0 |
0 |
T92 |
95649 |
170 |
0 |
0 |
T106 |
14699 |
32 |
0 |
0 |
T109 |
76071 |
490 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
46 |
0 |
0 |
T130 |
10509 |
13 |
0 |
0 |
T132 |
5897 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2000 |
0 |
0 |
T72 |
4067 |
7 |
0 |
0 |
T88 |
65980 |
101 |
0 |
0 |
T91 |
10758 |
14 |
0 |
0 |
T92 |
95649 |
147 |
0 |
0 |
T93 |
10443 |
3 |
0 |
0 |
T106 |
14699 |
23 |
0 |
0 |
T109 |
76071 |
463 |
0 |
0 |
T111 |
2154 |
10 |
0 |
0 |
T129 |
34730 |
57 |
0 |
0 |
T130 |
10509 |
16 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1842 |
0 |
0 |
T72 |
4067 |
11 |
0 |
0 |
T88 |
65980 |
76 |
0 |
0 |
T91 |
10758 |
16 |
0 |
0 |
T92 |
95649 |
120 |
0 |
0 |
T106 |
14699 |
29 |
0 |
0 |
T109 |
76071 |
466 |
0 |
0 |
T111 |
2154 |
9 |
0 |
0 |
T129 |
34730 |
49 |
0 |
0 |
T130 |
10509 |
13 |
0 |
0 |
T132 |
5897 |
15 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1901 |
0 |
0 |
T72 |
4067 |
19 |
0 |
0 |
T88 |
65980 |
74 |
0 |
0 |
T91 |
10758 |
13 |
0 |
0 |
T92 |
95649 |
148 |
0 |
0 |
T106 |
14699 |
23 |
0 |
0 |
T109 |
76071 |
544 |
0 |
0 |
T111 |
2154 |
4 |
0 |
0 |
T129 |
34730 |
42 |
0 |
0 |
T130 |
10509 |
28 |
0 |
0 |
T132 |
5897 |
12 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1803 |
0 |
0 |
T72 |
4067 |
6 |
0 |
0 |
T88 |
65980 |
94 |
0 |
0 |
T91 |
10758 |
15 |
0 |
0 |
T92 |
95649 |
115 |
0 |
0 |
T106 |
14699 |
36 |
0 |
0 |
T109 |
76071 |
544 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
48 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
3 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1820 |
0 |
0 |
T72 |
4067 |
20 |
0 |
0 |
T88 |
65980 |
79 |
0 |
0 |
T91 |
10758 |
12 |
0 |
0 |
T92 |
95649 |
127 |
0 |
0 |
T106 |
14699 |
19 |
0 |
0 |
T109 |
76071 |
492 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
39 |
0 |
0 |
T130 |
10509 |
18 |
0 |
0 |
T131 |
10866 |
9 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2634 |
0 |
0 |
T72 |
4067 |
6 |
0 |
0 |
T88 |
65980 |
190 |
0 |
0 |
T91 |
10758 |
27 |
0 |
0 |
T92 |
95649 |
321 |
0 |
0 |
T106 |
14699 |
28 |
0 |
0 |
T109 |
76071 |
496 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
83 |
0 |
0 |
T130 |
10509 |
19 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1761 |
0 |
0 |
T72 |
4067 |
15 |
0 |
0 |
T88 |
65980 |
73 |
0 |
0 |
T91 |
10758 |
16 |
0 |
0 |
T92 |
95649 |
104 |
0 |
0 |
T106 |
14699 |
22 |
0 |
0 |
T109 |
76071 |
490 |
0 |
0 |
T111 |
2154 |
7 |
0 |
0 |
T129 |
34730 |
26 |
0 |
0 |
T130 |
10509 |
12 |
0 |
0 |
T132 |
5897 |
10 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2994 |
0 |
0 |
T72 |
4067 |
10 |
0 |
0 |
T88 |
65980 |
206 |
0 |
0 |
T91 |
10758 |
26 |
0 |
0 |
T92 |
95649 |
307 |
0 |
0 |
T106 |
14699 |
63 |
0 |
0 |
T109 |
76071 |
558 |
0 |
0 |
T111 |
2154 |
6 |
0 |
0 |
T129 |
34730 |
117 |
0 |
0 |
T130 |
10509 |
23 |
0 |
0 |
T132 |
5897 |
17 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
2046 |
0 |
0 |
T72 |
4067 |
13 |
0 |
0 |
T88 |
65980 |
115 |
0 |
0 |
T91 |
10758 |
12 |
0 |
0 |
T92 |
95649 |
151 |
0 |
0 |
T106 |
14699 |
36 |
0 |
0 |
T109 |
76071 |
554 |
0 |
0 |
T111 |
2154 |
1 |
0 |
0 |
T129 |
34730 |
54 |
0 |
0 |
T130 |
10509 |
38 |
0 |
0 |
T132 |
5897 |
29 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1920 |
0 |
0 |
T72 |
4067 |
7 |
0 |
0 |
T88 |
65980 |
62 |
0 |
0 |
T91 |
10758 |
10 |
0 |
0 |
T92 |
95649 |
144 |
0 |
0 |
T106 |
14699 |
21 |
0 |
0 |
T109 |
76071 |
548 |
0 |
0 |
T111 |
2154 |
10 |
0 |
0 |
T129 |
34730 |
55 |
0 |
0 |
T130 |
10509 |
6 |
0 |
0 |
T132 |
5897 |
20 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1778 |
0 |
0 |
T72 |
4067 |
4 |
0 |
0 |
T88 |
65980 |
68 |
0 |
0 |
T91 |
10758 |
16 |
0 |
0 |
T92 |
95649 |
93 |
0 |
0 |
T106 |
14699 |
22 |
0 |
0 |
T109 |
76071 |
562 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
37 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
17 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1748 |
0 |
0 |
T72 |
4067 |
11 |
0 |
0 |
T88 |
65980 |
82 |
0 |
0 |
T91 |
10758 |
11 |
0 |
0 |
T92 |
95649 |
97 |
0 |
0 |
T106 |
14699 |
31 |
0 |
0 |
T109 |
76071 |
515 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
45 |
0 |
0 |
T130 |
10509 |
17 |
0 |
0 |
T132 |
5897 |
8 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1776 |
0 |
0 |
T72 |
4067 |
15 |
0 |
0 |
T88 |
65980 |
85 |
0 |
0 |
T91 |
10758 |
15 |
0 |
0 |
T92 |
95649 |
111 |
0 |
0 |
T106 |
14699 |
18 |
0 |
0 |
T109 |
76071 |
546 |
0 |
0 |
T111 |
2154 |
8 |
0 |
0 |
T129 |
34730 |
51 |
0 |
0 |
T130 |
10509 |
7 |
0 |
0 |
T132 |
5897 |
14 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1736 |
0 |
0 |
T72 |
4067 |
17 |
0 |
0 |
T88 |
65980 |
93 |
0 |
0 |
T91 |
10758 |
10 |
0 |
0 |
T92 |
95649 |
119 |
0 |
0 |
T106 |
14699 |
31 |
0 |
0 |
T109 |
76071 |
495 |
0 |
0 |
T116 |
8928 |
2 |
0 |
0 |
T129 |
34730 |
43 |
0 |
0 |
T130 |
10509 |
9 |
0 |
0 |
T131 |
10866 |
6 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
579241311 |
1739 |
0 |
0 |
T72 |
4067 |
14 |
0 |
0 |
T88 |
65980 |
75 |
0 |
0 |
T91 |
10758 |
18 |
0 |
0 |
T92 |
95649 |
125 |
0 |
0 |
T106 |
14699 |
20 |
0 |
0 |
T109 |
76071 |
517 |
0 |
0 |
T111 |
2154 |
2 |
0 |
0 |
T129 |
34730 |
33 |
0 |
0 |
T130 |
10509 |
10 |
0 |
0 |
T132 |
5897 |
20 |
0 |
0 |