| T808 |
/workspace/coverage/default/3.spi_device_alert_test.3474368448 |
|
|
Mar 24 02:37:40 PM PDT 24 |
Mar 24 02:37:41 PM PDT 24 |
45985812 ps |
| T809 |
/workspace/coverage/default/23.spi_device_flash_mode.3589977184 |
|
|
Mar 24 02:38:56 PM PDT 24 |
Mar 24 02:39:03 PM PDT 24 |
525254634 ps |
| T810 |
/workspace/coverage/default/18.spi_device_flash_and_tpm.3800916239 |
|
|
Mar 24 02:38:37 PM PDT 24 |
Mar 24 02:41:11 PM PDT 24 |
48309771979 ps |
| T811 |
/workspace/coverage/default/5.spi_device_pass_cmd_filtering.782612266 |
|
|
Mar 24 02:37:48 PM PDT 24 |
Mar 24 02:38:11 PM PDT 24 |
31860587976 ps |
| T812 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.2221900402 |
|
|
Mar 24 02:38:33 PM PDT 24 |
Mar 24 02:38:40 PM PDT 24 |
2833725457 ps |
| T813 |
/workspace/coverage/default/48.spi_device_upload.1261810479 |
|
|
Mar 24 02:40:32 PM PDT 24 |
Mar 24 02:40:43 PM PDT 24 |
4173736061 ps |
| T814 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3349241206 |
|
|
Mar 24 02:38:41 PM PDT 24 |
Mar 24 02:38:46 PM PDT 24 |
826802702 ps |
| T815 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2842899120 |
|
|
Mar 24 02:39:37 PM PDT 24 |
Mar 24 02:39:48 PM PDT 24 |
12475240853 ps |
| T816 |
/workspace/coverage/default/1.spi_device_ram_cfg.2260767142 |
|
|
Mar 24 02:37:31 PM PDT 24 |
Mar 24 02:37:32 PM PDT 24 |
50733211 ps |
| T817 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.2559942090 |
|
|
Mar 24 02:40:29 PM PDT 24 |
Mar 24 02:40:35 PM PDT 24 |
902074602 ps |
| T818 |
/workspace/coverage/default/17.spi_device_cfg_cmd.335705151 |
|
|
Mar 24 02:38:37 PM PDT 24 |
Mar 24 02:38:45 PM PDT 24 |
1559520694 ps |
| T819 |
/workspace/coverage/default/2.spi_device_tpm_rw.2441164385 |
|
|
Mar 24 02:37:37 PM PDT 24 |
Mar 24 02:37:43 PM PDT 24 |
183225228 ps |
| T820 |
/workspace/coverage/default/44.spi_device_flash_and_tpm.3457591617 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:46:49 PM PDT 24 |
230824660674 ps |
| T821 |
/workspace/coverage/default/45.spi_device_mailbox.1588982574 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:40:32 PM PDT 24 |
688286664 ps |
| T822 |
/workspace/coverage/default/11.spi_device_ram_cfg.3239104420 |
|
|
Mar 24 02:38:07 PM PDT 24 |
Mar 24 02:38:08 PM PDT 24 |
38149155 ps |
| T823 |
/workspace/coverage/default/34.spi_device_tpm_all.824522330 |
|
|
Mar 24 02:39:35 PM PDT 24 |
Mar 24 02:40:28 PM PDT 24 |
67857118715 ps |
| T824 |
/workspace/coverage/default/35.spi_device_alert_test.1145780608 |
|
|
Mar 24 02:39:51 PM PDT 24 |
Mar 24 02:39:52 PM PDT 24 |
35081334 ps |
| T825 |
/workspace/coverage/default/24.spi_device_intercept.1849952752 |
|
|
Mar 24 02:39:07 PM PDT 24 |
Mar 24 02:39:12 PM PDT 24 |
291137634 ps |
| T826 |
/workspace/coverage/default/40.spi_device_cfg_cmd.1333023194 |
|
|
Mar 24 02:40:06 PM PDT 24 |
Mar 24 02:40:09 PM PDT 24 |
577771556 ps |
| T827 |
/workspace/coverage/default/28.spi_device_intercept.3655116577 |
|
|
Mar 24 02:39:20 PM PDT 24 |
Mar 24 02:39:24 PM PDT 24 |
255009523 ps |
| T828 |
/workspace/coverage/default/6.spi_device_upload.1005866594 |
|
|
Mar 24 02:37:50 PM PDT 24 |
Mar 24 02:38:05 PM PDT 24 |
3460454706 ps |
| T829 |
/workspace/coverage/default/12.spi_device_flash_mode.3476741062 |
|
|
Mar 24 02:38:16 PM PDT 24 |
Mar 24 02:38:33 PM PDT 24 |
1147637096 ps |
| T830 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3795840436 |
|
|
Mar 24 02:39:08 PM PDT 24 |
Mar 24 02:39:32 PM PDT 24 |
38227667265 ps |
| T831 |
/workspace/coverage/default/3.spi_device_mem_parity.645467965 |
|
|
Mar 24 02:37:39 PM PDT 24 |
Mar 24 02:37:40 PM PDT 24 |
106935079 ps |
| T832 |
/workspace/coverage/default/11.spi_device_flash_all.954891643 |
|
|
Mar 24 02:38:10 PM PDT 24 |
Mar 24 02:39:21 PM PDT 24 |
18634098877 ps |
| T252 |
/workspace/coverage/default/17.spi_device_stress_all.2484363303 |
|
|
Mar 24 02:38:38 PM PDT 24 |
Mar 24 02:40:57 PM PDT 24 |
64462668080 ps |
| T833 |
/workspace/coverage/default/16.spi_device_stress_all.2914968635 |
|
|
Mar 24 02:38:34 PM PDT 24 |
Mar 24 02:38:35 PM PDT 24 |
75267285 ps |
| T834 |
/workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1129996721 |
|
|
Mar 24 02:37:44 PM PDT 24 |
Mar 24 02:37:52 PM PDT 24 |
2326368429 ps |
| T835 |
/workspace/coverage/default/36.spi_device_upload.832392713 |
|
|
Mar 24 02:39:46 PM PDT 24 |
Mar 24 02:40:09 PM PDT 24 |
29373787501 ps |
| T836 |
/workspace/coverage/default/27.spi_device_pass_cmd_filtering.2454000640 |
|
|
Mar 24 02:39:10 PM PDT 24 |
Mar 24 02:39:17 PM PDT 24 |
825228192 ps |
| T837 |
/workspace/coverage/default/40.spi_device_pass_cmd_filtering.3769019258 |
|
|
Mar 24 02:40:00 PM PDT 24 |
Mar 24 02:40:41 PM PDT 24 |
31061306340 ps |
| T838 |
/workspace/coverage/default/7.spi_device_flash_and_tpm.3565404114 |
|
|
Mar 24 02:38:00 PM PDT 24 |
Mar 24 02:38:18 PM PDT 24 |
2627890310 ps |
| T839 |
/workspace/coverage/default/20.spi_device_upload.3103830292 |
|
|
Mar 24 02:38:44 PM PDT 24 |
Mar 24 02:38:49 PM PDT 24 |
1729610084 ps |
| T840 |
/workspace/coverage/default/42.spi_device_flash_all.2312960059 |
|
|
Mar 24 02:40:12 PM PDT 24 |
Mar 24 02:41:40 PM PDT 24 |
5265634713 ps |
| T841 |
/workspace/coverage/default/47.spi_device_stress_all.721801223 |
|
|
Mar 24 02:40:28 PM PDT 24 |
Mar 24 02:41:11 PM PDT 24 |
25948434518 ps |
| T842 |
/workspace/coverage/default/38.spi_device_tpm_all.3109199496 |
|
|
Mar 24 02:39:49 PM PDT 24 |
Mar 24 02:40:33 PM PDT 24 |
6150194128 ps |
| T843 |
/workspace/coverage/default/45.spi_device_intercept.382608251 |
|
|
Mar 24 02:40:23 PM PDT 24 |
Mar 24 02:40:28 PM PDT 24 |
1451557307 ps |
| T844 |
/workspace/coverage/default/12.spi_device_csb_read.3069634349 |
|
|
Mar 24 02:38:08 PM PDT 24 |
Mar 24 02:38:09 PM PDT 24 |
30390159 ps |
| T845 |
/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3672424457 |
|
|
Mar 24 02:37:49 PM PDT 24 |
Mar 24 02:37:57 PM PDT 24 |
5532337620 ps |
| T846 |
/workspace/coverage/default/18.spi_device_cfg_cmd.1281082792 |
|
|
Mar 24 02:38:45 PM PDT 24 |
Mar 24 02:38:50 PM PDT 24 |
3832968323 ps |
| T253 |
/workspace/coverage/default/40.spi_device_flash_all.2980411133 |
|
|
Mar 24 02:40:02 PM PDT 24 |
Mar 24 02:45:34 PM PDT 24 |
245011896906 ps |
| T847 |
/workspace/coverage/default/33.spi_device_csb_read.457292802 |
|
|
Mar 24 02:39:34 PM PDT 24 |
Mar 24 02:39:35 PM PDT 24 |
15633894 ps |
| T848 |
/workspace/coverage/default/31.spi_device_upload.96714017 |
|
|
Mar 24 02:39:25 PM PDT 24 |
Mar 24 02:39:30 PM PDT 24 |
2669256367 ps |
| T849 |
/workspace/coverage/default/4.spi_device_upload.2071645274 |
|
|
Mar 24 02:37:46 PM PDT 24 |
Mar 24 02:38:06 PM PDT 24 |
11298406205 ps |
| T850 |
/workspace/coverage/default/8.spi_device_stress_all.1497555348 |
|
|
Mar 24 02:37:59 PM PDT 24 |
Mar 24 02:38:01 PM PDT 24 |
650696196 ps |
| T851 |
/workspace/coverage/default/43.spi_device_tpm_rw.2845323662 |
|
|
Mar 24 02:40:09 PM PDT 24 |
Mar 24 02:40:11 PM PDT 24 |
523180523 ps |
| T852 |
/workspace/coverage/default/46.spi_device_cfg_cmd.3262962447 |
|
|
Mar 24 02:40:25 PM PDT 24 |
Mar 24 02:40:30 PM PDT 24 |
2666746730 ps |
| T853 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1440807614 |
|
|
Mar 24 02:37:50 PM PDT 24 |
Mar 24 02:39:07 PM PDT 24 |
11421954774 ps |
| T854 |
/workspace/coverage/default/11.spi_device_tpm_rw.1089498565 |
|
|
Mar 24 02:38:08 PM PDT 24 |
Mar 24 02:38:16 PM PDT 24 |
209363264 ps |
| T855 |
/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3020999385 |
|
|
Mar 24 02:39:55 PM PDT 24 |
Mar 24 02:40:18 PM PDT 24 |
37118101566 ps |
| T856 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.1586556644 |
|
|
Mar 24 02:40:08 PM PDT 24 |
Mar 24 02:40:08 PM PDT 24 |
14535331 ps |
| T857 |
/workspace/coverage/default/14.spi_device_tpm_rw.2521920197 |
|
|
Mar 24 02:38:19 PM PDT 24 |
Mar 24 02:38:20 PM PDT 24 |
65358574 ps |
| T858 |
/workspace/coverage/default/45.spi_device_tpm_rw.2399157040 |
|
|
Mar 24 02:40:26 PM PDT 24 |
Mar 24 02:40:28 PM PDT 24 |
93033476 ps |
| T859 |
/workspace/coverage/default/10.spi_device_tpm_sts_read.109796467 |
|
|
Mar 24 02:38:02 PM PDT 24 |
Mar 24 02:38:03 PM PDT 24 |
51106420 ps |
| T860 |
/workspace/coverage/default/5.spi_device_cfg_cmd.1025761290 |
|
|
Mar 24 02:37:47 PM PDT 24 |
Mar 24 02:37:58 PM PDT 24 |
9641913265 ps |
| T861 |
/workspace/coverage/default/45.spi_device_pass_cmd_filtering.1703073542 |
|
|
Mar 24 02:40:20 PM PDT 24 |
Mar 24 02:40:29 PM PDT 24 |
2486765758 ps |
| T237 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.878118191 |
|
|
Mar 24 02:39:06 PM PDT 24 |
Mar 24 02:39:09 PM PDT 24 |
1061034335 ps |
| T862 |
/workspace/coverage/default/16.spi_device_intercept.2266439686 |
|
|
Mar 24 02:38:31 PM PDT 24 |
Mar 24 02:38:40 PM PDT 24 |
5785932080 ps |
| T863 |
/workspace/coverage/default/19.spi_device_read_buffer_direct.154823601 |
|
|
Mar 24 02:38:40 PM PDT 24 |
Mar 24 02:38:44 PM PDT 24 |
424219534 ps |
| T864 |
/workspace/coverage/default/49.spi_device_upload.938920279 |
|
|
Mar 24 02:40:37 PM PDT 24 |
Mar 24 02:40:45 PM PDT 24 |
469202825 ps |
| T865 |
/workspace/coverage/default/18.spi_device_pass_cmd_filtering.1323940760 |
|
|
Mar 24 02:38:43 PM PDT 24 |
Mar 24 02:38:54 PM PDT 24 |
12839182911 ps |
| T243 |
/workspace/coverage/default/22.spi_device_flash_and_tpm.4256407749 |
|
|
Mar 24 02:38:52 PM PDT 24 |
Mar 24 02:42:14 PM PDT 24 |
54078719723 ps |
| T866 |
/workspace/coverage/default/12.spi_device_alert_test.681225984 |
|
|
Mar 24 02:38:11 PM PDT 24 |
Mar 24 02:38:12 PM PDT 24 |
38847407 ps |
| T867 |
/workspace/coverage/default/35.spi_device_mailbox.1289595476 |
|
|
Mar 24 02:39:44 PM PDT 24 |
Mar 24 02:40:30 PM PDT 24 |
60734186807 ps |
| T868 |
/workspace/coverage/default/37.spi_device_mailbox.2406733721 |
|
|
Mar 24 02:39:55 PM PDT 24 |
Mar 24 02:41:10 PM PDT 24 |
25810301099 ps |
| T869 |
/workspace/coverage/default/12.spi_device_flash_all.942658010 |
|
|
Mar 24 02:38:13 PM PDT 24 |
Mar 24 02:41:08 PM PDT 24 |
273458492664 ps |
| T870 |
/workspace/coverage/default/19.spi_device_mailbox.2718781053 |
|
|
Mar 24 02:38:42 PM PDT 24 |
Mar 24 02:38:52 PM PDT 24 |
21454543839 ps |
| T871 |
/workspace/coverage/default/15.spi_device_flash_and_tpm.3726851651 |
|
|
Mar 24 02:38:33 PM PDT 24 |
Mar 24 02:39:09 PM PDT 24 |
13931692819 ps |
| T872 |
/workspace/coverage/default/41.spi_device_alert_test.950089183 |
|
|
Mar 24 02:40:08 PM PDT 24 |
Mar 24 02:40:09 PM PDT 24 |
42793782 ps |
| T873 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1455056730 |
|
|
Mar 24 02:39:14 PM PDT 24 |
Mar 24 02:39:27 PM PDT 24 |
106730426350 ps |
| T874 |
/workspace/coverage/default/23.spi_device_csb_read.1682893518 |
|
|
Mar 24 02:38:58 PM PDT 24 |
Mar 24 02:38:59 PM PDT 24 |
15728941 ps |
| T875 |
/workspace/coverage/default/5.spi_device_flash_and_tpm.237851621 |
|
|
Mar 24 02:37:53 PM PDT 24 |
Mar 24 02:38:40 PM PDT 24 |
20173413793 ps |
| T876 |
/workspace/coverage/default/8.spi_device_alert_test.2804526759 |
|
|
Mar 24 02:38:00 PM PDT 24 |
Mar 24 02:38:01 PM PDT 24 |
40959548 ps |
| T877 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1225240204 |
|
|
Mar 24 02:37:53 PM PDT 24 |
Mar 24 02:38:27 PM PDT 24 |
11350747212 ps |
| T878 |
/workspace/coverage/default/11.spi_device_csb_read.217540655 |
|
|
Mar 24 02:38:03 PM PDT 24 |
Mar 24 02:38:05 PM PDT 24 |
25147423 ps |
| T879 |
/workspace/coverage/default/15.spi_device_mailbox.4239757624 |
|
|
Mar 24 02:38:25 PM PDT 24 |
Mar 24 02:38:41 PM PDT 24 |
1865352294 ps |
| T880 |
/workspace/coverage/default/34.spi_device_csb_read.1637452269 |
|
|
Mar 24 02:39:37 PM PDT 24 |
Mar 24 02:39:38 PM PDT 24 |
21009845 ps |
| T881 |
/workspace/coverage/default/9.spi_device_alert_test.4174561074 |
|
|
Mar 24 02:38:06 PM PDT 24 |
Mar 24 02:38:07 PM PDT 24 |
21873634 ps |
| T882 |
/workspace/coverage/default/2.spi_device_mem_parity.198200408 |
|
|
Mar 24 02:37:36 PM PDT 24 |
Mar 24 02:37:39 PM PDT 24 |
14627986 ps |
| T883 |
/workspace/coverage/default/42.spi_device_csb_read.2508572237 |
|
|
Mar 24 02:40:07 PM PDT 24 |
Mar 24 02:40:08 PM PDT 24 |
17290566 ps |
| T884 |
/workspace/coverage/default/16.spi_device_mailbox.2203356511 |
|
|
Mar 24 02:38:28 PM PDT 24 |
Mar 24 02:38:50 PM PDT 24 |
5924885212 ps |
| T245 |
/workspace/coverage/default/46.spi_device_stress_all.3997551711 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:41:58 PM PDT 24 |
17950285077 ps |
| T885 |
/workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1647381857 |
|
|
Mar 24 02:39:14 PM PDT 24 |
Mar 24 02:42:01 PM PDT 24 |
25818197963 ps |
| T886 |
/workspace/coverage/default/37.spi_device_csb_read.2423680421 |
|
|
Mar 24 02:39:44 PM PDT 24 |
Mar 24 02:39:45 PM PDT 24 |
24256826 ps |
| T887 |
/workspace/coverage/default/27.spi_device_tpm_sts_read.2294353867 |
|
|
Mar 24 02:39:11 PM PDT 24 |
Mar 24 02:39:12 PM PDT 24 |
41176309 ps |
| T888 |
/workspace/coverage/default/48.spi_device_tpm_rw.456553857 |
|
|
Mar 24 02:40:34 PM PDT 24 |
Mar 24 02:40:35 PM PDT 24 |
12810616 ps |
| T889 |
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.4241021079 |
|
|
Mar 24 02:37:59 PM PDT 24 |
Mar 24 02:38:06 PM PDT 24 |
8994322817 ps |
| T890 |
/workspace/coverage/default/21.spi_device_alert_test.2799168048 |
|
|
Mar 24 02:38:52 PM PDT 24 |
Mar 24 02:38:52 PM PDT 24 |
61464744 ps |
| T891 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.38390178 |
|
|
Mar 24 02:40:08 PM PDT 24 |
Mar 24 02:40:16 PM PDT 24 |
8250187737 ps |
| T892 |
/workspace/coverage/default/43.spi_device_alert_test.2144782827 |
|
|
Mar 24 02:40:14 PM PDT 24 |
Mar 24 02:40:15 PM PDT 24 |
33396343 ps |
| T893 |
/workspace/coverage/default/42.spi_device_stress_all.332736531 |
|
|
Mar 24 02:40:09 PM PDT 24 |
Mar 24 02:49:54 PM PDT 24 |
160123909567 ps |
| T894 |
/workspace/coverage/default/5.spi_device_intercept.3756393857 |
|
|
Mar 24 02:37:44 PM PDT 24 |
Mar 24 02:37:51 PM PDT 24 |
5660017549 ps |
| T895 |
/workspace/coverage/default/36.spi_device_read_buffer_direct.2294785021 |
|
|
Mar 24 02:39:46 PM PDT 24 |
Mar 24 02:39:50 PM PDT 24 |
123075436 ps |
| T896 |
/workspace/coverage/default/33.spi_device_intercept.1598978891 |
|
|
Mar 24 02:39:35 PM PDT 24 |
Mar 24 02:39:43 PM PDT 24 |
2623447239 ps |
| T897 |
/workspace/coverage/default/9.spi_device_csb_read.1684220023 |
|
|
Mar 24 02:38:00 PM PDT 24 |
Mar 24 02:38:01 PM PDT 24 |
22280130 ps |
| T898 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.3824137873 |
|
|
Mar 24 02:39:11 PM PDT 24 |
Mar 24 02:39:15 PM PDT 24 |
443935432 ps |
| T899 |
/workspace/coverage/default/22.spi_device_tpm_all.1988739404 |
|
|
Mar 24 02:38:52 PM PDT 24 |
Mar 24 02:40:09 PM PDT 24 |
26743746886 ps |
| T900 |
/workspace/coverage/default/15.spi_device_intercept.1931534150 |
|
|
Mar 24 02:38:25 PM PDT 24 |
Mar 24 02:38:29 PM PDT 24 |
493393629 ps |
| T901 |
/workspace/coverage/default/42.spi_device_cfg_cmd.3074187231 |
|
|
Mar 24 02:40:09 PM PDT 24 |
Mar 24 02:40:14 PM PDT 24 |
1423060793 ps |
| T902 |
/workspace/coverage/default/7.spi_device_upload.1513948834 |
|
|
Mar 24 02:37:52 PM PDT 24 |
Mar 24 02:38:11 PM PDT 24 |
5014097853 ps |
| T903 |
/workspace/coverage/default/13.spi_device_flash_all.3161280622 |
|
|
Mar 24 02:38:18 PM PDT 24 |
Mar 24 02:42:26 PM PDT 24 |
50497520821 ps |
| T904 |
/workspace/coverage/default/15.spi_device_cfg_cmd.1303486296 |
|
|
Mar 24 02:38:31 PM PDT 24 |
Mar 24 02:38:36 PM PDT 24 |
430546893 ps |
| T905 |
/workspace/coverage/default/24.spi_device_flash_and_tpm.3243566077 |
|
|
Mar 24 02:39:04 PM PDT 24 |
Mar 24 02:42:15 PM PDT 24 |
108286242848 ps |
| T906 |
/workspace/coverage/default/36.spi_device_tpm_all.3311462684 |
|
|
Mar 24 02:39:46 PM PDT 24 |
Mar 24 02:40:11 PM PDT 24 |
4172671735 ps |
| T907 |
/workspace/coverage/default/4.spi_device_tpm_rw.1421570654 |
|
|
Mar 24 02:37:44 PM PDT 24 |
Mar 24 02:37:46 PM PDT 24 |
810881147 ps |
| T908 |
/workspace/coverage/default/16.spi_device_cfg_cmd.834428225 |
|
|
Mar 24 02:38:33 PM PDT 24 |
Mar 24 02:38:36 PM PDT 24 |
190775415 ps |
| T909 |
/workspace/coverage/default/23.spi_device_tpm_rw.1114888467 |
|
|
Mar 24 02:38:56 PM PDT 24 |
Mar 24 02:38:59 PM PDT 24 |
505429067 ps |
| T910 |
/workspace/coverage/default/30.spi_device_intercept.2186480313 |
|
|
Mar 24 02:39:30 PM PDT 24 |
Mar 24 02:39:39 PM PDT 24 |
1889954718 ps |
| T911 |
/workspace/coverage/default/28.spi_device_flash_mode.1525626878 |
|
|
Mar 24 02:39:16 PM PDT 24 |
Mar 24 02:39:55 PM PDT 24 |
31337031901 ps |
| T912 |
/workspace/coverage/default/48.spi_device_cfg_cmd.3217201239 |
|
|
Mar 24 02:40:39 PM PDT 24 |
Mar 24 02:40:46 PM PDT 24 |
3217264926 ps |
| T913 |
/workspace/coverage/default/0.spi_device_stress_all.3738930547 |
|
|
Mar 24 02:37:23 PM PDT 24 |
Mar 24 02:37:24 PM PDT 24 |
397864241 ps |
| T914 |
/workspace/coverage/default/37.spi_device_alert_test.2518164389 |
|
|
Mar 24 02:40:02 PM PDT 24 |
Mar 24 02:40:03 PM PDT 24 |
14624230 ps |
| T915 |
/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.482827735 |
|
|
Mar 24 02:38:44 PM PDT 24 |
Mar 24 02:38:48 PM PDT 24 |
210604456 ps |
| T916 |
/workspace/coverage/default/34.spi_device_mailbox.3202673736 |
|
|
Mar 24 02:39:37 PM PDT 24 |
Mar 24 02:39:41 PM PDT 24 |
2122589974 ps |
| T917 |
/workspace/coverage/default/37.spi_device_cfg_cmd.3207066968 |
|
|
Mar 24 02:39:53 PM PDT 24 |
Mar 24 02:39:58 PM PDT 24 |
696317438 ps |
| T918 |
/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1906091 |
|
|
Mar 24 02:40:03 PM PDT 24 |
Mar 24 02:40:13 PM PDT 24 |
11605161020 ps |
| T919 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3862606998 |
|
|
Mar 24 02:38:35 PM PDT 24 |
Mar 24 02:42:09 PM PDT 24 |
27284844709 ps |
| T920 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1499110170 |
|
|
Mar 24 02:38:24 PM PDT 24 |
Mar 24 02:38:28 PM PDT 24 |
97493678 ps |
| T921 |
/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2011208770 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:40:32 PM PDT 24 |
1685379918 ps |
| T922 |
/workspace/coverage/default/14.spi_device_mailbox.2844958118 |
|
|
Mar 24 02:38:25 PM PDT 24 |
Mar 24 02:38:38 PM PDT 24 |
6066724570 ps |
| T923 |
/workspace/coverage/default/13.spi_device_mailbox.1859125590 |
|
|
Mar 24 02:38:17 PM PDT 24 |
Mar 24 02:38:32 PM PDT 24 |
8418466733 ps |
| T924 |
/workspace/coverage/default/38.spi_device_flash_mode.4204559506 |
|
|
Mar 24 02:39:57 PM PDT 24 |
Mar 24 02:40:09 PM PDT 24 |
1248929665 ps |
| T925 |
/workspace/coverage/default/0.spi_device_csb_read.627672900 |
|
|
Mar 24 02:37:25 PM PDT 24 |
Mar 24 02:37:26 PM PDT 24 |
19287017 ps |
| T926 |
/workspace/coverage/default/30.spi_device_flash_and_tpm.2096442517 |
|
|
Mar 24 02:39:27 PM PDT 24 |
Mar 24 02:40:17 PM PDT 24 |
2718593497 ps |
| T927 |
/workspace/coverage/default/32.spi_device_alert_test.1721523761 |
|
|
Mar 24 02:39:41 PM PDT 24 |
Mar 24 02:39:42 PM PDT 24 |
14755642 ps |
| T928 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.3731374229 |
|
|
Mar 24 02:37:25 PM PDT 24 |
Mar 24 02:37:29 PM PDT 24 |
2607545986 ps |
| T929 |
/workspace/coverage/default/44.spi_device_intercept.1772969796 |
|
|
Mar 24 02:40:16 PM PDT 24 |
Mar 24 02:40:19 PM PDT 24 |
445727471 ps |
| T930 |
/workspace/coverage/default/11.spi_device_cfg_cmd.3459684815 |
|
|
Mar 24 02:38:09 PM PDT 24 |
Mar 24 02:38:14 PM PDT 24 |
471527828 ps |
| T256 |
/workspace/coverage/default/1.spi_device_flash_all.337329134 |
|
|
Mar 24 02:37:32 PM PDT 24 |
Mar 24 02:40:04 PM PDT 24 |
22160669304 ps |
| T931 |
/workspace/coverage/default/46.spi_device_tpm_rw.3541284607 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:40:23 PM PDT 24 |
14149191 ps |
| T932 |
/workspace/coverage/default/17.spi_device_upload.401354136 |
|
|
Mar 24 02:38:40 PM PDT 24 |
Mar 24 02:38:43 PM PDT 24 |
436811729 ps |
| T933 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2192467455 |
|
|
Mar 24 02:39:30 PM PDT 24 |
Mar 24 02:39:57 PM PDT 24 |
8587144552 ps |
| T934 |
/workspace/coverage/default/44.spi_device_tpm_all.2150504963 |
|
|
Mar 24 02:40:13 PM PDT 24 |
Mar 24 02:40:39 PM PDT 24 |
4288276515 ps |
| T935 |
/workspace/coverage/default/1.spi_device_intercept.3066838961 |
|
|
Mar 24 02:37:30 PM PDT 24 |
Mar 24 02:37:42 PM PDT 24 |
3290930231 ps |
| T936 |
/workspace/coverage/default/2.spi_device_ram_cfg.3753843761 |
|
|
Mar 24 02:37:36 PM PDT 24 |
Mar 24 02:37:39 PM PDT 24 |
20878636 ps |
| T937 |
/workspace/coverage/default/47.spi_device_alert_test.3401949302 |
|
|
Mar 24 02:40:27 PM PDT 24 |
Mar 24 02:40:28 PM PDT 24 |
36216456 ps |
| T938 |
/workspace/coverage/default/36.spi_device_mailbox.2689405920 |
|
|
Mar 24 02:39:46 PM PDT 24 |
Mar 24 02:40:27 PM PDT 24 |
14337922423 ps |
| T939 |
/workspace/coverage/default/19.spi_device_ram_cfg.1025617058 |
|
|
Mar 24 02:38:45 PM PDT 24 |
Mar 24 02:38:46 PM PDT 24 |
15044375 ps |
| T940 |
/workspace/coverage/default/37.spi_device_flash_all.926775721 |
|
|
Mar 24 02:39:51 PM PDT 24 |
Mar 24 02:40:59 PM PDT 24 |
16349385380 ps |
| T941 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2089372432 |
|
|
Mar 24 02:38:23 PM PDT 24 |
Mar 24 02:38:38 PM PDT 24 |
9230012786 ps |
| T942 |
/workspace/coverage/default/11.spi_device_intercept.417365369 |
|
|
Mar 24 02:38:08 PM PDT 24 |
Mar 24 02:38:13 PM PDT 24 |
282147795 ps |
| T943 |
/workspace/coverage/default/10.spi_device_flash_mode.3506509575 |
|
|
Mar 24 02:38:04 PM PDT 24 |
Mar 24 02:38:18 PM PDT 24 |
6528127991 ps |
| T944 |
/workspace/coverage/default/20.spi_device_stress_all.2630425954 |
|
|
Mar 24 02:38:47 PM PDT 24 |
Mar 24 02:39:54 PM PDT 24 |
4829066117 ps |
| T945 |
/workspace/coverage/default/42.spi_device_tpm_all.3440830822 |
|
|
Mar 24 02:40:09 PM PDT 24 |
Mar 24 02:40:47 PM PDT 24 |
2473565310 ps |
| T946 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3934954010 |
|
|
Mar 24 02:40:23 PM PDT 24 |
Mar 24 02:40:44 PM PDT 24 |
32299878117 ps |
| T947 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.1592609420 |
|
|
Mar 24 02:38:20 PM PDT 24 |
Mar 24 02:38:21 PM PDT 24 |
24460292 ps |
| T948 |
/workspace/coverage/default/3.spi_device_mailbox.3551676270 |
|
|
Mar 24 02:37:41 PM PDT 24 |
Mar 24 02:37:53 PM PDT 24 |
4263958205 ps |
| T949 |
/workspace/coverage/default/46.spi_device_intercept.2063464246 |
|
|
Mar 24 02:40:28 PM PDT 24 |
Mar 24 02:40:31 PM PDT 24 |
307425071 ps |
| T950 |
/workspace/coverage/default/45.spi_device_alert_test.2763123700 |
|
|
Mar 24 02:40:19 PM PDT 24 |
Mar 24 02:40:20 PM PDT 24 |
70684869 ps |
| T951 |
/workspace/coverage/default/17.spi_device_read_buffer_direct.3284273939 |
|
|
Mar 24 02:38:40 PM PDT 24 |
Mar 24 02:38:44 PM PDT 24 |
155301367 ps |
| T952 |
/workspace/coverage/default/21.spi_device_flash_all.2086592490 |
|
|
Mar 24 02:38:47 PM PDT 24 |
Mar 24 02:39:31 PM PDT 24 |
6678725273 ps |
| T953 |
/workspace/coverage/default/49.spi_device_stress_all.3210985981 |
|
|
Mar 24 02:40:37 PM PDT 24 |
Mar 24 02:40:39 PM PDT 24 |
300135477 ps |
| T954 |
/workspace/coverage/default/0.spi_device_ram_cfg.1291766818 |
|
|
Mar 24 02:37:23 PM PDT 24 |
Mar 24 02:37:23 PM PDT 24 |
43130393 ps |
| T955 |
/workspace/coverage/default/2.spi_device_upload.2631920081 |
|
|
Mar 24 02:37:36 PM PDT 24 |
Mar 24 02:37:46 PM PDT 24 |
3009367428 ps |
| T956 |
/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2653055728 |
|
|
Mar 24 02:40:04 PM PDT 24 |
Mar 24 02:40:15 PM PDT 24 |
3947218318 ps |
| T957 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.750684348 |
|
|
Mar 24 02:38:16 PM PDT 24 |
Mar 24 02:38:18 PM PDT 24 |
277077721 ps |
| T958 |
/workspace/coverage/default/2.spi_device_mailbox.406052891 |
|
|
Mar 24 02:37:38 PM PDT 24 |
Mar 24 02:37:53 PM PDT 24 |
2835136144 ps |
| T959 |
/workspace/coverage/default/2.spi_device_cfg_cmd.4012142602 |
|
|
Mar 24 02:37:36 PM PDT 24 |
Mar 24 02:37:42 PM PDT 24 |
697352959 ps |
| T960 |
/workspace/coverage/default/48.spi_device_mailbox.4103577760 |
|
|
Mar 24 02:40:32 PM PDT 24 |
Mar 24 02:40:42 PM PDT 24 |
2666772111 ps |
| T961 |
/workspace/coverage/default/31.spi_device_intercept.1548530005 |
|
|
Mar 24 02:39:24 PM PDT 24 |
Mar 24 02:39:36 PM PDT 24 |
5611306135 ps |
| T962 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.2865029118 |
|
|
Mar 24 02:39:25 PM PDT 24 |
Mar 24 02:39:26 PM PDT 24 |
106717249 ps |
| T963 |
/workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2259102365 |
|
|
Mar 24 02:37:41 PM PDT 24 |
Mar 24 02:38:56 PM PDT 24 |
54183308494 ps |
| T964 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1927507126 |
|
|
Mar 24 02:38:18 PM PDT 24 |
Mar 24 02:38:31 PM PDT 24 |
2482694736 ps |
| T68 |
/workspace/coverage/default/2.spi_device_sec_cm.3354910002 |
|
|
Mar 24 02:37:44 PM PDT 24 |
Mar 24 02:37:45 PM PDT 24 |
155880997 ps |
| T965 |
/workspace/coverage/default/9.spi_device_tpm_sts_read.2974807060 |
|
|
Mar 24 02:37:59 PM PDT 24 |
Mar 24 02:38:01 PM PDT 24 |
232849282 ps |
| T966 |
/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2157861349 |
|
|
Mar 24 02:37:23 PM PDT 24 |
Mar 24 02:38:56 PM PDT 24 |
72410631197 ps |
| T967 |
/workspace/coverage/default/49.spi_device_csb_read.2583247331 |
|
|
Mar 24 02:40:30 PM PDT 24 |
Mar 24 02:40:31 PM PDT 24 |
43583725 ps |
| T968 |
/workspace/coverage/default/30.spi_device_tpm_rw.2769314631 |
|
|
Mar 24 02:39:24 PM PDT 24 |
Mar 24 02:39:26 PM PDT 24 |
181341308 ps |
| T969 |
/workspace/coverage/default/19.spi_device_cfg_cmd.820633120 |
|
|
Mar 24 02:38:45 PM PDT 24 |
Mar 24 02:38:50 PM PDT 24 |
3179641184 ps |
| T970 |
/workspace/coverage/default/17.spi_device_mailbox.834518985 |
|
|
Mar 24 02:38:45 PM PDT 24 |
Mar 24 02:39:21 PM PDT 24 |
55713685585 ps |
| T971 |
/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2821849092 |
|
|
Mar 24 02:39:31 PM PDT 24 |
Mar 24 02:40:35 PM PDT 24 |
20542323985 ps |
| T972 |
/workspace/coverage/default/5.spi_device_tpm_rw.2079189676 |
|
|
Mar 24 02:37:53 PM PDT 24 |
Mar 24 02:37:56 PM PDT 24 |
46187520 ps |
| T973 |
/workspace/coverage/default/44.spi_device_read_buffer_direct.1536720075 |
|
|
Mar 24 02:40:22 PM PDT 24 |
Mar 24 02:40:27 PM PDT 24 |
3028401571 ps |
| T974 |
/workspace/coverage/default/38.spi_device_cfg_cmd.1634190621 |
|
|
Mar 24 02:39:54 PM PDT 24 |
Mar 24 02:39:57 PM PDT 24 |
84046174 ps |
| T975 |
/workspace/coverage/default/17.spi_device_alert_test.2753388616 |
|
|
Mar 24 02:38:38 PM PDT 24 |
Mar 24 02:38:38 PM PDT 24 |
12520452 ps |
| T976 |
/workspace/coverage/default/33.spi_device_flash_mode.1533746288 |
|
|
Mar 24 02:39:40 PM PDT 24 |
Mar 24 02:39:45 PM PDT 24 |
388264236 ps |
| T977 |
/workspace/coverage/default/40.spi_device_flash_mode.592098834 |
|
|
Mar 24 02:40:04 PM PDT 24 |
Mar 24 02:40:13 PM PDT 24 |
1035859606 ps |
| T978 |
/workspace/coverage/default/27.spi_device_flash_and_tpm.4022462689 |
|
|
Mar 24 02:39:16 PM PDT 24 |
Mar 24 02:43:40 PM PDT 24 |
35278128007 ps |
| T979 |
/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3252393184 |
|
|
Mar 24 02:38:10 PM PDT 24 |
Mar 24 02:38:18 PM PDT 24 |
952485081 ps |
| T980 |
/workspace/coverage/default/26.spi_device_alert_test.269767767 |
|
|
Mar 24 02:39:09 PM PDT 24 |
Mar 24 02:39:10 PM PDT 24 |
14187153 ps |
| T981 |
/workspace/coverage/default/49.spi_device_alert_test.1527447620 |
|
|
Mar 24 02:40:34 PM PDT 24 |
Mar 24 02:40:34 PM PDT 24 |
13811368 ps |
| T240 |
/workspace/coverage/default/0.spi_device_flash_and_tpm.2531870186 |
|
|
Mar 24 02:37:24 PM PDT 24 |
Mar 24 02:41:48 PM PDT 24 |
69535111119 ps |
| T982 |
/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1347250382 |
|
|
Mar 24 02:39:21 PM PDT 24 |
Mar 24 02:39:24 PM PDT 24 |
489794649 ps |
| T983 |
/workspace/coverage/default/23.spi_device_alert_test.2307299240 |
|
|
Mar 24 02:39:04 PM PDT 24 |
Mar 24 02:39:05 PM PDT 24 |
24950069 ps |
| T984 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.4031647474 |
|
|
Mar 24 02:39:56 PM PDT 24 |
Mar 24 02:39:57 PM PDT 24 |
193748655 ps |
| T985 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.584280434 |
|
|
Mar 24 02:40:20 PM PDT 24 |
Mar 24 02:40:49 PM PDT 24 |
56625173732 ps |
| T986 |
/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3268886123 |
|
|
Mar 24 02:40:07 PM PDT 24 |
Mar 24 02:40:26 PM PDT 24 |
12710135244 ps |
| T987 |
/workspace/coverage/default/30.spi_device_mailbox.2541223917 |
|
|
Mar 24 02:39:19 PM PDT 24 |
Mar 24 02:39:26 PM PDT 24 |
7906445507 ps |
| T988 |
/workspace/coverage/default/46.spi_device_pass_cmd_filtering.645808692 |
|
|
Mar 24 02:40:26 PM PDT 24 |
Mar 24 02:40:33 PM PDT 24 |
1960911323 ps |
| T989 |
/workspace/coverage/default/7.spi_device_flash_mode.2990397849 |
|
|
Mar 24 02:37:54 PM PDT 24 |
Mar 24 02:38:22 PM PDT 24 |
4633317016 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2048554465 |
|
|
Mar 24 12:37:07 PM PDT 24 |
Mar 24 12:37:17 PM PDT 24 |
319892013 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1206085033 |
|
|
Mar 24 12:37:25 PM PDT 24 |
Mar 24 12:37:36 PM PDT 24 |
17780238 ps |
| T82 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1988852300 |
|
|
Mar 24 12:37:09 PM PDT 24 |
Mar 24 12:37:24 PM PDT 24 |
212018369 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1501584280 |
|
|
Mar 24 12:37:18 PM PDT 24 |
Mar 24 12:37:22 PM PDT 24 |
35638968 ps |
| T992 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.3325684223 |
|
|
Mar 24 12:38:49 PM PDT 24 |
Mar 24 12:38:50 PM PDT 24 |
37207945 ps |
| T83 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.384007480 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:17 PM PDT 24 |
388050644 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.484088900 |
|
|
Mar 24 12:37:36 PM PDT 24 |
Mar 24 12:37:38 PM PDT 24 |
106499603 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3841891083 |
|
|
Mar 24 12:37:25 PM PDT 24 |
Mar 24 12:37:33 PM PDT 24 |
1049987984 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1176760311 |
|
|
Mar 24 12:37:06 PM PDT 24 |
Mar 24 12:37:36 PM PDT 24 |
1455895464 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3618112599 |
|
|
Mar 24 12:37:04 PM PDT 24 |
Mar 24 12:37:11 PM PDT 24 |
230506217 ps |
| T994 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3023242936 |
|
|
Mar 24 12:37:16 PM PDT 24 |
Mar 24 12:37:17 PM PDT 24 |
48643685 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2346610526 |
|
|
Mar 24 12:37:13 PM PDT 24 |
Mar 24 12:37:29 PM PDT 24 |
792463258 ps |
| T88 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.135145242 |
|
|
Mar 24 12:37:17 PM PDT 24 |
Mar 24 12:37:32 PM PDT 24 |
2749282016 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.820507007 |
|
|
Mar 24 12:37:24 PM PDT 24 |
Mar 24 12:37:27 PM PDT 24 |
449263920 ps |
| T996 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3990227261 |
|
|
Mar 24 12:37:29 PM PDT 24 |
Mar 24 12:37:31 PM PDT 24 |
143635300 ps |
| T92 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1803922339 |
|
|
Mar 24 12:37:24 PM PDT 24 |
Mar 24 12:37:46 PM PDT 24 |
2517145507 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.971951261 |
|
|
Mar 24 12:37:33 PM PDT 24 |
Mar 24 12:37:51 PM PDT 24 |
1191501868 ps |
| T997 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.2834431864 |
|
|
Mar 24 12:37:38 PM PDT 24 |
Mar 24 12:37:38 PM PDT 24 |
43784463 ps |
| T998 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1199150971 |
|
|
Mar 24 12:37:43 PM PDT 24 |
Mar 24 12:37:44 PM PDT 24 |
13364106 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2623950595 |
|
|
Mar 24 12:37:24 PM PDT 24 |
Mar 24 12:37:25 PM PDT 24 |
48448499 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1729242303 |
|
|
Mar 24 12:37:19 PM PDT 24 |
Mar 24 12:37:26 PM PDT 24 |
121194091 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.723375852 |
|
|
Mar 24 12:37:30 PM PDT 24 |
Mar 24 12:37:34 PM PDT 24 |
23737716 ps |
| T91 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2665007407 |
|
|
Mar 24 12:37:30 PM PDT 24 |
Mar 24 12:37:32 PM PDT 24 |
109795038 ps |
| T110 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3752712215 |
|
|
Mar 24 12:37:14 PM PDT 24 |
Mar 24 12:37:16 PM PDT 24 |
29111932 ps |
| T89 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3173207841 |
|
|
Mar 24 12:37:34 PM PDT 24 |
Mar 24 12:37:36 PM PDT 24 |
181494242 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3142402827 |
|
|
Mar 24 12:37:01 PM PDT 24 |
Mar 24 12:37:05 PM PDT 24 |
305389862 ps |
| T1001 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.288837858 |
|
|
Mar 24 12:37:17 PM PDT 24 |
Mar 24 12:37:18 PM PDT 24 |
21646209 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.1532545925 |
|
|
Mar 24 12:37:14 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
66620085 ps |
| T1003 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3465692434 |
|
|
Mar 24 12:37:24 PM PDT 24 |
Mar 24 12:37:25 PM PDT 24 |
47253562 ps |
| T90 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.859562787 |
|
|
Mar 24 12:37:09 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
434286683 ps |
| T1004 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2358864878 |
|
|
Mar 24 12:37:14 PM PDT 24 |
Mar 24 12:37:16 PM PDT 24 |
85264142 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3531926380 |
|
|
Mar 24 12:37:18 PM PDT 24 |
Mar 24 12:37:22 PM PDT 24 |
39932560 ps |
| T112 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.948460362 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:04 PM PDT 24 |
45113130 ps |
| T106 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1275364678 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
188486200 ps |
| T94 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1903480707 |
|
|
Mar 24 12:37:10 PM PDT 24 |
Mar 24 12:37:13 PM PDT 24 |
80741943 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1933101813 |
|
|
Mar 24 12:37:16 PM PDT 24 |
Mar 24 12:37:18 PM PDT 24 |
491520988 ps |
| T93 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.85939387 |
|
|
Mar 24 12:37:35 PM PDT 24 |
Mar 24 12:37:37 PM PDT 24 |
107677578 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.409702599 |
|
|
Mar 24 12:37:38 PM PDT 24 |
Mar 24 12:37:40 PM PDT 24 |
120243623 ps |
| T114 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3273952044 |
|
|
Mar 24 12:37:12 PM PDT 24 |
Mar 24 12:37:14 PM PDT 24 |
70939760 ps |
| T101 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3026348640 |
|
|
Mar 24 12:37:05 PM PDT 24 |
Mar 24 12:37:14 PM PDT 24 |
269336645 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3559142067 |
|
|
Mar 24 12:37:16 PM PDT 24 |
Mar 24 12:37:17 PM PDT 24 |
162797171 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.289983376 |
|
|
Mar 24 12:37:03 PM PDT 24 |
Mar 24 12:37:07 PM PDT 24 |
110982957 ps |
| T1005 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1510671791 |
|
|
Mar 24 12:37:09 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
203766977 ps |
| T1006 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.650264489 |
|
|
Mar 24 12:37:07 PM PDT 24 |
Mar 24 12:37:10 PM PDT 24 |
13550029 ps |
| T1007 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.639991243 |
|
|
Mar 24 12:37:42 PM PDT 24 |
Mar 24 12:37:43 PM PDT 24 |
42727553 ps |
| T115 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1829218715 |
|
|
Mar 24 12:37:30 PM PDT 24 |
Mar 24 12:37:32 PM PDT 24 |
173611469 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.18609597 |
|
|
Mar 24 12:37:20 PM PDT 24 |
Mar 24 12:37:29 PM PDT 24 |
385906785 ps |
| T1008 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.3005997437 |
|
|
Mar 24 12:37:40 PM PDT 24 |
Mar 24 12:37:41 PM PDT 24 |
32450803 ps |
| T154 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3073203000 |
|
|
Mar 24 12:37:37 PM PDT 24 |
Mar 24 12:38:00 PM PDT 24 |
863135092 ps |
| T1009 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.936333666 |
|
|
Mar 24 12:37:02 PM PDT 24 |
Mar 24 12:37:03 PM PDT 24 |
13691467 ps |
| T130 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2623264392 |
|
|
Mar 24 12:37:26 PM PDT 24 |
Mar 24 12:37:29 PM PDT 24 |
214492758 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.800929670 |
|
|
Mar 24 12:37:19 PM PDT 24 |
Mar 24 12:37:24 PM PDT 24 |
47736053 ps |
| T131 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1936050614 |
|
|
Mar 24 12:37:16 PM PDT 24 |
Mar 24 12:37:19 PM PDT 24 |
221763671 ps |
| T102 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3141249350 |
|
|
Mar 24 12:37:15 PM PDT 24 |
Mar 24 12:37:19 PM PDT 24 |
208955924 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2091885938 |
|
|
Mar 24 12:37:21 PM PDT 24 |
Mar 24 12:37:24 PM PDT 24 |
140726853 ps |
| T1010 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1506084800 |
|
|
Mar 24 12:37:37 PM PDT 24 |
Mar 24 12:37:38 PM PDT 24 |
17694105 ps |
| T1011 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.437960678 |
|
|
Mar 24 12:37:21 PM PDT 24 |
Mar 24 12:37:31 PM PDT 24 |
1583953289 ps |
| T116 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3160760246 |
|
|
Mar 24 12:37:22 PM PDT 24 |
Mar 24 12:37:25 PM PDT 24 |
91117165 ps |
| T97 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2072941002 |
|
|
Mar 24 12:37:12 PM PDT 24 |
Mar 24 12:37:15 PM PDT 24 |
63187949 ps |
| T1012 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.1206298780 |
|
|
Mar 24 12:37:45 PM PDT 24 |
Mar 24 12:37:47 PM PDT 24 |
13899894 ps |