Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 98.36 94.43 98.61 89.36 97.09 95.82 98.22


Total test records in report: 1115
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T117 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3143146021 Mar 24 12:37:17 PM PDT 24 Mar 24 12:37:20 PM PDT 24 194042589 ps
T1013 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3779553853 Mar 24 12:37:26 PM PDT 24 Mar 24 12:37:28 PM PDT 24 62105470 ps
T1014 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2298397998 Mar 24 12:38:22 PM PDT 24 Mar 24 12:38:23 PM PDT 24 24047433 ps
T1015 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2055104668 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:12 PM PDT 24 105644652 ps
T151 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3080525335 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:36 PM PDT 24 1444384087 ps
T1016 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457705206 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:23 PM PDT 24 52946204 ps
T1017 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1948833455 Mar 24 12:37:34 PM PDT 24 Mar 24 12:37:35 PM PDT 24 21972834 ps
T1018 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3210808236 Mar 24 12:37:32 PM PDT 24 Mar 24 12:37:37 PM PDT 24 1981686159 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2297034209 Mar 24 12:37:28 PM PDT 24 Mar 24 12:37:29 PM PDT 24 41351600 ps
T1020 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2826779252 Mar 24 12:37:24 PM PDT 24 Mar 24 12:37:26 PM PDT 24 30762975 ps
T1021 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2096788958 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:14 PM PDT 24 393826587 ps
T1022 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.480067168 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:22 PM PDT 24 11792189 ps
T1023 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4264297211 Mar 24 12:37:53 PM PDT 24 Mar 24 12:37:59 PM PDT 24 13279202 ps
T1024 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1541194178 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:22 PM PDT 24 13354561 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3478823129 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:27 PM PDT 24 185081262 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.760216992 Mar 24 12:37:29 PM PDT 24 Mar 24 12:37:32 PM PDT 24 79002217 ps
T1027 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2078212902 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:10 PM PDT 24 52722731 ps
T1028 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2066626375 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:37 PM PDT 24 130602430 ps
T100 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1116300865 Mar 24 12:37:20 PM PDT 24 Mar 24 12:37:23 PM PDT 24 48044503 ps
T1029 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1646074738 Mar 24 12:37:32 PM PDT 24 Mar 24 12:37:33 PM PDT 24 57477790 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1350704109 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:24 PM PDT 24 39118887 ps
T1030 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1208714708 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:46 PM PDT 24 840179917 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2818155374 Mar 24 12:37:15 PM PDT 24 Mar 24 12:37:16 PM PDT 24 18124736 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1289342179 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:23 PM PDT 24 28940114 ps
T1033 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1072842342 Mar 24 12:37:32 PM PDT 24 Mar 24 12:37:33 PM PDT 24 37029820 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.714853566 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:22 PM PDT 24 383854273 ps
T1034 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2567950608 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:48 PM PDT 24 19236680 ps
T1035 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1348659776 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:16 PM PDT 24 712799053 ps
T1036 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2724510734 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:23 PM PDT 24 156058622 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3605990319 Mar 24 12:37:27 PM PDT 24 Mar 24 12:37:59 PM PDT 24 7431609916 ps
T1038 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.327383873 Mar 24 12:37:20 PM PDT 24 Mar 24 12:37:24 PM PDT 24 232310643 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1020048768 Mar 24 12:37:06 PM PDT 24 Mar 24 12:37:24 PM PDT 24 802743113 ps
T1040 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.780068408 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:46 PM PDT 24 362956392 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4222896633 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:22 PM PDT 24 13587842 ps
T1042 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3262225578 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:15 PM PDT 24 43475566 ps
T104 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4243419956 Mar 24 12:37:10 PM PDT 24 Mar 24 12:37:18 PM PDT 24 37997087 ps
T1043 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.785495229 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:38 PM PDT 24 20008004 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1126891823 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:39 PM PDT 24 13950975 ps
T1045 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3298320888 Mar 24 12:37:23 PM PDT 24 Mar 24 12:37:25 PM PDT 24 23787101 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4143270248 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:22 PM PDT 24 63429447 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1415398324 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:17 PM PDT 24 163931973 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2445362200 Mar 24 12:37:33 PM PDT 24 Mar 24 12:37:46 PM PDT 24 189686581 ps
T73 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1993014452 Mar 24 12:37:25 PM PDT 24 Mar 24 12:37:27 PM PDT 24 73144144 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4228769487 Mar 24 12:37:30 PM PDT 24 Mar 24 12:37:34 PM PDT 24 187203831 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3361093994 Mar 24 12:37:26 PM PDT 24 Mar 24 12:37:32 PM PDT 24 113393460 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2576705565 Mar 24 12:37:05 PM PDT 24 Mar 24 12:37:15 PM PDT 24 159005301 ps
T99 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3247738023 Mar 24 12:37:16 PM PDT 24 Mar 24 12:37:20 PM PDT 24 196847328 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.530714286 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:16 PM PDT 24 251849754 ps
T1053 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1182855033 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:20 PM PDT 24 281146860 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3446487547 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:24 PM PDT 24 268268634 ps
T1055 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1991268528 Mar 24 12:37:33 PM PDT 24 Mar 24 12:37:37 PM PDT 24 439882765 ps
T1056 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4012404208 Mar 24 12:37:34 PM PDT 24 Mar 24 12:37:35 PM PDT 24 54186554 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3675563853 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:14 PM PDT 24 108787631 ps
T1058 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3701280946 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:12 PM PDT 24 85334563 ps
T1059 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3907196750 Mar 24 12:37:25 PM PDT 24 Mar 24 12:37:26 PM PDT 24 12763523 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1306972896 Mar 24 12:37:44 PM PDT 24 Mar 24 12:37:47 PM PDT 24 43725928 ps
T1061 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2668013816 Mar 24 12:37:21 PM PDT 24 Mar 24 12:37:22 PM PDT 24 20762598 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4085985045 Mar 24 12:37:17 PM PDT 24 Mar 24 12:37:20 PM PDT 24 353943742 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3176791543 Mar 24 12:37:10 PM PDT 24 Mar 24 12:37:21 PM PDT 24 424555131 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1621477597 Mar 24 12:37:27 PM PDT 24 Mar 24 12:37:52 PM PDT 24 4293083632 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3378930877 Mar 24 12:37:12 PM PDT 24 Mar 24 12:37:13 PM PDT 24 163065369 ps
T1066 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.196704316 Mar 24 12:37:25 PM PDT 24 Mar 24 12:37:26 PM PDT 24 53768254 ps
T1067 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.411418397 Mar 24 12:37:36 PM PDT 24 Mar 24 12:37:37 PM PDT 24 13643429 ps
T1068 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.251618767 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:50 PM PDT 24 162290950 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.516546390 Mar 24 12:37:21 PM PDT 24 Mar 24 12:37:24 PM PDT 24 34472171 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2282328536 Mar 24 12:37:23 PM PDT 24 Mar 24 12:37:25 PM PDT 24 47445321 ps
T1071 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.670267836 Mar 24 12:37:21 PM PDT 24 Mar 24 12:37:44 PM PDT 24 4718117220 ps
T74 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.829384406 Mar 24 12:36:56 PM PDT 24 Mar 24 12:36:58 PM PDT 24 30324121 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3763770880 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:07 PM PDT 24 19579418 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2154635212 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:14 PM PDT 24 60396640 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1016202010 Mar 24 12:37:02 PM PDT 24 Mar 24 12:37:04 PM PDT 24 34221065 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3536164909 Mar 24 12:37:08 PM PDT 24 Mar 24 12:37:13 PM PDT 24 104660796 ps
T103 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2467862163 Mar 24 12:37:34 PM PDT 24 Mar 24 12:37:38 PM PDT 24 495247518 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4082494313 Mar 24 12:37:29 PM PDT 24 Mar 24 12:37:31 PM PDT 24 76748299 ps
T1077 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3338012346 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:25 PM PDT 24 315869788 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3248792950 Mar 24 12:37:34 PM PDT 24 Mar 24 12:37:36 PM PDT 24 77184847 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4288190766 Mar 24 12:37:24 PM PDT 24 Mar 24 12:37:28 PM PDT 24 185208697 ps
T1080 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2591195997 Mar 24 12:37:06 PM PDT 24 Mar 24 12:37:11 PM PDT 24 27769697 ps
T1081 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3058661584 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:38 PM PDT 24 17053961 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2670029127 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:13 PM PDT 24 11978128 ps
T1083 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1779090783 Mar 24 12:37:27 PM PDT 24 Mar 24 12:37:35 PM PDT 24 40244970 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4023588671 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:17 PM PDT 24 127878221 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.444816028 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:16 PM PDT 24 278945951 ps
T1086 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.875107190 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:44 PM PDT 24 29493361 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2872894695 Mar 24 12:37:30 PM PDT 24 Mar 24 12:37:33 PM PDT 24 291947667 ps
T1088 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2753685677 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:54 PM PDT 24 53734490 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3536819340 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:16 PM PDT 24 81072773 ps
T1090 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1710991292 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:47 PM PDT 24 17679366 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4130700866 Mar 24 12:37:12 PM PDT 24 Mar 24 12:37:16 PM PDT 24 297171319 ps
T1092 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1916676312 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:25 PM PDT 24 895783373 ps
T1093 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1744592816 Mar 24 12:37:30 PM PDT 24 Mar 24 12:37:31 PM PDT 24 18110258 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1277060111 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:20 PM PDT 24 303450492 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3677812860 Mar 24 12:37:38 PM PDT 24 Mar 24 12:38:00 PM PDT 24 822162279 ps
T1096 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3397374583 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:41 PM PDT 24 70480001 ps
T1097 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1736663819 Mar 24 12:37:33 PM PDT 24 Mar 24 12:37:34 PM PDT 24 14988673 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3591865563 Mar 24 12:37:24 PM PDT 24 Mar 24 12:37:25 PM PDT 24 17947760 ps
T1099 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1966591940 Mar 24 12:37:49 PM PDT 24 Mar 24 12:37:51 PM PDT 24 44012607 ps
T153 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2632712922 Mar 24 12:37:35 PM PDT 24 Mar 24 12:37:50 PM PDT 24 562347656 ps
T1100 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1489442464 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:38 PM PDT 24 66961985 ps
T1101 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2704339234 Mar 24 12:37:36 PM PDT 24 Mar 24 12:37:37 PM PDT 24 14488314 ps
T1102 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1074196578 Mar 24 12:37:13 PM PDT 24 Mar 24 12:37:14 PM PDT 24 20903705 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1294090315 Mar 24 12:37:25 PM PDT 24 Mar 24 12:37:44 PM PDT 24 1318595484 ps
T1104 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1880199705 Mar 24 12:37:46 PM PDT 24 Mar 24 12:37:48 PM PDT 24 14074904 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3436898695 Mar 24 12:37:11 PM PDT 24 Mar 24 12:37:13 PM PDT 24 68505746 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.372294575 Mar 24 12:37:35 PM PDT 24 Mar 24 12:37:38 PM PDT 24 161273605 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3900921831 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:20 PM PDT 24 106212233 ps
T1108 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.219091443 Mar 24 12:37:04 PM PDT 24 Mar 24 12:37:12 PM PDT 24 52223923 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1402792958 Mar 24 12:37:09 PM PDT 24 Mar 24 12:37:30 PM PDT 24 1188807504 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2383390400 Mar 24 12:37:41 PM PDT 24 Mar 24 12:37:46 PM PDT 24 117379797 ps
T1111 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2008951007 Mar 24 12:37:03 PM PDT 24 Mar 24 12:37:06 PM PDT 24 71867947 ps
T1112 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.909635648 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:23 PM PDT 24 216258534 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2887722406 Mar 24 12:37:29 PM PDT 24 Mar 24 12:37:41 PM PDT 24 124351081 ps
T1114 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2055897375 Mar 24 12:37:14 PM PDT 24 Mar 24 12:37:29 PM PDT 24 2457374196 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1569838118 Mar 24 12:37:30 PM PDT 24 Mar 24 12:37:32 PM PDT 24 69620233 ps
T152 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1536769469 Mar 24 12:37:23 PM PDT 24 Mar 24 12:37:37 PM PDT 24 2302164355 ps

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.784130277
Short name T8
Test name
Test status
Simulation time 332638582177 ps
CPU time 402.67 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:46:43 PM PDT 24
Peak memory 264248 kb
Host smart-6e505e38-555b-4cc2-9ed7-001ac4eac6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784130277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.784130277
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3114057914
Short name T44
Test name
Test status
Simulation time 45589863022 ps
CPU time 452.36 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:46:43 PM PDT 24
Peak memory 298060 kb
Host smart-3f27dfd8-f6bf-4bfc-a708-c6ce92509516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114057914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3114057914
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2871947887
Short name T43
Test name
Test status
Simulation time 318952901443 ps
CPU time 565.26 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 263868 kb
Host smart-62b5810a-f96f-4625-88e8-6deea4acef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871947887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2871947887
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1803922339
Short name T92
Test name
Test status
Simulation time 2517145507 ps
CPU time 21.85 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 215132 kb
Host smart-81dada5e-e91a-4c32-8c36-1cbc0d95a0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803922339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1803922339
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2165904347
Short name T27
Test name
Test status
Simulation time 13642459278 ps
CPU time 139.07 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 267396 kb
Host smart-4e30ef5f-c865-4aa4-a63b-d67d325271c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165904347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2165904347
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3119367107
Short name T158
Test name
Test status
Simulation time 197564661119 ps
CPU time 690.2 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:52:07 PM PDT 24
Peak memory 269472 kb
Host smart-664cc3d2-82e0-4bd0-8e35-76fcb21dde0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119367107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3119367107
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.4174686169
Short name T64
Test name
Test status
Simulation time 16324930 ps
CPU time 0.77 seconds
Started Mar 24 02:38:03 PM PDT 24
Finished Mar 24 02:38:04 PM PDT 24
Peak memory 215908 kb
Host smart-35e2f4cf-67f5-4008-8515-e0e1f8d5b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174686169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.4174686169
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3292323882
Short name T134
Test name
Test status
Simulation time 57363121707 ps
CPU time 204.32 seconds
Started Mar 24 02:40:23 PM PDT 24
Finished Mar 24 02:43:47 PM PDT 24
Peak memory 264196 kb
Host smart-d694c337-2ade-4825-9f92-5530c6cfc397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292323882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3292323882
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1729242303
Short name T85
Test name
Test status
Simulation time 121194091 ps
CPU time 4.79 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:26 PM PDT 24
Peak memory 217228 kb
Host smart-7f6e4e55-30c9-4dc0-9364-72a1f1bc0bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729242303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1729242303
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3550732169
Short name T34
Test name
Test status
Simulation time 191818301812 ps
CPU time 351.03 seconds
Started Mar 24 02:40:32 PM PDT 24
Finished Mar 24 02:46:23 PM PDT 24
Peak memory 263524 kb
Host smart-74c1fabb-bf76-4ee9-9e33-e47409ab0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550732169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3550732169
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1329001608
Short name T125
Test name
Test status
Simulation time 3153985023 ps
CPU time 27.4 seconds
Started Mar 24 02:39:48 PM PDT 24
Finished Mar 24 02:40:16 PM PDT 24
Peak memory 228612 kb
Host smart-6135d773-1b31-4416-8f5b-f638ebadd1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329001608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1329001608
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.208462143
Short name T54
Test name
Test status
Simulation time 104215712 ps
CPU time 1.05 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 235232 kb
Host smart-606d1545-7a84-4ec5-8407-479bd5362a13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208462143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.208462143
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.347331528
Short name T173
Test name
Test status
Simulation time 33703902057 ps
CPU time 181.74 seconds
Started Mar 24 02:38:50 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 270468 kb
Host smart-f8fb6a71-b012-4492-bd0f-6a5fa1f33016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347331528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.347331528
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2548317939
Short name T15
Test name
Test status
Simulation time 10929105370 ps
CPU time 54.11 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 250656 kb
Host smart-2cec967a-2923-4f65-9ce9-415b220a15bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548317939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2548317939
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3559142067
Short name T72
Test name
Test status
Simulation time 162797171 ps
CPU time 1.43 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 206128 kb
Host smart-fad75ad5-01a3-4c14-a6a9-31582a727929
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559142067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3559142067
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2641243827
Short name T13
Test name
Test status
Simulation time 123802305067 ps
CPU time 85.15 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 260556 kb
Host smart-aae92d60-f96f-4666-91a9-1d98e7fee4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641243827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2641243827
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2014803003
Short name T225
Test name
Test status
Simulation time 417310128517 ps
CPU time 682.69 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:49:41 PM PDT 24
Peak memory 266380 kb
Host smart-3fc893dd-621b-4a89-b4e1-a34ff65b6a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014803003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2014803003
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2214549692
Short name T25
Test name
Test status
Simulation time 34398081 ps
CPU time 1.04 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 216220 kb
Host smart-297bd0b9-f398-44b3-b27d-83d03a12473f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214549692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2214549692
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2762502792
Short name T62
Test name
Test status
Simulation time 21679069298 ps
CPU time 195.48 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:41:33 PM PDT 24
Peak memory 254192 kb
Host smart-2ed66eb5-0eb2-4122-a171-e11c25a9d6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762502792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2762502792
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3099185113
Short name T227
Test name
Test status
Simulation time 94856601428 ps
CPU time 192.78 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:42:19 PM PDT 24
Peak memory 281608 kb
Host smart-c2dcbdbf-831e-4b54-9b37-e93086e38610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099185113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3099185113
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3130364651
Short name T2
Test name
Test status
Simulation time 20035800 ps
CPU time 0.73 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 204828 kb
Host smart-9b93b54d-4942-44d2-9eac-3c887baa85ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130364651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3130364651
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1541699206
Short name T249
Test name
Test status
Simulation time 68173087235 ps
CPU time 406.34 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:45:13 PM PDT 24
Peak memory 271700 kb
Host smart-0723bcb7-f5ba-48fb-8188-9565d3211eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541699206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1541699206
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3862507138
Short name T156
Test name
Test status
Simulation time 13277703772 ps
CPU time 82.29 seconds
Started Mar 24 02:39:32 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 268512 kb
Host smart-6d6fd8ea-4e5c-4e04-b7bc-ccf9edb05488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862507138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3862507138
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.803305102
Short name T18
Test name
Test status
Simulation time 84786174408 ps
CPU time 56.02 seconds
Started Mar 24 02:38:39 PM PDT 24
Finished Mar 24 02:39:35 PM PDT 24
Peak memory 216040 kb
Host smart-f2e37c8f-9b08-4b24-97ae-75de2392142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803305102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.803305102
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3462385450
Short name T182
Test name
Test status
Simulation time 23280757120 ps
CPU time 152.22 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:41:17 PM PDT 24
Peak memory 272300 kb
Host smart-12eece10-7400-4b1a-9323-65449477c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462385450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3462385450
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1903480707
Short name T94
Test name
Test status
Simulation time 80741943 ps
CPU time 1.54 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 215040 kb
Host smart-7e32b402-344b-4e73-97b9-4b40dbdb055e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903480707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
903480707
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2335630255
Short name T170
Test name
Test status
Simulation time 6135149351 ps
CPU time 60.57 seconds
Started Mar 24 02:39:36 PM PDT 24
Finished Mar 24 02:40:37 PM PDT 24
Peak memory 248784 kb
Host smart-e2b8286d-427a-4526-891a-9932d6f48342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335630255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2335630255
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2484363303
Short name T252
Test name
Test status
Simulation time 64462668080 ps
CPU time 139.53 seconds
Started Mar 24 02:38:38 PM PDT 24
Finished Mar 24 02:40:57 PM PDT 24
Peak memory 256072 kb
Host smart-877a46e9-9e26-4fc8-b068-ef9490d43263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484363303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2484363303
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3080525335
Short name T151
Test name
Test status
Simulation time 1444384087 ps
CPU time 15.13 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 215040 kb
Host smart-49f4584b-c4f5-4a31-a641-0e9fe8f6035e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080525335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3080525335
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1683002574
Short name T231
Test name
Test status
Simulation time 65214500766 ps
CPU time 521.41 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:48:23 PM PDT 24
Peak memory 288260 kb
Host smart-9e8c1af2-a962-4376-b967-d3e7e027a7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683002574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1683002574
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2559786936
Short name T61
Test name
Test status
Simulation time 46664354045 ps
CPU time 284.9 seconds
Started Mar 24 02:39:55 PM PDT 24
Finished Mar 24 02:44:40 PM PDT 24
Peak memory 258584 kb
Host smart-c0f68237-a9c6-413d-bf3b-c1e93f745b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559786936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2559786936
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.451179489
Short name T596
Test name
Test status
Simulation time 9824717010 ps
CPU time 25.09 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 235636 kb
Host smart-5e6c20e9-2feb-4530-9ded-1cd5acbe2402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451179489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.451179489
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2324849017
Short name T244
Test name
Test status
Simulation time 6085745023 ps
CPU time 140.76 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 268196 kb
Host smart-7e22bd94-0e3d-4977-912c-68fcf46b4e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324849017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2324849017
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4208315189
Short name T172
Test name
Test status
Simulation time 47900757483 ps
CPU time 359.74 seconds
Started Mar 24 02:38:15 PM PDT 24
Finished Mar 24 02:44:15 PM PDT 24
Peak memory 255440 kb
Host smart-18578321-eaf7-49e9-a7bf-75c9d9cae637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208315189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4208315189
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1539388122
Short name T165
Test name
Test status
Simulation time 766815048199 ps
CPU time 693.28 seconds
Started Mar 24 02:39:45 PM PDT 24
Finished Mar 24 02:51:19 PM PDT 24
Peak memory 281564 kb
Host smart-d30d7163-0e58-417c-8625-b5fd8551df93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539388122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1539388122
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.568935183
Short name T41
Test name
Test status
Simulation time 33658081072 ps
CPU time 30.59 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:57 PM PDT 24
Peak memory 232332 kb
Host smart-46034f7c-6464-4176-9d29-3d2b6485fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568935183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.568935183
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.85939387
Short name T93
Test name
Test status
Simulation time 107677578 ps
CPU time 2.72 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 214924 kb
Host smart-be07428a-fa6c-4228-b531-fca52d192ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85939387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.85939387
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1621477597
Short name T1064
Test name
Test status
Simulation time 4293083632 ps
CPU time 24.11 seconds
Started Mar 24 12:37:27 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 215024 kb
Host smart-4145c79c-c13b-4c73-a05e-115e526524a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621477597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1621477597
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2531870186
Short name T240
Test name
Test status
Simulation time 69535111119 ps
CPU time 263.88 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:41:48 PM PDT 24
Peak memory 256100 kb
Host smart-cbb9a2f5-9a2f-42b9-9a56-db8f96f021a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531870186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2531870186
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.337329134
Short name T256
Test name
Test status
Simulation time 22160669304 ps
CPU time 151.65 seconds
Started Mar 24 02:37:32 PM PDT 24
Finished Mar 24 02:40:04 PM PDT 24
Peak memory 265104 kb
Host smart-3d536029-be25-4c83-89f0-40a53991f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337329134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.337329134
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.295005886
Short name T139
Test name
Test status
Simulation time 39321520873 ps
CPU time 396.67 seconds
Started Mar 24 02:38:10 PM PDT 24
Finished Mar 24 02:44:47 PM PDT 24
Peak memory 286852 kb
Host smart-237ebeb6-0f6e-4f0c-be4a-b661947f3b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295005886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.295005886
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1805745012
Short name T233
Test name
Test status
Simulation time 19364151162 ps
CPU time 158.75 seconds
Started Mar 24 02:38:49 PM PDT 24
Finished Mar 24 02:41:28 PM PDT 24
Peak memory 273132 kb
Host smart-eead947b-31b7-4796-b6c9-1ad592da784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805745012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1805745012
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4256407749
Short name T243
Test name
Test status
Simulation time 54078719723 ps
CPU time 201.73 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 273236 kb
Host smart-5d433b7c-ab36-4e17-9d7e-974d7dba52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256407749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4256407749
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2546188788
Short name T50
Test name
Test status
Simulation time 112243576 ps
CPU time 2.32 seconds
Started Mar 24 02:38:14 PM PDT 24
Finished Mar 24 02:38:16 PM PDT 24
Peak memory 216164 kb
Host smart-942ff66b-b006-4b4d-9451-6796fc8ee097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546188788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2546188788
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3243566077
Short name T905
Test name
Test status
Simulation time 108286242848 ps
CPU time 190.87 seconds
Started Mar 24 02:39:04 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 253460 kb
Host smart-87f33856-ca0d-48e0-b659-9350af332cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243566077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3243566077
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1779090783
Short name T1083
Test name
Test status
Simulation time 40244970 ps
CPU time 2.63 seconds
Started Mar 24 12:37:27 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 215016 kb
Host smart-961cf716-cfb6-4dff-a82c-67fa626a865e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779090783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1779090783
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2346610526
Short name T109
Test name
Test status
Simulation time 792463258 ps
CPU time 16.19 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 214844 kb
Host smart-38392cf8-6519-48a0-b130-195c0c3b5758
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346610526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2346610526
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3605990319
Short name T1037
Test name
Test status
Simulation time 7431609916 ps
CPU time 32.59 seconds
Started Mar 24 12:37:27 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 206684 kb
Host smart-b2fb8bc1-b2cb-4194-9902-e668ec7f9a1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605990319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3605990319
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4023588671
Short name T1084
Test name
Test status
Simulation time 127878221 ps
CPU time 2.72 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 217684 kb
Host smart-22e31c61-5195-4279-8d36-53dd8b4e83f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023588671 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4023588671
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1350704109
Short name T118
Test name
Test status
Simulation time 39118887 ps
CPU time 2.38 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 214800 kb
Host smart-f1f8974c-ef63-4592-ac4f-14dd0649ee0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350704109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
350704109
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.936333666
Short name T1009
Test name
Test status
Simulation time 13691467 ps
CPU time 0.71 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:03 PM PDT 24
Peak memory 202920 kb
Host smart-02c7908f-2cbb-49f0-a02f-a96b5eda68a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936333666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.936333666
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3763770880
Short name T1072
Test name
Test status
Simulation time 19579418 ps
CPU time 1.2 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:07 PM PDT 24
Peak memory 214828 kb
Host smart-9bc1b0ee-b7b6-417b-b77b-60f41e858ac9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763770880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3763770880
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1289342179
Short name T1032
Test name
Test status
Simulation time 28940114 ps
CPU time 0.62 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 202796 kb
Host smart-9f57d7b6-4887-4e30-b952-d8e1bd03c9e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289342179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1289342179
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2887722406
Short name T1113
Test name
Test status
Simulation time 124351081 ps
CPU time 1.75 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 214900 kb
Host smart-f8d3f8a8-2fe5-4e64-8c87-0a88a069e234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887722406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2887722406
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4243419956
Short name T104
Test name
Test status
Simulation time 37997087 ps
CPU time 2.54 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:18 PM PDT 24
Peak memory 214928 kb
Host smart-1448fe86-e70d-44cc-aa4a-1bfa453200b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243419956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
243419956
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1020048768
Short name T1039
Test name
Test status
Simulation time 802743113 ps
CPU time 14.42 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 206476 kb
Host smart-41f5311d-40a5-49eb-9bf3-4b018fbbb800
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020048768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1020048768
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.780068408
Short name T1040
Test name
Test status
Simulation time 362956392 ps
CPU time 23.42 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 206400 kb
Host smart-18fede6c-0389-4c4b-8019-f04d89f148f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780068408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.780068408
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.829384406
Short name T74
Test name
Test status
Simulation time 30324121 ps
CPU time 1.14 seconds
Started Mar 24 12:36:56 PM PDT 24
Finished Mar 24 12:36:58 PM PDT 24
Peak memory 206580 kb
Host smart-f5784fc2-04f9-4004-8308-7a44b2b659fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829384406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.829384406
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3026348640
Short name T101
Test name
Test status
Simulation time 269336645 ps
CPU time 4.17 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 216476 kb
Host smart-e7f96649-aeaa-4cec-958c-db101ccc4f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026348640 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3026348640
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1569838118
Short name T1115
Test name
Test status
Simulation time 69620233 ps
CPU time 2.32 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 214856 kb
Host smart-d4985c42-028f-48a7-9e16-9155387d81ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569838118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
569838118
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1306972896
Short name T1060
Test name
Test status
Simulation time 43725928 ps
CPU time 0.68 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 202920 kb
Host smart-ef6bceb6-8e8b-4482-acb9-7fee3c2c6c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306972896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
306972896
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.948460362
Short name T112
Test name
Test status
Simulation time 45113130 ps
CPU time 1.61 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 214860 kb
Host smart-1fbe7796-ed97-449d-a0cb-784e170243a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948460362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.948460362
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2818155374
Short name T1031
Test name
Test status
Simulation time 18124736 ps
CPU time 0.63 seconds
Started Mar 24 12:37:15 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 202812 kb
Host smart-e2e860fd-b074-4bbd-836c-9b0b0ad7f787
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818155374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2818155374
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3675563853
Short name T1057
Test name
Test status
Simulation time 108787631 ps
CPU time 1.76 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214836 kb
Host smart-a9419e30-9d60-4876-b50f-7b175099f19e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675563853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3675563853
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1116300865
Short name T100
Test name
Test status
Simulation time 48044503 ps
CPU time 1.82 seconds
Started Mar 24 12:37:20 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 214952 kb
Host smart-8e1723c5-ee88-4645-a33b-92d08d3ad286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116300865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
116300865
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1277060111
Short name T1094
Test name
Test status
Simulation time 303450492 ps
CPU time 7.1 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214880 kb
Host smart-399c4d2d-49dc-4ff5-b02e-e93df099d255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277060111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1277060111
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2753685677
Short name T1088
Test name
Test status
Simulation time 53734490 ps
CPU time 3.65 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 216652 kb
Host smart-7bd03867-62dd-40f5-8ffd-10ae34f49663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753685677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2753685677
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3618112599
Short name T108
Test name
Test status
Simulation time 230506217 ps
CPU time 1.89 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 206572 kb
Host smart-23bdf6df-b309-4067-be2b-1a889072ee8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618112599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3618112599
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2567950608
Short name T1034
Test name
Test status
Simulation time 19236680 ps
CPU time 0.7 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 202920 kb
Host smart-54b488b6-3c26-4616-b8bc-5aa27431a01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567950608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2567950608
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3210808236
Short name T1018
Test name
Test status
Simulation time 1981686159 ps
CPU time 4.29 seconds
Started Mar 24 12:37:32 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 215072 kb
Host smart-8c54ed8e-70a8-4fc2-bfef-ece5470ee56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210808236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3210808236
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1402792958
Short name T1109
Test name
Test status
Simulation time 1188807504 ps
CPU time 18.04 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:30 PM PDT 24
Peak memory 214880 kb
Host smart-a226553b-f6ef-4c5e-ba8a-2006372a1c62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402792958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1402792958
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1275364678
Short name T106
Test name
Test status
Simulation time 188486200 ps
CPU time 3.44 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 216224 kb
Host smart-d0829a6c-58e6-4d61-bf61-c0aab2896218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275364678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1275364678
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.444816028
Short name T1085
Test name
Test status
Simulation time 278945951 ps
CPU time 2.04 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214812 kb
Host smart-418da33f-0439-4dd9-8650-cb61a83880b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444816028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.444816028
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1206085033
Short name T990
Test name
Test status
Simulation time 17780238 ps
CPU time 0.75 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 202912 kb
Host smart-4eddb932-04dc-4a25-b065-7d29e00b25cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206085033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1206085033
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.530714286
Short name T1052
Test name
Test status
Simulation time 251849754 ps
CPU time 3.65 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214836 kb
Host smart-62a921a5-2e50-4310-a9bc-f1d40a5db838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530714286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.530714286
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3361093994
Short name T1050
Test name
Test status
Simulation time 113393460 ps
CPU time 6.31 seconds
Started Mar 24 12:37:26 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 214864 kb
Host smart-64555487-0075-4b2a-8b96-a9cf782a1643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361093994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3361093994
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3141249350
Short name T102
Test name
Test status
Simulation time 208955924 ps
CPU time 3.66 seconds
Started Mar 24 12:37:15 PM PDT 24
Finished Mar 24 12:37:19 PM PDT 24
Peak memory 217260 kb
Host smart-5017862b-6fc5-43c8-9237-ccda3b3e8eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141249350 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3141249350
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.409702599
Short name T113
Test name
Test status
Simulation time 120243623 ps
CPU time 2 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:40 PM PDT 24
Peak memory 206604 kb
Host smart-89fbebad-8a04-4753-a0cb-0949ee3b6563
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409702599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.409702599
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3023242936
Short name T994
Test name
Test status
Simulation time 48643685 ps
CPU time 0.77 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 202936 kb
Host smart-555e49c6-11f1-40d4-bfec-456dda80f56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023242936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3023242936
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.251618767
Short name T1068
Test name
Test status
Simulation time 162290950 ps
CPU time 4.04 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 214916 kb
Host smart-252f838e-797a-4ef9-afb1-021939a7b922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251618767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.251618767
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.670267836
Short name T1071
Test name
Test status
Simulation time 4718117220 ps
CPU time 21.03 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 215000 kb
Host smart-c2d9904b-6494-4667-9442-bc0277ffa20d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670267836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.670267836
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1916676312
Short name T1092
Test name
Test status
Simulation time 895783373 ps
CPU time 4.11 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 216580 kb
Host smart-c36c0c7d-a6a8-4110-8603-b2d610839ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916676312 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1916676312
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2358864878
Short name T1004
Test name
Test status
Simulation time 85264142 ps
CPU time 2.55 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214896 kb
Host smart-e620c63d-a70b-4f9e-8cef-6f052514b345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358864878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2358864878
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3058661584
Short name T1081
Test name
Test status
Simulation time 17053961 ps
CPU time 0.74 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 203224 kb
Host smart-b993bb03-08f3-4dbc-b5a4-5853ebb98dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058661584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3058661584
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4228769487
Short name T1049
Test name
Test status
Simulation time 187203831 ps
CPU time 4.08 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:34 PM PDT 24
Peak memory 216112 kb
Host smart-1f2130df-aca7-4fd7-82e6-411fd3ab637c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228769487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4228769487
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2282328536
Short name T1070
Test name
Test status
Simulation time 47445321 ps
CPU time 1.73 seconds
Started Mar 24 12:37:23 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 215048 kb
Host smart-3ee2b30a-d6c5-4776-b3d3-419fab8a42cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282328536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2282328536
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3073203000
Short name T154
Test name
Test status
Simulation time 863135092 ps
CPU time 22.48 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 214900 kb
Host smart-bc197662-f13e-4b94-85ea-720ebe504309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073203000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3073203000
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1348659776
Short name T1035
Test name
Test status
Simulation time 712799053 ps
CPU time 3.75 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 216860 kb
Host smart-390e2ff3-187b-4bca-a7c8-24dd14abedf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348659776 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1348659776
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3160760246
Short name T116
Test name
Test status
Simulation time 91117165 ps
CPU time 2.23 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 214812 kb
Host smart-d0c2c83d-deac-4f60-b8f8-6f187d7d24ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160760246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3160760246
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2066626375
Short name T1028
Test name
Test status
Simulation time 130602430 ps
CPU time 0.73 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 203192 kb
Host smart-82b0623a-765c-4ff7-8c81-df8df49109c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066626375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2066626375
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2872894695
Short name T1087
Test name
Test status
Simulation time 291947667 ps
CPU time 3.66 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 214808 kb
Host smart-8759a06b-fdcb-4d7f-94e0-95c82a522894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872894695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2872894695
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3248792950
Short name T1078
Test name
Test status
Simulation time 77184847 ps
CPU time 2.19 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 215004 kb
Host smart-2b478bcc-98d7-4812-9662-5f0e86b63256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248792950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3248792950
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1988852300
Short name T82
Test name
Test status
Simulation time 212018369 ps
CPU time 12.79 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 214924 kb
Host smart-7d990577-c20f-41ca-8202-fe5967c80878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988852300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1988852300
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2665007407
Short name T91
Test name
Test status
Simulation time 109795038 ps
CPU time 2.65 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 215916 kb
Host smart-1bc1af50-663c-4b93-8b97-989dfb3006a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665007407 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2665007407
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.516546390
Short name T1069
Test name
Test status
Simulation time 34472171 ps
CPU time 1.08 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 206568 kb
Host smart-f8cb7688-4c78-4986-948f-b9f5ad75cf96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516546390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.516546390
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1532545925
Short name T1002
Test name
Test status
Simulation time 66620085 ps
CPU time 0.7 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 203240 kb
Host smart-5b6234bb-f0fe-49c6-b7ed-acd1b9e51a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532545925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1532545925
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.820507007
Short name T995
Test name
Test status
Simulation time 449263920 ps
CPU time 2.68 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:27 PM PDT 24
Peak memory 214688 kb
Host smart-cf0366be-f855-4bac-8d07-ff5c8011d0ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820507007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.820507007
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2091885938
Short name T95
Test name
Test status
Simulation time 140726853 ps
CPU time 2.33 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 214996 kb
Host smart-3076f2d2-9c31-4ff2-884d-9da2dfdc35b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091885938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2091885938
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1182855033
Short name T1053
Test name
Test status
Simulation time 281146860 ps
CPU time 7.84 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 215272 kb
Host smart-ded535b5-79e2-4208-8400-a440b076c1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182855033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1182855033
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1208714708
Short name T1030
Test name
Test status
Simulation time 840179917 ps
CPU time 2.8 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 216000 kb
Host smart-877b969c-2025-411a-93e7-d9b7684c7e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208714708 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1208714708
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3990227261
Short name T996
Test name
Test status
Simulation time 143635300 ps
CPU time 1.77 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 206528 kb
Host smart-f36bcc0e-bcc5-4bce-9171-d8d5fad0e069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990227261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3990227261
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.785495229
Short name T1043
Test name
Test status
Simulation time 20008004 ps
CPU time 0.68 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 202944 kb
Host smart-d172f3e7-ac8c-4044-b2fd-761f8f1b8456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785495229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.785495229
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3478823129
Short name T1025
Test name
Test status
Simulation time 185081262 ps
CPU time 3.99 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:27 PM PDT 24
Peak memory 214956 kb
Host smart-2124abe9-c1a4-41a4-a61f-8e58cc056bae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478823129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3478823129
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3173207841
Short name T89
Test name
Test status
Simulation time 181494242 ps
CPU time 2.25 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 214996 kb
Host smart-13d657c8-98b8-41b0-9bb5-95e76ad80b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173207841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3173207841
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.135145242
Short name T88
Test name
Test status
Simulation time 2749282016 ps
CPU time 14.62 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 215076 kb
Host smart-b11f6e81-b173-4810-94f3-f9bfc671e9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135145242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.135145242
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2724510734
Short name T1036
Test name
Test status
Simulation time 156058622 ps
CPU time 2.73 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 216536 kb
Host smart-d7fd4e7b-8dd9-4875-b663-1a7cb9ce01aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724510734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2724510734
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3779553853
Short name T1013
Test name
Test status
Simulation time 62105470 ps
CPU time 1.54 seconds
Started Mar 24 12:37:26 PM PDT 24
Finished Mar 24 12:37:28 PM PDT 24
Peak memory 214796 kb
Host smart-8e806431-45ec-4980-b09e-29e129052642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779553853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3779553853
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3465692434
Short name T1003
Test name
Test status
Simulation time 47253562 ps
CPU time 0.72 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 202896 kb
Host smart-d9df22e3-03c5-49fe-9896-b9fd2e354bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465692434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3465692434
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.437960678
Short name T1011
Test name
Test status
Simulation time 1583953289 ps
CPU time 2.87 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 214820 kb
Host smart-888ed32a-324b-433d-a4a6-3fb1cf156048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437960678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.437960678
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.800929670
Short name T96
Test name
Test status
Simulation time 47736053 ps
CPU time 3.46 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 217132 kb
Host smart-d0230928-acb3-4c7d-ae27-458965a82569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800929670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.800929670
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2632712922
Short name T153
Test name
Test status
Simulation time 562347656 ps
CPU time 14.42 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 215208 kb
Host smart-41fc3589-2a2a-43ba-b4cd-54706d4a7938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632712922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2632712922
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.327383873
Short name T1038
Test name
Test status
Simulation time 232310643 ps
CPU time 2.47 seconds
Started Mar 24 12:37:20 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 216464 kb
Host smart-fdf5a8d6-39e4-4af4-b19e-f3040d0eb0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327383873 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.327383873
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4085985045
Short name T1062
Test name
Test status
Simulation time 353943742 ps
CPU time 1.93 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214844 kb
Host smart-2f15de8c-10f9-43bc-a782-ddb3b3983138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085985045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4085985045
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1506084800
Short name T1010
Test name
Test status
Simulation time 17694105 ps
CPU time 0.76 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 202912 kb
Host smart-e92814e0-f672-4874-a079-6e46974e6b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506084800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1506084800
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3446487547
Short name T1054
Test name
Test status
Simulation time 268268634 ps
CPU time 3.71 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:24 PM PDT 24
Peak memory 214980 kb
Host smart-b8ea73bb-d152-40a5-94f6-c58f6e31d81d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446487547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3446487547
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1991268528
Short name T1055
Test name
Test status
Simulation time 439882765 ps
CPU time 2.91 seconds
Started Mar 24 12:37:33 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 215916 kb
Host smart-ff247ce4-8943-464a-b0df-55f2367bc352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991268528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1991268528
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1646074738
Short name T1029
Test name
Test status
Simulation time 57477790 ps
CPU time 1.78 seconds
Started Mar 24 12:37:32 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 215236 kb
Host smart-5510e434-e9a6-47c8-bd38-cb7162b8f730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646074738 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1646074738
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.372294575
Short name T1106
Test name
Test status
Simulation time 161273605 ps
CPU time 2.55 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 214852 kb
Host smart-2808a035-4e3b-426d-ad82-21b41a8ce91f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372294575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.372294575
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1126891823
Short name T1044
Test name
Test status
Simulation time 13950975 ps
CPU time 0.69 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:39 PM PDT 24
Peak memory 202892 kb
Host smart-4ea3b78e-9f53-47cb-9617-9587cff60c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126891823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1126891823
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.909635648
Short name T1112
Test name
Test status
Simulation time 216258534 ps
CPU time 1.84 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 215216 kb
Host smart-3faa19e0-3bd6-44cb-bdce-0ac896cb5cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909635648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.909635648
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3397374583
Short name T1096
Test name
Test status
Simulation time 70480001 ps
CPU time 2.56 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 216028 kb
Host smart-2bcac0ac-b24b-4af4-9cb9-d5075a06037c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397374583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3397374583
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3677812860
Short name T1095
Test name
Test status
Simulation time 822162279 ps
CPU time 22.69 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 214948 kb
Host smart-eb3531ca-e838-4687-8471-0189f7f47ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677812860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3677812860
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2048554465
Short name T107
Test name
Test status
Simulation time 319892013 ps
CPU time 8 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 206660 kb
Host smart-2347dcdb-fe29-4c3e-aa4b-959ca563e0ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048554465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2048554465
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2445362200
Short name T1048
Test name
Test status
Simulation time 189686581 ps
CPU time 12.01 seconds
Started Mar 24 12:37:33 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 206420 kb
Host smart-ce8d4dcc-9be1-454f-8824-37d93b256c0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445362200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2445362200
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3536164909
Short name T1075
Test name
Test status
Simulation time 104660796 ps
CPU time 1.19 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 206660 kb
Host smart-6c5e601a-46b2-4e5b-baf9-9fdfb24284a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536164909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3536164909
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.484088900
Short name T84
Test name
Test status
Simulation time 106499603 ps
CPU time 1.68 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 214864 kb
Host smart-c8d08949-b0ce-4e87-ad80-2f3e725371f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484088900 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.484088900
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3273952044
Short name T114
Test name
Test status
Simulation time 70939760 ps
CPU time 2.09 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 214892 kb
Host smart-39f36ce4-5b78-4a0c-92e7-8c10790fa1c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273952044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
273952044
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2297034209
Short name T1019
Test name
Test status
Simulation time 41351600 ps
CPU time 0.7 seconds
Started Mar 24 12:37:28 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 202924 kb
Host smart-b2ef202d-722b-4ee1-bfec-2c6b39411ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297034209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
297034209
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3752712215
Short name T110
Test name
Test status
Simulation time 29111932 ps
CPU time 1.95 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214840 kb
Host smart-f8382761-3b52-488d-8013-e537b81b74fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752712215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3752712215
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2078212902
Short name T1027
Test name
Test status
Simulation time 52722731 ps
CPU time 0.66 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 203136 kb
Host smart-d4683346-4646-4c25-8974-7a734eec2eb4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078212902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2078212902
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3142402827
Short name T1000
Test name
Test status
Simulation time 305389862 ps
CPU time 2.75 seconds
Started Mar 24 12:37:01 PM PDT 24
Finished Mar 24 12:37:05 PM PDT 24
Peak memory 214844 kb
Host smart-e061939f-d167-4a72-ae6f-866aa9368e85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142402827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3142402827
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.289983376
Short name T98
Test name
Test status
Simulation time 110982957 ps
CPU time 2.86 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:07 PM PDT 24
Peak memory 214936 kb
Host smart-bec339cc-d1f7-4466-a0da-4194bdd8ac03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289983376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.289983376
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3900921831
Short name T1107
Test name
Test status
Simulation time 106212233 ps
CPU time 5.97 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214880 kb
Host smart-548efcd8-7549-41ea-9861-19bfb683fd06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900921831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3900921831
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.480067168
Short name T1022
Test name
Test status
Simulation time 11792189 ps
CPU time 0.75 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 202920 kb
Host smart-77a9a691-5c2d-47a7-9609-490ea4f462f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480067168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.480067168
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3298320888
Short name T1045
Test name
Test status
Simulation time 23787101 ps
CPU time 0.69 seconds
Started Mar 24 12:37:23 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 202924 kb
Host smart-bbec062f-078d-4122-b90d-c2446fd87383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298320888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3298320888
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4264297211
Short name T1023
Test name
Test status
Simulation time 13279202 ps
CPU time 0.71 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 202980 kb
Host smart-2f39d53c-3078-488b-8309-bbcf244ac432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264297211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4264297211
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.219091443
Short name T1108
Test name
Test status
Simulation time 52223923 ps
CPU time 0.72 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 202840 kb
Host smart-ced9c877-0291-41d7-acf7-d46a8bef6527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219091443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.219091443
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.196704316
Short name T1066
Test name
Test status
Simulation time 53768254 ps
CPU time 0.71 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:26 PM PDT 24
Peak memory 203252 kb
Host smart-461c58ae-a53e-463a-a282-468ed59c6ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196704316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.196704316
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3907196750
Short name T1059
Test name
Test status
Simulation time 12763523 ps
CPU time 0.69 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:26 PM PDT 24
Peak memory 202908 kb
Host smart-87fe204d-bfd6-4994-bc88-06226d5f03e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907196750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3907196750
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1736663819
Short name T1097
Test name
Test status
Simulation time 14988673 ps
CPU time 0.76 seconds
Started Mar 24 12:37:33 PM PDT 24
Finished Mar 24 12:37:34 PM PDT 24
Peak memory 203236 kb
Host smart-020fb7f9-0f35-4d04-aade-60cbe826c1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736663819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1736663819
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1206298780
Short name T1012
Test name
Test status
Simulation time 13899894 ps
CPU time 0.71 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 202932 kb
Host smart-a60de310-2f06-4820-868c-2ed2b4a0c258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206298780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1206298780
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2704339234
Short name T1101
Test name
Test status
Simulation time 14488314 ps
CPU time 0.71 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 202924 kb
Host smart-0005a090-b97e-4b28-8138-2bbf8dd927fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704339234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2704339234
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2834431864
Short name T997
Test name
Test status
Simulation time 43784463 ps
CPU time 0.68 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 202936 kb
Host smart-dbe3726a-b8e5-4c68-9af4-925f99a9d589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834431864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2834431864
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3176791543
Short name T1063
Test name
Test status
Simulation time 424555131 ps
CPU time 9.04 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:21 PM PDT 24
Peak memory 206756 kb
Host smart-2efab041-6fdf-4af5-a68c-80478d81f602
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176791543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3176791543
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1176760311
Short name T993
Test name
Test status
Simulation time 1455895464 ps
CPU time 25.84 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 206492 kb
Host smart-dcc84ca2-2524-4eab-9e16-80b2c865f9bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176760311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1176760311
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3531926380
Short name T111
Test name
Test status
Simulation time 39932560 ps
CPU time 0.95 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 206236 kb
Host smart-f33b3579-99e5-4e37-bd54-8c4be8ca9dd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531926380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3531926380
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2154635212
Short name T1073
Test name
Test status
Simulation time 60396640 ps
CPU time 3.73 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 217220 kb
Host smart-d83ee5e6-31b8-4ed4-963d-c87b89b7c02b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154635212 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2154635212
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1936050614
Short name T131
Test name
Test status
Simulation time 221763671 ps
CPU time 2.79 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:19 PM PDT 24
Peak memory 214348 kb
Host smart-e40d05ce-3048-4369-8a01-123327fca1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936050614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
936050614
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2623950595
Short name T999
Test name
Test status
Simulation time 48448499 ps
CPU time 0.71 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 203144 kb
Host smart-7975d479-3765-4096-89e0-0e1fb3d42119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623950595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
623950595
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.760216992
Short name T1026
Test name
Test status
Simulation time 79002217 ps
CPU time 2.23 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 214808 kb
Host smart-761d4bce-5e15-41fc-a5dc-7597d0166a50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760216992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.760216992
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2670029127
Short name T1082
Test name
Test status
Simulation time 11978128 ps
CPU time 0.66 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 203144 kb
Host smart-f5215cb9-96be-4da9-8762-4356132ef626
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670029127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2670029127
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2055104668
Short name T1015
Test name
Test status
Simulation time 105644652 ps
CPU time 2.85 seconds
Started Mar 24 12:37:04 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 214912 kb
Host smart-42419010-8f2a-497e-ac39-3aec7c078c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055104668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2055104668
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3841891083
Short name T87
Test name
Test status
Simulation time 1049987984 ps
CPU time 7.22 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 214880 kb
Host smart-535fad01-a930-4c2e-bc9e-a73defb61949
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841891083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3841891083
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.650264489
Short name T1006
Test name
Test status
Simulation time 13550029 ps
CPU time 0.7 seconds
Started Mar 24 12:37:07 PM PDT 24
Finished Mar 24 12:37:10 PM PDT 24
Peak memory 202924 kb
Host smart-b27e99f6-db73-4a8e-929a-f0f66cf1b0f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650264489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.650264489
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3262225578
Short name T1042
Test name
Test status
Simulation time 43475566 ps
CPU time 0.73 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 202880 kb
Host smart-cc034074-629f-41e3-8ce0-2c018e5851f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262225578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3262225578
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2298397998
Short name T1014
Test name
Test status
Simulation time 24047433 ps
CPU time 0.7 seconds
Started Mar 24 12:38:22 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 202220 kb
Host smart-c4f4f2b5-18d5-46c8-8a73-3f7e53658e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298397998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2298397998
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3325684223
Short name T992
Test name
Test status
Simulation time 37207945 ps
CPU time 0.67 seconds
Started Mar 24 12:38:49 PM PDT 24
Finished Mar 24 12:38:50 PM PDT 24
Peak memory 203160 kb
Host smart-7d9ba3a4-7c4d-4385-a0cb-88a625b1cbc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325684223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3325684223
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4012404208
Short name T1056
Test name
Test status
Simulation time 54186554 ps
CPU time 0.73 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 203244 kb
Host smart-cc033ed8-3246-40bb-9222-888b99d69a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012404208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4012404208
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1074196578
Short name T1102
Test name
Test status
Simulation time 20903705 ps
CPU time 0.69 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 202916 kb
Host smart-f9e97b37-4a43-45db-b89b-996908dbee23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074196578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1074196578
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1072842342
Short name T1033
Test name
Test status
Simulation time 37029820 ps
CPU time 0.74 seconds
Started Mar 24 12:37:32 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 202988 kb
Host smart-1d464d38-fcc1-425e-9edf-b3e773993a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072842342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1072842342
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1710991292
Short name T1090
Test name
Test status
Simulation time 17679366 ps
CPU time 0.74 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 203228 kb
Host smart-9415d54a-bc44-4a6c-8e1e-4b512681abe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710991292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1710991292
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3005997437
Short name T1008
Test name
Test status
Simulation time 32450803 ps
CPU time 0.69 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 202840 kb
Host smart-bfaf8050-19e4-44a9-b025-17c5d5f10b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005997437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3005997437
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.639991243
Short name T1007
Test name
Test status
Simulation time 42727553 ps
CPU time 0.8 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 202924 kb
Host smart-1de29ed0-a43a-4bbe-a34e-42a907d95e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639991243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.639991243
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.714853566
Short name T119
Test name
Test status
Simulation time 383854273 ps
CPU time 7.59 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 214824 kb
Host smart-53f14558-83e4-4a58-a6e0-d67928aa210a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714853566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.714853566
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1294090315
Short name T1103
Test name
Test status
Simulation time 1318595484 ps
CPU time 14.26 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 206640 kb
Host smart-b2c0ef7c-06ae-4ad1-916f-b18d8cddf03b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294090315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1294090315
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1993014452
Short name T73
Test name
Test status
Simulation time 73144144 ps
CPU time 1.17 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:27 PM PDT 24
Peak memory 206440 kb
Host smart-e2d9a784-b2ea-4487-90cc-822e6fafaca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993014452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1993014452
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2826779252
Short name T1020
Test name
Test status
Simulation time 30762975 ps
CPU time 1.82 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:26 PM PDT 24
Peak memory 214876 kb
Host smart-8bc27f79-fb2c-41aa-9472-4a0a8821b91d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826779252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2826779252
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3436898695
Short name T1105
Test name
Test status
Simulation time 68505746 ps
CPU time 1.22 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 206520 kb
Host smart-1d1e689a-d629-43be-982d-ba0fc84a6821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436898695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
436898695
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3591865563
Short name T1098
Test name
Test status
Simulation time 17947760 ps
CPU time 0.73 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 202728 kb
Host smart-72b06494-f2ec-44dc-b5f9-a742f8b03b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591865563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
591865563
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4143270248
Short name T1046
Test name
Test status
Simulation time 63429447 ps
CPU time 1.22 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 214860 kb
Host smart-08ddeddb-533d-4d53-91ed-4c5711773f2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143270248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4143270248
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1501584280
Short name T991
Test name
Test status
Simulation time 35638968 ps
CPU time 0.64 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 202776 kb
Host smart-df37648b-bffd-4742-a27b-7658d7975779
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501584280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1501584280
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4082494313
Short name T1076
Test name
Test status
Simulation time 76748299 ps
CPU time 1.81 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 214836 kb
Host smart-90dccf67-ab4a-4509-9834-c9113b565995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082494313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4082494313
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3338012346
Short name T1077
Test name
Test status
Simulation time 315869788 ps
CPU time 3.62 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:25 PM PDT 24
Peak memory 214796 kb
Host smart-3fcda785-4b59-4a48-9e66-b1bef8447f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338012346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
338012346
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.18609597
Short name T129
Test name
Test status
Simulation time 385906785 ps
CPU time 7.61 seconds
Started Mar 24 12:37:20 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 215536 kb
Host smart-6c776843-79fa-4f57-97b5-327ab6f32784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18609597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.18609597
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3701280946
Short name T1058
Test name
Test status
Simulation time 85334563 ps
CPU time 0.72 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 202916 kb
Host smart-c08eaf15-f3a1-4131-b667-112a7ddaa1cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701280946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3701280946
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2668013816
Short name T1061
Test name
Test status
Simulation time 20762598 ps
CPU time 0.69 seconds
Started Mar 24 12:37:21 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 202924 kb
Host smart-74503a90-1488-40e7-9dda-a399f0a5e2c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668013816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2668013816
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.411418397
Short name T1067
Test name
Test status
Simulation time 13643429 ps
CPU time 0.68 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 202888 kb
Host smart-20304d0e-46f7-4b3f-8711-ad84b4bac086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411418397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.411418397
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1880199705
Short name T1104
Test name
Test status
Simulation time 14074904 ps
CPU time 0.76 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 202848 kb
Host smart-362b73f5-4dfc-45e2-9bc5-a84b91fdac88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880199705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1880199705
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1966591940
Short name T1099
Test name
Test status
Simulation time 44012607 ps
CPU time 0.69 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 203228 kb
Host smart-34360f65-96e8-4314-a24b-f8de7700a0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966591940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1966591940
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1199150971
Short name T998
Test name
Test status
Simulation time 13364106 ps
CPU time 0.74 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 202928 kb
Host smart-7e3e4c14-7b72-467c-8704-da80c24704d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199150971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1199150971
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1744592816
Short name T1093
Test name
Test status
Simulation time 18110258 ps
CPU time 0.76 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 202884 kb
Host smart-bcfcf993-3c51-480f-aade-a090e4454399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744592816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1744592816
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1489442464
Short name T1100
Test name
Test status
Simulation time 66961985 ps
CPU time 0.71 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 202920 kb
Host smart-031f93a6-01bf-49c8-bb90-7fb6da782413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489442464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1489442464
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2591195997
Short name T1080
Test name
Test status
Simulation time 27769697 ps
CPU time 0.73 seconds
Started Mar 24 12:37:06 PM PDT 24
Finished Mar 24 12:37:11 PM PDT 24
Peak memory 202900 kb
Host smart-2ff78f47-a08b-4f55-9ccb-db22a7fc6cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591195997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2591195997
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.875107190
Short name T1086
Test name
Test status
Simulation time 29493361 ps
CPU time 0.68 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 202832 kb
Host smart-4c1dbf85-eb6e-4537-ac97-1cc0eedded46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875107190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.875107190
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1510671791
Short name T1005
Test name
Test status
Simulation time 203766977 ps
CPU time 3.76 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 217408 kb
Host smart-788e4176-830f-4877-81df-10c821c2f29e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510671791 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1510671791
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2008951007
Short name T1111
Test name
Test status
Simulation time 71867947 ps
CPU time 1.87 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:06 PM PDT 24
Peak memory 214804 kb
Host smart-7745103a-9cbd-4674-9b78-df84aed9ea93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008951007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
008951007
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.288837858
Short name T1001
Test name
Test status
Simulation time 21646209 ps
CPU time 0.74 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:37:18 PM PDT 24
Peak memory 202876 kb
Host smart-556b5013-eeb8-4b22-8b55-c6954febd4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288837858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.288837858
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2576705565
Short name T1051
Test name
Test status
Simulation time 159005301 ps
CPU time 3.83 seconds
Started Mar 24 12:37:05 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 214864 kb
Host smart-1ef7f5ab-665c-49c0-aa0d-d0d651f3dddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576705565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2576705565
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2383390400
Short name T1110
Test name
Test status
Simulation time 117379797 ps
CPU time 4.44 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 214948 kb
Host smart-aefb7443-bb91-4527-b181-7098ed64535d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383390400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
383390400
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2096788958
Short name T1021
Test name
Test status
Simulation time 393826587 ps
CPU time 2.53 seconds
Started Mar 24 12:37:08 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 216292 kb
Host smart-0a9b12da-5aad-4b30-8ac5-318b7a4e1be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096788958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2096788958
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1829218715
Short name T115
Test name
Test status
Simulation time 173611469 ps
CPU time 2.38 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 214856 kb
Host smart-b6d620c8-681e-4922-8990-80acc3194aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829218715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
829218715
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3378930877
Short name T1065
Test name
Test status
Simulation time 163065369 ps
CPU time 0.73 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:13 PM PDT 24
Peak memory 202920 kb
Host smart-0bab7903-2b6f-46cd-91f9-4179a3c6ec78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378930877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
378930877
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4130700866
Short name T1091
Test name
Test status
Simulation time 297171319 ps
CPU time 3.77 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 214840 kb
Host smart-6f80e1db-654a-4333-8959-783d85af1495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130700866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4130700866
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2467862163
Short name T103
Test name
Test status
Simulation time 495247518 ps
CPU time 4.22 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 214916 kb
Host smart-25c714ed-6abc-4256-9b1e-34ee1be09801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467862163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
467862163
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1536769469
Short name T152
Test name
Test status
Simulation time 2302164355 ps
CPU time 13.95 seconds
Started Mar 24 12:37:23 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 215280 kb
Host smart-b54a3c3b-b602-4378-a13e-4ae64026f9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536769469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1536769469
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.723375852
Short name T86
Test name
Test status
Simulation time 23737716 ps
CPU time 1.54 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:34 PM PDT 24
Peak memory 214816 kb
Host smart-15448659-7132-4533-9559-4e3a635fa2e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723375852 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.723375852
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1016202010
Short name T1074
Test name
Test status
Simulation time 34221065 ps
CPU time 1.26 seconds
Started Mar 24 12:37:02 PM PDT 24
Finished Mar 24 12:37:04 PM PDT 24
Peak memory 214872 kb
Host smart-0994c615-bfda-44f7-9a30-7c7acf7f62a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016202010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
016202010
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4222896633
Short name T1041
Test name
Test status
Simulation time 13587842 ps
CPU time 0.69 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 203244 kb
Host smart-3be7e61f-76da-4aad-88f9-3ef27f2ad91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222896633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
222896633
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1933101813
Short name T132
Test name
Test status
Simulation time 491520988 ps
CPU time 1.81 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:18 PM PDT 24
Peak memory 214872 kb
Host smart-d4f722a6-9e79-4f07-82a6-d96b68997dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933101813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1933101813
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2072941002
Short name T97
Test name
Test status
Simulation time 63187949 ps
CPU time 2.63 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 215964 kb
Host smart-89945819-1ee4-404e-8736-8d972a26ea0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072941002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
072941002
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2055897375
Short name T1114
Test name
Test status
Simulation time 2457374196 ps
CPU time 15.53 seconds
Started Mar 24 12:37:14 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 214972 kb
Host smart-e599f8ce-6e6a-4006-aee2-d9f5d12e8d17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055897375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2055897375
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2623264392
Short name T130
Test name
Test status
Simulation time 214492758 ps
CPU time 2.76 seconds
Started Mar 24 12:37:26 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 216188 kb
Host smart-cb684efa-617f-441f-afda-cfeb35617f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623264392 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2623264392
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1948833455
Short name T1017
Test name
Test status
Simulation time 21972834 ps
CPU time 1.24 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 214716 kb
Host smart-f7ffe45f-d753-4a7e-9480-86fa857adc04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948833455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
948833455
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1541194178
Short name T1024
Test name
Test status
Simulation time 13354561 ps
CPU time 0.71 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 203240 kb
Host smart-a1932c99-5000-46ba-8808-334a20101c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541194178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
541194178
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3457705206
Short name T1016
Test name
Test status
Simulation time 52946204 ps
CPU time 1.89 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 214872 kb
Host smart-432ebecc-8ab8-49bf-9a68-5a6d14fec14a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457705206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3457705206
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3247738023
Short name T99
Test name
Test status
Simulation time 196847328 ps
CPU time 2.96 seconds
Started Mar 24 12:37:16 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214960 kb
Host smart-2d25f4aa-8212-4013-ae46-88a1266d969e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247738023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
247738023
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.971951261
Short name T105
Test name
Test status
Simulation time 1191501868 ps
CPU time 17.56 seconds
Started Mar 24 12:37:33 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 214824 kb
Host smart-1d25a912-de31-49df-94f9-079fe7a1a766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971951261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.971951261
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4288190766
Short name T1079
Test name
Test status
Simulation time 185208697 ps
CPU time 3.21 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:28 PM PDT 24
Peak memory 216164 kb
Host smart-a558e4b3-fd99-4010-807e-73e7936ed0f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288190766 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4288190766
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3143146021
Short name T117
Test name
Test status
Simulation time 194042589 ps
CPU time 2.44 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:37:20 PM PDT 24
Peak memory 214780 kb
Host smart-d5ff801d-515f-4e06-8e7f-94ab376eed49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143146021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
143146021
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1415398324
Short name T1047
Test name
Test status
Simulation time 163931973 ps
CPU time 0.75 seconds
Started Mar 24 12:37:11 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 202916 kb
Host smart-ec4818df-6cc8-4353-9441-a1ea697b75aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415398324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
415398324
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3536819340
Short name T1089
Test name
Test status
Simulation time 81072773 ps
CPU time 2.62 seconds
Started Mar 24 12:37:13 PM PDT 24
Finished Mar 24 12:37:16 PM PDT 24
Peak memory 215160 kb
Host smart-4fb2a010-16c4-46df-b850-985543d07195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536819340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3536819340
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.859562787
Short name T90
Test name
Test status
Simulation time 434286683 ps
CPU time 3.86 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:15 PM PDT 24
Peak memory 214924 kb
Host smart-466b38b6-e106-4be4-8664-fc2fc7cd724e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859562787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.859562787
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.384007480
Short name T83
Test name
Test status
Simulation time 388050644 ps
CPU time 5.71 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:17 PM PDT 24
Peak memory 216520 kb
Host smart-45a4fd9a-66d8-40ce-b0ba-a4cfa0f2440a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384007480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.384007480
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.258985335
Short name T289
Test name
Test status
Simulation time 20622911 ps
CPU time 0.7 seconds
Started Mar 24 02:37:28 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 204292 kb
Host smart-3d5c1309-94a6-401e-9738-58f973683887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258985335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.258985335
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2043753161
Short name T571
Test name
Test status
Simulation time 1112960925 ps
CPU time 4.45 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 233700 kb
Host smart-c57c06ed-dc14-43df-9525-93dbd778e79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043753161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2043753161
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.627672900
Short name T925
Test name
Test status
Simulation time 19287017 ps
CPU time 0.86 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:26 PM PDT 24
Peak memory 205884 kb
Host smart-25cc5892-afb6-439e-8b04-e9113168d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627672900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.627672900
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3741304723
Short name T445
Test name
Test status
Simulation time 1920094516 ps
CPU time 21.03 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 236992 kb
Host smart-654ae655-85fa-4134-a241-3323c71b3b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741304723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3741304723
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2157861349
Short name T966
Test name
Test status
Simulation time 72410631197 ps
CPU time 92.9 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 232460 kb
Host smart-b89b1323-c168-4b20-8294-c9d9b95b8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157861349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2157861349
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3615438544
Short name T127
Test name
Test status
Simulation time 10327123490 ps
CPU time 46.51 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:38:11 PM PDT 24
Peak memory 237884 kb
Host smart-f5ba85fe-b540-4d51-b4a2-1d4aae4d8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615438544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3615438544
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2558434625
Short name T367
Test name
Test status
Simulation time 2054398378 ps
CPU time 4.1 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:30 PM PDT 24
Peak memory 233712 kb
Host smart-b2a863ea-c7d5-4503-9471-e79779d52992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558434625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2558434625
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1059567635
Short name T700
Test name
Test status
Simulation time 7472099817 ps
CPU time 23.53 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:47 PM PDT 24
Peak memory 237860 kb
Host smart-cc673795-c58c-4abf-b7ad-937911351722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059567635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1059567635
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3026520252
Short name T625
Test name
Test status
Simulation time 11023972385 ps
CPU time 25.27 seconds
Started Mar 24 02:37:27 PM PDT 24
Finished Mar 24 02:37:52 PM PDT 24
Peak memory 217948 kb
Host smart-3c8f55ef-89e7-458c-902e-2572d0fe388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026520252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3026520252
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1126764682
Short name T650
Test name
Test status
Simulation time 301406382 ps
CPU time 5.71 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:30 PM PDT 24
Peak memory 217368 kb
Host smart-7b2ea644-51eb-46e3-b6cd-0350456d1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126764682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1126764682
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1291766818
Short name T954
Test name
Test status
Simulation time 43130393 ps
CPU time 0.71 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:37:23 PM PDT 24
Peak memory 215860 kb
Host smart-11f12212-64d5-4e74-8733-7b70db393b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291766818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1291766818
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3731374229
Short name T928
Test name
Test status
Simulation time 2607545986 ps
CPU time 4.01 seconds
Started Mar 24 02:37:25 PM PDT 24
Finished Mar 24 02:37:29 PM PDT 24
Peak memory 222240 kb
Host smart-c0f588b7-1e7c-484a-b784-460f25e36b83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3731374229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3731374229
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3738930547
Short name T913
Test name
Test status
Simulation time 397864241 ps
CPU time 0.9 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 205896 kb
Host smart-48f7fe7b-666c-4e05-b87b-3848705e2550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738930547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3738930547
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.943739743
Short name T562
Test name
Test status
Simulation time 1943940321 ps
CPU time 28.9 seconds
Started Mar 24 02:37:26 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 216032 kb
Host smart-35e878d8-60b2-40be-bb08-db37ad5ceb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943739743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.943739743
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3478443903
Short name T16
Test name
Test status
Simulation time 388930914 ps
CPU time 2.53 seconds
Started Mar 24 02:37:24 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 215768 kb
Host smart-5fec43e6-3f74-4d59-a967-9251bb8585fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478443903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3478443903
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3278702547
Short name T406
Test name
Test status
Simulation time 134599528 ps
CPU time 1.19 seconds
Started Mar 24 02:37:26 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 215600 kb
Host smart-d7c891a4-7be1-4967-96be-45be2adb3eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278702547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3278702547
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2327928711
Short name T42
Test name
Test status
Simulation time 28985029 ps
CPU time 0.84 seconds
Started Mar 24 02:37:26 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 205272 kb
Host smart-52993815-44bc-412d-8402-29c1ee2b3c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327928711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2327928711
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.528147208
Short name T528
Test name
Test status
Simulation time 584721455 ps
CPU time 3.85 seconds
Started Mar 24 02:37:23 PM PDT 24
Finished Mar 24 02:37:27 PM PDT 24
Peak memory 232392 kb
Host smart-b637b1d0-81ca-42e4-adfa-55682f21544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528147208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.528147208
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2379774491
Short name T280
Test name
Test status
Simulation time 34994419 ps
CPU time 0.72 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 204276 kb
Host smart-c619fa6e-193e-4eb4-846a-2d3d6d2ce4d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379774491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
379774491
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3014051304
Short name T430
Test name
Test status
Simulation time 102872319 ps
CPU time 2.78 seconds
Started Mar 24 02:37:33 PM PDT 24
Finished Mar 24 02:37:36 PM PDT 24
Peak memory 218024 kb
Host smart-04b5be75-4dac-4718-ad12-0ece17d871e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014051304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3014051304
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2712573381
Short name T309
Test name
Test status
Simulation time 86229894 ps
CPU time 0.86 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 205892 kb
Host smart-222b70c8-301e-46d7-bef6-d2d0e9da528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712573381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2712573381
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1829499991
Short name T166
Test name
Test status
Simulation time 26813583596 ps
CPU time 192.7 seconds
Started Mar 24 02:37:37 PM PDT 24
Finished Mar 24 02:40:51 PM PDT 24
Peak memory 240132 kb
Host smart-20e515f1-5bca-4ed7-8eba-63becf3c77f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829499991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1829499991
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3681339270
Short name T179
Test name
Test status
Simulation time 15031514578 ps
CPU time 142.63 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 256788 kb
Host smart-99640b05-a825-4a50-ba7a-479e23965575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681339270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3681339270
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3066838961
Short name T935
Test name
Test status
Simulation time 3290930231 ps
CPU time 11.45 seconds
Started Mar 24 02:37:30 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 219496 kb
Host smart-d034bf42-dda6-4095-a39e-d06ca1b358dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066838961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3066838961
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3341340838
Short name T772
Test name
Test status
Simulation time 6404117154 ps
CPU time 9.49 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 218264 kb
Host smart-197e7e5c-f131-489f-a648-711d051551ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341340838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3341340838
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2066626580
Short name T481
Test name
Test status
Simulation time 120723406 ps
CPU time 1.05 seconds
Started Mar 24 02:37:30 PM PDT 24
Finished Mar 24 02:37:31 PM PDT 24
Peak memory 216228 kb
Host smart-bac1d6c6-cc03-4b87-869b-ad7b1c53c427
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066626580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2066626580
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.980087518
Short name T251
Test name
Test status
Simulation time 4748935355 ps
CPU time 7.16 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:38 PM PDT 24
Peak memory 232380 kb
Host smart-5c0bd987-33b9-46c3-84d7-08e005c586eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980087518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
980087518
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2925366070
Short name T162
Test name
Test status
Simulation time 10314830376 ps
CPU time 29.24 seconds
Started Mar 24 02:37:29 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 238680 kb
Host smart-737f8a43-7b44-4129-8a5d-9b21082791f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925366070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2925366070
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2260767142
Short name T816
Test name
Test status
Simulation time 50733211 ps
CPU time 0.76 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:32 PM PDT 24
Peak memory 215836 kb
Host smart-58df64c9-9416-4d69-9da4-8de6d0806d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260767142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2260767142
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2939735826
Short name T40
Test name
Test status
Simulation time 610764673 ps
CPU time 3.45 seconds
Started Mar 24 02:37:29 PM PDT 24
Finished Mar 24 02:37:33 PM PDT 24
Peak memory 221732 kb
Host smart-82c3e6db-4af6-40e6-ac69-88128a21db06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2939735826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2939735826
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3874165892
Short name T59
Test name
Test status
Simulation time 84048229 ps
CPU time 1.18 seconds
Started Mar 24 02:37:29 PM PDT 24
Finished Mar 24 02:37:31 PM PDT 24
Peak memory 235124 kb
Host smart-8bfd4a0f-1fb1-462e-a21b-510427b8480e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874165892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3874165892
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4020788822
Short name T60
Test name
Test status
Simulation time 17909064494 ps
CPU time 135.45 seconds
Started Mar 24 02:37:30 PM PDT 24
Finished Mar 24 02:39:45 PM PDT 24
Peak memory 250616 kb
Host smart-c9109992-e94c-4cb6-8bc4-846b6bce18d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020788822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4020788822
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.319975281
Short name T619
Test name
Test status
Simulation time 356572981 ps
CPU time 3.55 seconds
Started Mar 24 02:37:33 PM PDT 24
Finished Mar 24 02:37:37 PM PDT 24
Peak memory 216076 kb
Host smart-17d20d46-893b-47d6-8520-14af9ebde682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319975281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.319975281
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2564479371
Short name T293
Test name
Test status
Simulation time 9392045757 ps
CPU time 11.3 seconds
Started Mar 24 02:37:31 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 215976 kb
Host smart-05a8c985-c646-41d5-9f2c-2f4252c1ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564479371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2564479371
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4290121783
Short name T403
Test name
Test status
Simulation time 121517285 ps
CPU time 1.06 seconds
Started Mar 24 02:37:29 PM PDT 24
Finished Mar 24 02:37:30 PM PDT 24
Peak memory 206332 kb
Host smart-21237ffc-1d5f-46ab-9170-b791243c2506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290121783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4290121783
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.224321120
Short name T561
Test name
Test status
Simulation time 76031726 ps
CPU time 0.82 seconds
Started Mar 24 02:37:29 PM PDT 24
Finished Mar 24 02:37:30 PM PDT 24
Peak memory 205272 kb
Host smart-aa0cc0d4-d99a-4e1a-8d9b-48754d592feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224321120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.224321120
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4004480070
Short name T553
Test name
Test status
Simulation time 2664161351 ps
CPU time 3.9 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:40 PM PDT 24
Peak memory 217868 kb
Host smart-40e5923a-c974-471e-a969-c7a6c10c7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004480070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4004480070
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1350235375
Short name T395
Test name
Test status
Simulation time 24277907 ps
CPU time 0.7 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:38:06 PM PDT 24
Peak memory 204284 kb
Host smart-a698f41f-25f9-4dd2-8ccc-9148050179c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350235375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1350235375
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2684435082
Short name T196
Test name
Test status
Simulation time 2943351016 ps
CPU time 3.64 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:10 PM PDT 24
Peak memory 236216 kb
Host smart-db719285-076a-4bf5-873a-79c6f111ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684435082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2684435082
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.265450339
Short name T56
Test name
Test status
Simulation time 88875881 ps
CPU time 0.73 seconds
Started Mar 24 02:38:03 PM PDT 24
Finished Mar 24 02:38:04 PM PDT 24
Peak memory 205228 kb
Host smart-83211ec7-e4e0-4c79-8a17-84362bf55f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265450339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.265450339
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3330809096
Short name T482
Test name
Test status
Simulation time 9542083635 ps
CPU time 41.97 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 248772 kb
Host smart-1217a1d4-a84b-4421-abff-964aca23c94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330809096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3330809096
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.852282368
Short name T228
Test name
Test status
Simulation time 24273857922 ps
CPU time 161.29 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:40:47 PM PDT 24
Peak memory 263728 kb
Host smart-646920b2-01a7-48ee-84d9-20dd7934c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852282368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.852282368
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1842374609
Short name T704
Test name
Test status
Simulation time 87710584888 ps
CPU time 639.66 seconds
Started Mar 24 02:38:07 PM PDT 24
Finished Mar 24 02:48:47 PM PDT 24
Peak memory 248936 kb
Host smart-4e5d7eba-8394-4fbc-95ba-b6b3c39435a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842374609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1842374609
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3506509575
Short name T943
Test name
Test status
Simulation time 6528127991 ps
CPU time 13.41 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:18 PM PDT 24
Peak memory 223080 kb
Host smart-131db9b3-6ba0-43c3-a64f-e9ede0e5db4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506509575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3506509575
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.564888668
Short name T721
Test name
Test status
Simulation time 195357268 ps
CPU time 3.17 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:38:21 PM PDT 24
Peak memory 218004 kb
Host smart-f7061dbd-cc4b-4960-982f-cd374118847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564888668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.564888668
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3664193588
Short name T12
Test name
Test status
Simulation time 97923664362 ps
CPU time 35.62 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:38:41 PM PDT 24
Peak memory 248724 kb
Host smart-6940a652-15d1-4d70-af40-455f46d46c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664193588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3664193588
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3534338581
Short name T776
Test name
Test status
Simulation time 27328693 ps
CPU time 0.99 seconds
Started Mar 24 02:38:07 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 216248 kb
Host smart-ebb10c50-f16e-4af1-adf7-725d3601de38
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534338581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3534338581
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3324968649
Short name T247
Test name
Test status
Simulation time 13649960389 ps
CPU time 20.98 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 232220 kb
Host smart-5c8eb1e3-c670-420c-a119-3fa78a52c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324968649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3324968649
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3162484859
Short name T654
Test name
Test status
Simulation time 1995827426 ps
CPU time 6.36 seconds
Started Mar 24 02:38:03 PM PDT 24
Finished Mar 24 02:38:09 PM PDT 24
Peak memory 235020 kb
Host smart-402a1f99-70aa-458e-94cb-f0bfe515ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162484859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3162484859
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3662847312
Short name T656
Test name
Test status
Simulation time 3860065279 ps
CPU time 4.65 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:17 PM PDT 24
Peak memory 218772 kb
Host smart-5c71bc90-279e-4ec4-b750-64e5347872bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662847312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3662847312
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3533965058
Short name T498
Test name
Test status
Simulation time 17671817659 ps
CPU time 119.77 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 236248 kb
Host smart-19a7b6f7-bf3f-49b1-856d-a8d94fade181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533965058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3533965058
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2361161286
Short name T719
Test name
Test status
Simulation time 48704142776 ps
CPU time 47.98 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:38:53 PM PDT 24
Peak memory 215992 kb
Host smart-249bab9c-c9f6-47c9-acf5-04e37ed6a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361161286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2361161286
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.137861198
Short name T269
Test name
Test status
Simulation time 18587226231 ps
CPU time 20.43 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:25 PM PDT 24
Peak memory 216016 kb
Host smart-93edabee-17c7-494f-bc65-886de1fba7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137861198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.137861198
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1117747485
Short name T466
Test name
Test status
Simulation time 168013860 ps
CPU time 2.04 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 215940 kb
Host smart-219c1833-8863-4630-a361-b1efe3c5b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117747485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1117747485
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.109796467
Short name T859
Test name
Test status
Simulation time 51106420 ps
CPU time 0.91 seconds
Started Mar 24 02:38:02 PM PDT 24
Finished Mar 24 02:38:03 PM PDT 24
Peak memory 205244 kb
Host smart-db163455-7c4c-457f-8f25-2d502f6094d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109796467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.109796467
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2178738285
Short name T531
Test name
Test status
Simulation time 565696661 ps
CPU time 3.73 seconds
Started Mar 24 02:38:05 PM PDT 24
Finished Mar 24 02:38:09 PM PDT 24
Peak memory 232336 kb
Host smart-a23f57a9-6ba1-451e-bc81-994dd90aad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178738285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2178738285
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3811867764
Short name T334
Test name
Test status
Simulation time 15469947 ps
CPU time 0.7 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:13 PM PDT 24
Peak memory 204884 kb
Host smart-8e77f97f-7ae9-457e-a57a-b031c1518f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811867764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3811867764
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3459684815
Short name T930
Test name
Test status
Simulation time 471527828 ps
CPU time 4.89 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:14 PM PDT 24
Peak memory 219076 kb
Host smart-4496924a-143b-47cb-ae82-356297369803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459684815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3459684815
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.217540655
Short name T878
Test name
Test status
Simulation time 25147423 ps
CPU time 0.72 seconds
Started Mar 24 02:38:03 PM PDT 24
Finished Mar 24 02:38:05 PM PDT 24
Peak memory 204900 kb
Host smart-a5f3bc72-558e-4385-b648-f3bbeb792505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217540655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.217540655
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.954891643
Short name T832
Test name
Test status
Simulation time 18634098877 ps
CPU time 70.02 seconds
Started Mar 24 02:38:10 PM PDT 24
Finished Mar 24 02:39:21 PM PDT 24
Peak memory 256612 kb
Host smart-e01ab8aa-4ebf-4987-aba4-a2bb3ed669ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954891643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.954891643
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2284879089
Short name T184
Test name
Test status
Simulation time 31440009317 ps
CPU time 95.81 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 249600 kb
Host smart-996ed0ca-a0ba-4e52-bea3-8205cd57ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284879089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2284879089
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3305937804
Short name T421
Test name
Test status
Simulation time 1485916021 ps
CPU time 20.06 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:38:29 PM PDT 24
Peak memory 240232 kb
Host smart-985c3b7d-37cd-441f-9a39-a62d0bb9de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305937804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3305937804
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.417365369
Short name T942
Test name
Test status
Simulation time 282147795 ps
CPU time 5.14 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:38:13 PM PDT 24
Peak memory 236568 kb
Host smart-b3b93abb-4079-4362-832c-94d51fb09322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417365369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.417365369
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3808000272
Short name T453
Test name
Test status
Simulation time 2025249135 ps
CPU time 5.24 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:23 PM PDT 24
Peak memory 234564 kb
Host smart-74f5d1ca-e1e6-4ceb-999f-c17f4e659abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808000272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3808000272
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.841136553
Short name T514
Test name
Test status
Simulation time 98543915 ps
CPU time 1.03 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:14 PM PDT 24
Peak memory 217468 kb
Host smart-b1e00358-c53c-41a0-8b7f-7278ce6f2a2e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841136553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.841136553
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2485945738
Short name T344
Test name
Test status
Simulation time 659660270 ps
CPU time 8.97 seconds
Started Mar 24 02:38:10 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 227464 kb
Host smart-c4ce1549-e13f-4b73-9e61-c763f84dadc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485945738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2485945738
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3247888333
Short name T434
Test name
Test status
Simulation time 27614537799 ps
CPU time 20.74 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:38:29 PM PDT 24
Peak memory 230796 kb
Host smart-06fc72bc-e29f-4ab8-9a79-ab245dc982aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247888333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3247888333
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3239104420
Short name T822
Test name
Test status
Simulation time 38149155 ps
CPU time 0.75 seconds
Started Mar 24 02:38:07 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 215804 kb
Host smart-66ba072e-d886-4708-a1f9-d67d42e2c9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239104420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3239104420
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3128053232
Short name T612
Test name
Test status
Simulation time 1605460120 ps
CPU time 4.72 seconds
Started Mar 24 02:38:07 PM PDT 24
Finished Mar 24 02:38:12 PM PDT 24
Peak memory 219320 kb
Host smart-47545b40-b0b8-4889-92c9-0bc5b69dfdee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3128053232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3128053232
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.394055064
Short name T648
Test name
Test status
Simulation time 9052793109 ps
CPU time 16.99 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:27 PM PDT 24
Peak memory 216072 kb
Host smart-e62850f3-8d13-43b6-9c73-4d90809e1e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394055064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.394055064
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3252393184
Short name T979
Test name
Test status
Simulation time 952485081 ps
CPU time 7.84 seconds
Started Mar 24 02:38:10 PM PDT 24
Finished Mar 24 02:38:18 PM PDT 24
Peak memory 215928 kb
Host smart-e681e6af-36fa-4792-a546-c5f22071ba76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252393184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3252393184
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1089498565
Short name T854
Test name
Test status
Simulation time 209363264 ps
CPU time 7.92 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:38:16 PM PDT 24
Peak memory 215976 kb
Host smart-4c395b5b-9c94-432d-b9c1-ec755a9ccb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089498565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1089498565
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1278635860
Short name T356
Test name
Test status
Simulation time 382172921 ps
CPU time 1 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:10 PM PDT 24
Peak memory 205568 kb
Host smart-742a00ec-e027-4204-a33f-2f255c498ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278635860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1278635860
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2438798551
Short name T499
Test name
Test status
Simulation time 3542122155 ps
CPU time 16.72 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 233836 kb
Host smart-18784518-34f9-4cb2-ba92-aa1742be9767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438798551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2438798551
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.681225984
Short name T866
Test name
Test status
Simulation time 38847407 ps
CPU time 0.68 seconds
Started Mar 24 02:38:11 PM PDT 24
Finished Mar 24 02:38:12 PM PDT 24
Peak memory 204820 kb
Host smart-ba0d10d2-1799-4824-9a8e-d3822750fee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681225984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.681225984
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3997535279
Short name T595
Test name
Test status
Simulation time 533143984 ps
CPU time 3.97 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:16 PM PDT 24
Peak memory 224016 kb
Host smart-d5979033-4377-45f3-a92c-5a98946ac88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997535279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3997535279
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3069634349
Short name T844
Test name
Test status
Simulation time 30390159 ps
CPU time 0.77 seconds
Started Mar 24 02:38:08 PM PDT 24
Finished Mar 24 02:38:09 PM PDT 24
Peak memory 205248 kb
Host smart-33dd49e9-5db4-4801-836c-fa5c9b82bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069634349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3069634349
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.942658010
Short name T869
Test name
Test status
Simulation time 273458492664 ps
CPU time 174.4 seconds
Started Mar 24 02:38:13 PM PDT 24
Finished Mar 24 02:41:08 PM PDT 24
Peak memory 256364 kb
Host smart-0623c3d7-a7bf-433d-b442-86ba49203f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942658010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.942658010
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3147026424
Short name T512
Test name
Test status
Simulation time 43723919434 ps
CPU time 172.81 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 232464 kb
Host smart-e6272794-1e95-4551-a308-0bfebca7caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147026424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3147026424
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3476741062
Short name T829
Test name
Test status
Simulation time 1147637096 ps
CPU time 17.1 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:33 PM PDT 24
Peak memory 240332 kb
Host smart-5e435580-0e27-4bb9-84f5-ca9fd3c70f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476741062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3476741062
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3502707627
Short name T302
Test name
Test status
Simulation time 19928400308 ps
CPU time 8.55 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 232384 kb
Host smart-dcb02767-ae66-494f-823e-4d7fa28a4a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502707627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3502707627
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.273694084
Short name T379
Test name
Test status
Simulation time 416574623 ps
CPU time 1.1 seconds
Started Mar 24 02:38:11 PM PDT 24
Finished Mar 24 02:38:12 PM PDT 24
Peak memory 216240 kb
Host smart-400d6795-eb5b-4c0a-802f-c5b1020c8f65
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273694084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.273694084
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2364108514
Short name T181
Test name
Test status
Simulation time 7059176547 ps
CPU time 9.08 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:25 PM PDT 24
Peak memory 233328 kb
Host smart-bf06e74d-1479-48d6-8df1-86283be47d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364108514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2364108514
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1852479074
Short name T400
Test name
Test status
Simulation time 5159722337 ps
CPU time 9.47 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:27 PM PDT 24
Peak memory 233368 kb
Host smart-dbbba456-2f4a-430d-b6d1-fbf0597fcf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852479074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1852479074
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2970558434
Short name T639
Test name
Test status
Simulation time 29713873 ps
CPU time 0.8 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:10 PM PDT 24
Peak memory 216060 kb
Host smart-34624e2f-3ba4-4a99-b675-165fbbb79268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970558434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2970558434
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2544537370
Short name T739
Test name
Test status
Simulation time 169317138 ps
CPU time 3.44 seconds
Started Mar 24 02:38:15 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 219360 kb
Host smart-5428ee47-ab66-4d3f-b6a0-6fb2fb936057
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2544537370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2544537370
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3752423712
Short name T652
Test name
Test status
Simulation time 4256807165 ps
CPU time 34.45 seconds
Started Mar 24 02:38:15 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 239816 kb
Host smart-dc006cca-88a4-47f0-851a-41d3fee66e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752423712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3752423712
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1215120112
Short name T750
Test name
Test status
Simulation time 20136262889 ps
CPU time 38.45 seconds
Started Mar 24 02:38:15 PM PDT 24
Finished Mar 24 02:38:53 PM PDT 24
Peak memory 215976 kb
Host smart-051aa147-cde2-4d46-9c1e-2cda35cb775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215120112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1215120112
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3407019271
Short name T304
Test name
Test status
Simulation time 6403420167 ps
CPU time 16.6 seconds
Started Mar 24 02:38:09 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 215984 kb
Host smart-e987e84b-4ff4-4398-aa77-b6b400ee95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407019271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3407019271
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1432318342
Short name T375
Test name
Test status
Simulation time 281874566 ps
CPU time 4.6 seconds
Started Mar 24 02:38:13 PM PDT 24
Finished Mar 24 02:38:18 PM PDT 24
Peak memory 216072 kb
Host smart-b33a7bec-cc17-49e4-a4ec-69c0ff143822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432318342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1432318342
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2812612188
Short name T417
Test name
Test status
Simulation time 174136114 ps
CPU time 1.03 seconds
Started Mar 24 02:38:11 PM PDT 24
Finished Mar 24 02:38:12 PM PDT 24
Peak memory 206276 kb
Host smart-4ab520f4-a0f5-4cb0-a5b1-5c795695a6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812612188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2812612188
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1087203961
Short name T286
Test name
Test status
Simulation time 86747400 ps
CPU time 2.78 seconds
Started Mar 24 02:38:13 PM PDT 24
Finished Mar 24 02:38:16 PM PDT 24
Peak memory 233228 kb
Host smart-71d2d25e-ba22-4679-8111-d07d1686b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087203961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1087203961
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2958881448
Short name T509
Test name
Test status
Simulation time 37575778 ps
CPU time 0.71 seconds
Started Mar 24 02:38:20 PM PDT 24
Finished Mar 24 02:38:21 PM PDT 24
Peak memory 204276 kb
Host smart-e5704dad-96af-47b9-b8a8-a12190835414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958881448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2958881448
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2704637533
Short name T446
Test name
Test status
Simulation time 12003773651 ps
CPU time 7.56 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 234220 kb
Host smart-4b4a5aa7-a545-4524-9309-fcbb3c73fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704637533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2704637533
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4272256510
Short name T300
Test name
Test status
Simulation time 71623022 ps
CPU time 0.79 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:14 PM PDT 24
Peak memory 205940 kb
Host smart-12b610e9-612c-42fc-898d-bffe54ecb1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272256510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4272256510
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3161280622
Short name T903
Test name
Test status
Simulation time 50497520821 ps
CPU time 248.08 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:42:26 PM PDT 24
Peak memory 264464 kb
Host smart-5afc6bd8-3fb2-422a-9957-aadf433998fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161280622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3161280622
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1534177133
Short name T298
Test name
Test status
Simulation time 12899311237 ps
CPU time 76.86 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:39:34 PM PDT 24
Peak memory 249956 kb
Host smart-e9edc38c-c92a-4f06-8cb6-6fc2c7ec8884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534177133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1534177133
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3327035731
Short name T229
Test name
Test status
Simulation time 67396105905 ps
CPU time 202.41 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 267424 kb
Host smart-29dffe18-10c4-490e-96c9-2193bdd142fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327035731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3327035731
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2620588372
Short name T271
Test name
Test status
Simulation time 13944657208 ps
CPU time 13.25 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 232324 kb
Host smart-e1253354-20f3-4021-ab9c-af6ecc38d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620588372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2620588372
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2148891491
Short name T350
Test name
Test status
Simulation time 1780904909 ps
CPU time 4.75 seconds
Started Mar 24 02:38:22 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 224156 kb
Host smart-31515b60-d0c6-4761-9a3d-019268e829cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148891491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2148891491
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1859125590
Short name T923
Test name
Test status
Simulation time 8418466733 ps
CPU time 14.44 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 234804 kb
Host smart-07ca282c-4187-43e5-b422-66856fd9f80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859125590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1859125590
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.4114604071
Short name T683
Test name
Test status
Simulation time 98638812 ps
CPU time 1.07 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:17 PM PDT 24
Peak memory 216264 kb
Host smart-f9e01601-dc97-4137-b269-af0384242948
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114604071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.4114604071
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3976701628
Short name T143
Test name
Test status
Simulation time 1126709174 ps
CPU time 4.75 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:38:22 PM PDT 24
Peak memory 217892 kb
Host smart-28c698c1-0eed-440c-a094-d9364e16b184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976701628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3976701628
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2290105036
Short name T163
Test name
Test status
Simulation time 783794480 ps
CPU time 8.97 seconds
Started Mar 24 02:38:21 PM PDT 24
Finished Mar 24 02:38:30 PM PDT 24
Peak memory 232104 kb
Host smart-0701eb06-ba75-45f9-a833-0d76fcf6813a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290105036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2290105036
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1870022822
Short name T384
Test name
Test status
Simulation time 16618577 ps
CPU time 0.75 seconds
Started Mar 24 02:38:12 PM PDT 24
Finished Mar 24 02:38:13 PM PDT 24
Peak memory 215812 kb
Host smart-8a4bf6b1-8edc-4bda-8084-661e016a2507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870022822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1870022822
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1463268246
Short name T281
Test name
Test status
Simulation time 1713164548 ps
CPU time 6.3 seconds
Started Mar 24 02:38:21 PM PDT 24
Finished Mar 24 02:38:27 PM PDT 24
Peak memory 222452 kb
Host smart-a009e93c-a55a-4887-b6db-e4305807da93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463268246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1463268246
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3165966239
Short name T713
Test name
Test status
Simulation time 647202714 ps
CPU time 6.95 seconds
Started Mar 24 02:38:21 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 215868 kb
Host smart-f2b159df-c790-4b28-9953-94aef43c46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165966239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3165966239
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3186526004
Short name T392
Test name
Test status
Simulation time 498928020 ps
CPU time 3.68 seconds
Started Mar 24 02:38:19 PM PDT 24
Finished Mar 24 02:38:23 PM PDT 24
Peak memory 215928 kb
Host smart-44b24c0f-e1b3-41ca-8a37-b2169013b1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186526004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3186526004
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2448140820
Short name T268
Test name
Test status
Simulation time 185633874 ps
CPU time 1.39 seconds
Started Mar 24 02:38:20 PM PDT 24
Finished Mar 24 02:38:21 PM PDT 24
Peak memory 215740 kb
Host smart-3fafd653-e5d9-47af-9008-9b0656de3483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448140820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2448140820
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.750684348
Short name T957
Test name
Test status
Simulation time 277077721 ps
CPU time 0.84 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:18 PM PDT 24
Peak memory 205304 kb
Host smart-2076950c-2298-4458-a4f2-1fc82cc6be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750684348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.750684348
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1555792999
Short name T604
Test name
Test status
Simulation time 3706338340 ps
CPU time 13.22 seconds
Started Mar 24 02:38:19 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 232128 kb
Host smart-91b51b03-3ce7-4c9d-bcb1-de004a79548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555792999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1555792999
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3198720574
Short name T57
Test name
Test status
Simulation time 21475214 ps
CPU time 0.79 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 204824 kb
Host smart-24a17ba7-c74d-4b95-8f0e-946bab24e4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198720574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3198720574
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3222475880
Short name T69
Test name
Test status
Simulation time 372838133 ps
CPU time 2.35 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 216456 kb
Host smart-a13e752e-5fa8-400a-b42f-81182d837d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222475880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3222475880
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1472330842
Short name T464
Test name
Test status
Simulation time 45505216 ps
CPU time 0.78 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 205228 kb
Host smart-2aa2981f-9ca2-45ed-895f-efb35983bcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472330842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1472330842
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1237385055
Short name T663
Test name
Test status
Simulation time 6109236122 ps
CPU time 56.91 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 251808 kb
Host smart-255ea85f-1978-4057-9048-d7f046f7baee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237385055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1237385055
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2752904679
Short name T615
Test name
Test status
Simulation time 119856170664 ps
CPU time 176.72 seconds
Started Mar 24 02:38:23 PM PDT 24
Finished Mar 24 02:41:20 PM PDT 24
Peak memory 248908 kb
Host smart-415b487c-fbe5-445f-84a1-73d9fc6be898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752904679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2752904679
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2501805501
Short name T491
Test name
Test status
Simulation time 21058988712 ps
CPU time 85.21 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:39:51 PM PDT 24
Peak memory 248848 kb
Host smart-93b047a7-4356-460c-ace1-4a37add5a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501805501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2501805501
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.259367154
Short name T682
Test name
Test status
Simulation time 437020502 ps
CPU time 21.42 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 254740 kb
Host smart-af8ff597-19a0-42c3-8e7d-fd75c55bf0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259367154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.259367154
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.507755339
Short name T220
Test name
Test status
Simulation time 1945428948 ps
CPU time 7.58 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:33 PM PDT 24
Peak memory 233324 kb
Host smart-e554e891-b769-4518-a94e-45c91b0c590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507755339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.507755339
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2844958118
Short name T922
Test name
Test status
Simulation time 6066724570 ps
CPU time 12.35 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 236980 kb
Host smart-86acfa0c-c65b-4dff-be1a-4a415245a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844958118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2844958118
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3055281224
Short name T574
Test name
Test status
Simulation time 130524345 ps
CPU time 1 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 216196 kb
Host smart-de6a3a8d-9c7f-4324-b1a5-f36be9e85b3d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055281224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3055281224
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2089372432
Short name T941
Test name
Test status
Simulation time 9230012786 ps
CPU time 15.26 seconds
Started Mar 24 02:38:23 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 224072 kb
Host smart-0b4f51b1-44b8-43a7-aab7-c76acbfe4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089372432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2089372432
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1619315166
Short name T668
Test name
Test status
Simulation time 13360756361 ps
CPU time 20.31 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 235712 kb
Host smart-cdd67166-790d-49d8-8a16-f9486fbf8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619315166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1619315166
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.562522356
Short name T626
Test name
Test status
Simulation time 15600207 ps
CPU time 0.75 seconds
Started Mar 24 02:38:16 PM PDT 24
Finished Mar 24 02:38:17 PM PDT 24
Peak memory 215812 kb
Host smart-749910c2-ccc7-477a-91cd-528049639300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562522356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.562522356
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4075332878
Short name T651
Test name
Test status
Simulation time 745202840 ps
CPU time 3.92 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:31 PM PDT 24
Peak memory 221432 kb
Host smart-5dcabb30-a6a7-4f16-8e3c-62c0c202ff8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4075332878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4075332878
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2973530488
Short name T260
Test name
Test status
Simulation time 18843923028 ps
CPU time 24.81 seconds
Started Mar 24 02:38:19 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 216020 kb
Host smart-6a1f9f13-e19f-42be-9742-7d673c5e746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973530488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2973530488
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1927507126
Short name T964
Test name
Test status
Simulation time 2482694736 ps
CPU time 13.34 seconds
Started Mar 24 02:38:18 PM PDT 24
Finished Mar 24 02:38:31 PM PDT 24
Peak memory 215976 kb
Host smart-76d2a610-7cc6-4a35-add7-af933adbb681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927507126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1927507126
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2521920197
Short name T857
Test name
Test status
Simulation time 65358574 ps
CPU time 0.82 seconds
Started Mar 24 02:38:19 PM PDT 24
Finished Mar 24 02:38:20 PM PDT 24
Peak memory 205276 kb
Host smart-9b1db155-f114-4d7f-9518-6034e7e171db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521920197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2521920197
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1592609420
Short name T947
Test name
Test status
Simulation time 24460292 ps
CPU time 0.77 seconds
Started Mar 24 02:38:20 PM PDT 24
Finished Mar 24 02:38:21 PM PDT 24
Peak memory 205308 kb
Host smart-eb2fa1fc-1ac6-43d4-8dc3-86e2ca3fbf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592609420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1592609420
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3597032886
Short name T533
Test name
Test status
Simulation time 3770865594 ps
CPU time 12.11 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 216952 kb
Host smart-a8aec4d9-9f37-4378-bf85-429af332f22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597032886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3597032886
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2869960392
Short name T805
Test name
Test status
Simulation time 20674689 ps
CPU time 0.7 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:31 PM PDT 24
Peak memory 204844 kb
Host smart-fc366d90-2935-4e84-8263-dadd7daa7dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869960392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2869960392
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1303486296
Short name T904
Test name
Test status
Simulation time 430546893 ps
CPU time 2.42 seconds
Started Mar 24 02:38:31 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 216084 kb
Host smart-611283c9-a3b0-48e2-95b9-bd91aef93d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303486296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1303486296
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.291313492
Short name T294
Test name
Test status
Simulation time 38963997 ps
CPU time 0.78 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 206192 kb
Host smart-ae675c1c-3d36-4b72-97b2-573922483bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291313492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.291313492
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3061814329
Short name T35
Test name
Test status
Simulation time 7500349124 ps
CPU time 53.64 seconds
Started Mar 24 02:38:31 PM PDT 24
Finished Mar 24 02:39:27 PM PDT 24
Peak memory 236072 kb
Host smart-92f187b5-cd88-4c94-8128-650b8f398481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061814329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3061814329
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3726851651
Short name T871
Test name
Test status
Simulation time 13931692819 ps
CPU time 35.29 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:39:09 PM PDT 24
Peak memory 236556 kb
Host smart-c908d609-41c8-4c44-b3e8-9710447feb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726851651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3726851651
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.997371622
Short name T504
Test name
Test status
Simulation time 72303854793 ps
CPU time 132.32 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:40:42 PM PDT 24
Peak memory 240572 kb
Host smart-b08a0039-381c-4bf0-8080-9d2395d6abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997371622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.997371622
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.359192378
Short name T751
Test name
Test status
Simulation time 3224270009 ps
CPU time 31.79 seconds
Started Mar 24 02:38:29 PM PDT 24
Finished Mar 24 02:39:02 PM PDT 24
Peak memory 235180 kb
Host smart-41c639d9-f5cf-4023-962b-c48cd42cf81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359192378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.359192378
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1931534150
Short name T900
Test name
Test status
Simulation time 493393629 ps
CPU time 3.35 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:29 PM PDT 24
Peak memory 233200 kb
Host smart-dde41a81-062d-4bbe-b045-6dba803f42e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931534150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1931534150
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4239757624
Short name T879
Test name
Test status
Simulation time 1865352294 ps
CPU time 16.44 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:41 PM PDT 24
Peak memory 248664 kb
Host smart-215a9c97-11cb-4d26-85bf-cad81be007cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239757624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4239757624
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3549346157
Short name T295
Test name
Test status
Simulation time 94556677 ps
CPU time 1.06 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 216232 kb
Host smart-2e9705ea-27e5-4e31-a774-9578fd61fe50
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549346157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3549346157
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1499110170
Short name T920
Test name
Test status
Simulation time 97493678 ps
CPU time 2.84 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 233240 kb
Host smart-67e6615f-49bc-4cce-9119-7cf3ea087ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499110170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1499110170
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2178584439
Short name T778
Test name
Test status
Simulation time 872922107 ps
CPU time 5.79 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 233076 kb
Host smart-cf2d374e-dc21-4646-a9e7-409d0d5c66b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178584439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2178584439
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3514218806
Short name T377
Test name
Test status
Simulation time 40517226 ps
CPU time 0.75 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 216056 kb
Host smart-00a7c97c-ff65-459e-8087-7dae68613d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514218806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3514218806
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2674334819
Short name T457
Test name
Test status
Simulation time 487504433 ps
CPU time 3.85 seconds
Started Mar 24 02:38:27 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 222364 kb
Host smart-9685174f-64cf-4f49-8370-e0c550d0ab9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2674334819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2674334819
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2587072451
Short name T547
Test name
Test status
Simulation time 18310051855 ps
CPU time 109.31 seconds
Started Mar 24 02:38:29 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 265664 kb
Host smart-78a6cdfb-cbd5-437f-8478-f04ede2c1a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587072451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2587072451
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3904652012
Short name T521
Test name
Test status
Simulation time 41403922002 ps
CPU time 60.43 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:39:25 PM PDT 24
Peak memory 220620 kb
Host smart-3ffbf67d-ce9d-4414-88dc-f0a6eec91630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904652012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3904652012
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3036896504
Short name T278
Test name
Test status
Simulation time 658447368 ps
CPU time 4.1 seconds
Started Mar 24 02:38:25 PM PDT 24
Finished Mar 24 02:38:29 PM PDT 24
Peak memory 215988 kb
Host smart-5a668958-5a82-41f9-aab8-c075e1f4055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036896504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3036896504
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3274127317
Short name T726
Test name
Test status
Simulation time 178644418 ps
CPU time 1.73 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 207660 kb
Host smart-333fe9c4-e211-477e-ab45-9bab3dabb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274127317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3274127317
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1998931608
Short name T781
Test name
Test status
Simulation time 349392613 ps
CPU time 1.02 seconds
Started Mar 24 02:38:24 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 205572 kb
Host smart-39e56ee2-c4ec-413c-bb0f-0e878bf266db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998931608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1998931608
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1599131466
Short name T329
Test name
Test status
Simulation time 5667443818 ps
CPU time 5.71 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 233476 kb
Host smart-0789aee2-b6f0-42b0-9327-90eef647b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599131466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1599131466
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.327695720
Short name T681
Test name
Test status
Simulation time 40461102 ps
CPU time 0.73 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 204856 kb
Host smart-86147a2f-9358-4f24-ac10-02d0cd2135c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327695720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.327695720
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.834428225
Short name T908
Test name
Test status
Simulation time 190775415 ps
CPU time 2.63 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 233696 kb
Host smart-09009e92-5dec-470d-9fd9-9771ba89eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834428225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.834428225
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1139645475
Short name T544
Test name
Test status
Simulation time 17364487 ps
CPU time 0.76 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:27 PM PDT 24
Peak memory 205964 kb
Host smart-c6683b20-fced-47a0-9241-4c72c55c7258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139645475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1139645475
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1045941980
Short name T177
Test name
Test status
Simulation time 11123607578 ps
CPU time 146.36 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:41:01 PM PDT 24
Peak memory 266668 kb
Host smart-24fd2e94-2a17-4227-8ca3-98bbcf2958db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045941980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1045941980
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3862606998
Short name T919
Test name
Test status
Simulation time 27284844709 ps
CPU time 212.49 seconds
Started Mar 24 02:38:35 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 254296 kb
Host smart-89316e17-8233-4a3e-9729-b23fe02cdfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862606998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3862606998
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.278313353
Short name T258
Test name
Test status
Simulation time 1055200795 ps
CPU time 20.88 seconds
Started Mar 24 02:38:34 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 234532 kb
Host smart-732fe1b8-f130-4c06-a8c6-0933349ef629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278313353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.278313353
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2266439686
Short name T862
Test name
Test status
Simulation time 5785932080 ps
CPU time 7.01 seconds
Started Mar 24 02:38:31 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 233668 kb
Host smart-230a914c-393f-49c8-a196-357cee68bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266439686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2266439686
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2203356511
Short name T884
Test name
Test status
Simulation time 5924885212 ps
CPU time 20.08 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 240504 kb
Host smart-25b81c67-7e34-4126-8281-89db8d26eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203356511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2203356511
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.122813508
Short name T444
Test name
Test status
Simulation time 60746610 ps
CPU time 1.09 seconds
Started Mar 24 02:38:31 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 216172 kb
Host smart-e1165463-5843-436f-adb3-35198b3a18b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122813508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.122813508
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3414171069
Short name T437
Test name
Test status
Simulation time 402245702 ps
CPU time 5.02 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 234720 kb
Host smart-4d50b94c-925c-4796-9fb4-7c4d3beacce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414171069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3414171069
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2249325095
Short name T744
Test name
Test status
Simulation time 1190730322 ps
CPU time 5.59 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:35 PM PDT 24
Peak memory 233176 kb
Host smart-e9ecb276-8a90-48c2-b51a-d8f6ba1b7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249325095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2249325095
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2438817638
Short name T643
Test name
Test status
Simulation time 16149308 ps
CPU time 0.75 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:30 PM PDT 24
Peak memory 215812 kb
Host smart-f3ada931-f1e2-4bc1-b69d-1265aec276c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438817638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2438817638
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3188815107
Short name T363
Test name
Test status
Simulation time 477057843 ps
CPU time 3.63 seconds
Started Mar 24 02:38:38 PM PDT 24
Finished Mar 24 02:38:42 PM PDT 24
Peak memory 222460 kb
Host smart-8c11ee9f-57ec-4576-947f-7680f2a3a26d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3188815107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3188815107
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2914968635
Short name T833
Test name
Test status
Simulation time 75267285 ps
CPU time 0.97 seconds
Started Mar 24 02:38:34 PM PDT 24
Finished Mar 24 02:38:35 PM PDT 24
Peak memory 206268 kb
Host smart-35d348f8-1de0-4b37-9337-5ec041d850a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914968635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2914968635
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3241597351
Short name T75
Test name
Test status
Simulation time 70395797152 ps
CPU time 62.67 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 215980 kb
Host smart-a41308a0-e61e-4c47-9e2b-3587c3122b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241597351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3241597351
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1203328026
Short name T680
Test name
Test status
Simulation time 14921399587 ps
CPU time 21.16 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:51 PM PDT 24
Peak memory 216076 kb
Host smart-51d6a489-7544-44eb-87e1-ce14fa0fd8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203328026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1203328026
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1676713793
Short name T279
Test name
Test status
Simulation time 142080315 ps
CPU time 0.95 seconds
Started Mar 24 02:38:28 PM PDT 24
Finished Mar 24 02:38:30 PM PDT 24
Peak memory 206344 kb
Host smart-9736a66d-b5e7-45a5-9489-b8549d745ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676713793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1676713793
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1551456422
Short name T676
Test name
Test status
Simulation time 308629264 ps
CPU time 0.98 seconds
Started Mar 24 02:38:26 PM PDT 24
Finished Mar 24 02:38:28 PM PDT 24
Peak memory 205544 kb
Host smart-7a5d2c1f-9e7d-4349-a4fa-57e14afc9fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551456422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1551456422
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1947732527
Short name T568
Test name
Test status
Simulation time 3128543420 ps
CPU time 10.01 seconds
Started Mar 24 02:38:29 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 217552 kb
Host smart-d85a80a9-f3ef-400f-8782-295dfb2025e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947732527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1947732527
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2753388616
Short name T975
Test name
Test status
Simulation time 12520452 ps
CPU time 0.73 seconds
Started Mar 24 02:38:38 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 204848 kb
Host smart-55aa1f71-4316-450d-a9e7-9b51cee7c3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753388616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2753388616
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.335705151
Short name T818
Test name
Test status
Simulation time 1559520694 ps
CPU time 7.41 seconds
Started Mar 24 02:38:37 PM PDT 24
Finished Mar 24 02:38:45 PM PDT 24
Peak memory 233248 kb
Host smart-3366e644-1372-4e55-8303-d8bd0bb33c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335705151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.335705151
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3007690806
Short name T458
Test name
Test status
Simulation time 15664030 ps
CPU time 0.75 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 204860 kb
Host smart-efabecfd-4b8b-4557-ac25-ecb3910d35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007690806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3007690806
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1349342272
Short name T31
Test name
Test status
Simulation time 281610095679 ps
CPU time 212.07 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 250784 kb
Host smart-367baaa2-8a0f-476d-84bb-b70618750b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349342272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1349342272
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3776953401
Short name T601
Test name
Test status
Simulation time 16241782586 ps
CPU time 45.82 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 232232 kb
Host smart-29da021a-ae5d-4b5b-b8f6-812c951fd1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776953401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3776953401
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2375444223
Short name T743
Test name
Test status
Simulation time 4406867917 ps
CPU time 81.72 seconds
Started Mar 24 02:38:39 PM PDT 24
Finished Mar 24 02:40:00 PM PDT 24
Peak memory 256996 kb
Host smart-7cd606fc-6f9e-48e1-8cba-54a3c16e4350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375444223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2375444223
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2681188901
Short name T483
Test name
Test status
Simulation time 5270968825 ps
CPU time 21.63 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:39:07 PM PDT 24
Peak memory 247124 kb
Host smart-c24b1230-c1ab-45cb-8fd2-ce919b795007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681188901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2681188901
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4021049863
Short name T747
Test name
Test status
Simulation time 1682397090 ps
CPU time 5.69 seconds
Started Mar 24 02:38:34 PM PDT 24
Finished Mar 24 02:38:41 PM PDT 24
Peak memory 223972 kb
Host smart-15ebe02a-4e55-4f5c-841b-f0600abade9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021049863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4021049863
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.834518985
Short name T970
Test name
Test status
Simulation time 55713685585 ps
CPU time 36.15 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:39:21 PM PDT 24
Peak memory 247808 kb
Host smart-0fd7cff2-52c9-484f-baf6-f78f5cf4ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834518985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.834518985
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2609056394
Short name T542
Test name
Test status
Simulation time 17785833 ps
CPU time 1.03 seconds
Started Mar 24 02:38:34 PM PDT 24
Finished Mar 24 02:38:37 PM PDT 24
Peak memory 217396 kb
Host smart-3c842493-879f-4dd2-8aab-dfd5f1a057a1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609056394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2609056394
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1889855529
Short name T635
Test name
Test status
Simulation time 67067222528 ps
CPU time 52.84 seconds
Started Mar 24 02:38:36 PM PDT 24
Finished Mar 24 02:39:29 PM PDT 24
Peak memory 245400 kb
Host smart-edf05d10-2e61-4db2-8708-5cbdd4d6bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889855529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1889855529
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2221900402
Short name T812
Test name
Test status
Simulation time 2833725457 ps
CPU time 6.28 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 224208 kb
Host smart-fb27ba62-7e37-411a-9671-de365b9389b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221900402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2221900402
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3596948438
Short name T353
Test name
Test status
Simulation time 35472189 ps
CPU time 0.72 seconds
Started Mar 24 02:38:33 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 215824 kb
Host smart-aca42664-59ff-47d5-8982-4cb661731fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596948438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3596948438
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3284273939
Short name T951
Test name
Test status
Simulation time 155301367 ps
CPU time 3.65 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 222316 kb
Host smart-a71b61c7-4167-4e78-9351-f74aa7d6638a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3284273939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3284273939
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4200908523
Short name T76
Test name
Test status
Simulation time 5875168410 ps
CPU time 15.87 seconds
Started Mar 24 02:38:32 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 216000 kb
Host smart-529765f5-2571-4e8e-8579-e345ae2568e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200908523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4200908523
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3023866441
Short name T359
Test name
Test status
Simulation time 11614594263 ps
CPU time 13.45 seconds
Started Mar 24 02:38:32 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 215964 kb
Host smart-620e25c5-7b06-4200-be55-585ffb14ce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023866441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3023866441
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4087403643
Short name T380
Test name
Test status
Simulation time 628706729 ps
CPU time 2.55 seconds
Started Mar 24 02:38:32 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 216008 kb
Host smart-d15a325a-20e7-405b-ab56-71b63f87421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087403643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4087403643
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1155078108
Short name T611
Test name
Test status
Simulation time 76260350 ps
CPU time 0.77 seconds
Started Mar 24 02:38:34 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 205228 kb
Host smart-a9a939c3-0b3c-4b32-9ff8-ab0cb8ad519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155078108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1155078108
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.401354136
Short name T932
Test name
Test status
Simulation time 436811729 ps
CPU time 3.23 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:38:43 PM PDT 24
Peak memory 235860 kb
Host smart-231a1532-21f5-494d-8f0b-2ab5316f246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401354136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.401354136
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.855815394
Short name T771
Test name
Test status
Simulation time 171360948 ps
CPU time 0.75 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:45 PM PDT 24
Peak memory 204240 kb
Host smart-a460d2c8-e476-4a84-abcc-62f5ed680d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855815394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.855815394
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1281082792
Short name T846
Test name
Test status
Simulation time 3832968323 ps
CPU time 5.03 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 233744 kb
Host smart-cc470fbe-a5d1-4477-aa9f-410b283ed760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281082792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1281082792
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.465549672
Short name T388
Test name
Test status
Simulation time 43191111 ps
CPU time 0.88 seconds
Started Mar 24 02:38:37 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 205720 kb
Host smart-ca8a3e55-1c15-404f-86f1-2c40e1ec1044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465549672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.465549672
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.341320698
Short name T804
Test name
Test status
Simulation time 77609418756 ps
CPU time 93.73 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 248888 kb
Host smart-3ca2884b-f569-460e-a9f5-6db86db8e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341320698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.341320698
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3800916239
Short name T810
Test name
Test status
Simulation time 48309771979 ps
CPU time 153.81 seconds
Started Mar 24 02:38:37 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 255320 kb
Host smart-f6c34aad-c586-468d-99aa-5cbcecf8ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800916239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3800916239
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3927420800
Short name T642
Test name
Test status
Simulation time 64434798734 ps
CPU time 100.25 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:40:21 PM PDT 24
Peak memory 265256 kb
Host smart-749dfe78-24bf-4fd9-92d5-4445bda44b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927420800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3927420800
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2031935743
Short name T39
Test name
Test status
Simulation time 22584462716 ps
CPU time 35.61 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 256688 kb
Host smart-34939f49-5194-4424-b601-e2b11a2b3a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031935743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2031935743
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3646147286
Short name T670
Test name
Test status
Simulation time 1287410760 ps
CPU time 2.78 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:49 PM PDT 24
Peak memory 223960 kb
Host smart-12669cef-766c-4a6f-b4cb-4e788e8a788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646147286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3646147286
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1445227811
Short name T597
Test name
Test status
Simulation time 6900013030 ps
CPU time 17.34 seconds
Started Mar 24 02:38:42 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 240020 kb
Host smart-d2f5e01b-a12b-472f-855a-96247b2fbb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445227811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1445227811
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.411945289
Short name T569
Test name
Test status
Simulation time 44107594 ps
CPU time 1.01 seconds
Started Mar 24 02:38:39 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 216224 kb
Host smart-af711542-c160-4f1a-a4a3-903480177d9b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411945289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.411945289
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3833950831
Short name T36
Test name
Test status
Simulation time 5129027242 ps
CPU time 16.25 seconds
Started Mar 24 02:38:37 PM PDT 24
Finished Mar 24 02:38:54 PM PDT 24
Peak memory 236664 kb
Host smart-8d256f91-c172-4578-b537-e870b843bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833950831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3833950831
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1323940760
Short name T865
Test name
Test status
Simulation time 12839182911 ps
CPU time 10.88 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:54 PM PDT 24
Peak memory 231928 kb
Host smart-40542259-9b5a-4c4b-8586-3ad4678c78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323940760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1323940760
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2681171387
Short name T438
Test name
Test status
Simulation time 18433707 ps
CPU time 0.75 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 215520 kb
Host smart-5a79defa-c6aa-4a2e-8b4d-2d3503ec7913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681171387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2681171387
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2476565889
Short name T594
Test name
Test status
Simulation time 5148615115 ps
CPU time 5.39 seconds
Started Mar 24 02:38:38 PM PDT 24
Finished Mar 24 02:38:43 PM PDT 24
Peak memory 219748 kb
Host smart-fdfde5a2-08a5-48f0-a861-a2fe5489d875
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2476565889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2476565889
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3774506594
Short name T473
Test name
Test status
Simulation time 56254959279 ps
CPU time 68.93 seconds
Started Mar 24 02:38:38 PM PDT 24
Finished Mar 24 02:39:47 PM PDT 24
Peak memory 232556 kb
Host smart-1bc6a88d-a321-4ce6-981f-f8b92883842a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774506594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3774506594
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.174195229
Short name T142
Test name
Test status
Simulation time 250602407 ps
CPU time 2.06 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:38:42 PM PDT 24
Peak memory 207540 kb
Host smart-162048ad-489a-401f-ad9c-b0dce18a145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174195229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.174195229
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2095087279
Short name T640
Test name
Test status
Simulation time 1753184105 ps
CPU time 4.83 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:38:45 PM PDT 24
Peak memory 216016 kb
Host smart-7aa02fa8-17f2-4f0e-b615-d0d7875d4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095087279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2095087279
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2534849822
Short name T803
Test name
Test status
Simulation time 94109137 ps
CPU time 0.76 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 205136 kb
Host smart-6ea83839-f74a-4776-998a-42d2c813ff93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534849822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2534849822
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3739375395
Short name T505
Test name
Test status
Simulation time 8676789244 ps
CPU time 26.75 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:39:09 PM PDT 24
Peak memory 220716 kb
Host smart-597fe0e2-5c97-40c2-bc92-60f809d0290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739375395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3739375395
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3126672441
Short name T401
Test name
Test status
Simulation time 40516039 ps
CPU time 0.69 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 205216 kb
Host smart-35518b9b-8445-4468-96e0-5e6c381d70f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126672441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3126672441
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.820633120
Short name T969
Test name
Test status
Simulation time 3179641184 ps
CPU time 4.81 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 218992 kb
Host smart-180b7617-07fd-4aa1-9a20-add9e5d1e611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820633120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.820633120
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4220971960
Short name T51
Test name
Test status
Simulation time 48465205 ps
CPU time 0.78 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:45 PM PDT 24
Peak memory 204868 kb
Host smart-d14e8ff3-7490-4f72-8c32-62a0d79056a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220971960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4220971960
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.145217446
Short name T221
Test name
Test status
Simulation time 7598553811 ps
CPU time 37.78 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:39:19 PM PDT 24
Peak memory 237132 kb
Host smart-fd839df9-a7f1-47b4-9466-b6812d1b158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145217446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.145217446
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1664310161
Short name T451
Test name
Test status
Simulation time 70327486347 ps
CPU time 86.32 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 248908 kb
Host smart-81b50993-0f4f-4d71-ade7-6c2ad1cd385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664310161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1664310161
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2609924081
Short name T259
Test name
Test status
Simulation time 3909153708 ps
CPU time 23.89 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:39:07 PM PDT 24
Peak memory 248292 kb
Host smart-c6692273-5106-4863-bfee-06bb06236a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609924081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2609924081
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1809467399
Short name T141
Test name
Test status
Simulation time 606409703 ps
CPU time 5.41 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:49 PM PDT 24
Peak memory 234672 kb
Host smart-40752acd-e426-47b6-8444-053ce56c5727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809467399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1809467399
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2718781053
Short name T870
Test name
Test status
Simulation time 21454543839 ps
CPU time 9.74 seconds
Started Mar 24 02:38:42 PM PDT 24
Finished Mar 24 02:38:52 PM PDT 24
Peak memory 223648 kb
Host smart-c1617347-e6b0-49df-bf7d-608c95f3d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718781053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2718781053
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3315121017
Short name T21
Test name
Test status
Simulation time 27238416 ps
CPU time 1.05 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:38:43 PM PDT 24
Peak memory 217468 kb
Host smart-26d90ad5-950c-481f-b167-66cca8336e9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315121017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3315121017
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3422539241
Short name T462
Test name
Test status
Simulation time 12697685788 ps
CPU time 11.77 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 233036 kb
Host smart-0d1c7da8-54e0-4e57-96f5-e57d6bbf95f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422539241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3422539241
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1199250569
Short name T468
Test name
Test status
Simulation time 339071599 ps
CPU time 4.95 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 232276 kb
Host smart-99c9801c-3d8e-4fb3-a330-24d25af200c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199250569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1199250569
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.1025617058
Short name T939
Test name
Test status
Simulation time 15044375 ps
CPU time 0.74 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 215660 kb
Host smart-aa70dbfc-25b5-4a34-bb92-8461c2bb8eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025617058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.1025617058
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.154823601
Short name T863
Test name
Test status
Simulation time 424219534 ps
CPU time 4.18 seconds
Started Mar 24 02:38:40 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 222628 kb
Host smart-4a6d598b-4ff2-4d19-82ce-0a966c6264b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=154823601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.154823601
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1879987009
Short name T136
Test name
Test status
Simulation time 31302343067 ps
CPU time 212.18 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:42:17 PM PDT 24
Peak memory 251384 kb
Host smart-03ed6bfa-bdd0-4978-944b-8de7288af7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879987009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1879987009
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2372738766
Short name T627
Test name
Test status
Simulation time 10786599927 ps
CPU time 52.09 seconds
Started Mar 24 02:38:45 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 215988 kb
Host smart-782115a2-f840-405e-b286-0628fe42868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372738766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2372738766
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3349241206
Short name T814
Test name
Test status
Simulation time 826802702 ps
CPU time 5.13 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 215832 kb
Host smart-f2109f2c-afb9-49b8-821e-6297788f1f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349241206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3349241206
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3452580386
Short name T150
Test name
Test status
Simulation time 775025984 ps
CPU time 3.95 seconds
Started Mar 24 02:38:42 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 215964 kb
Host smart-040d55a9-debc-4ea0-8368-a76c68616453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452580386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3452580386
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1547529246
Short name T330
Test name
Test status
Simulation time 145294633 ps
CPU time 1.13 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 206316 kb
Host smart-2ef4b1a7-6fe3-4f46-9614-e3aed0308e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547529246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1547529246
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2301037396
Short name T198
Test name
Test status
Simulation time 17773782358 ps
CPU time 26.96 seconds
Started Mar 24 02:38:41 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 237364 kb
Host smart-d0d63511-2e1f-4f78-a300-8bc1f0b55594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301037396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2301037396
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1995030235
Short name T534
Test name
Test status
Simulation time 14299636 ps
CPU time 0.75 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 204804 kb
Host smart-0800b81f-4aad-46bf-aa8a-c90c02d2d17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995030235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
995030235
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4012142602
Short name T959
Test name
Test status
Simulation time 697352959 ps
CPU time 4.17 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 218032 kb
Host smart-f1a2628e-b7fc-45ea-9e5f-2bb8c7403310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012142602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4012142602
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1760986737
Short name T277
Test name
Test status
Simulation time 52019459 ps
CPU time 0.75 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:36 PM PDT 24
Peak memory 205176 kb
Host smart-e9a02b18-9966-4fd8-a44e-3f97325403a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760986737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1760986737
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2655990871
Short name T420
Test name
Test status
Simulation time 1812939020 ps
CPU time 12.27 seconds
Started Mar 24 02:37:38 PM PDT 24
Finished Mar 24 02:37:50 PM PDT 24
Peak memory 237580 kb
Host smart-d8925a29-0139-4613-ba87-a190ee5ab132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655990871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2655990871
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3564060903
Short name T686
Test name
Test status
Simulation time 12905373746 ps
CPU time 15.28 seconds
Started Mar 24 02:37:35 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 234564 kb
Host smart-7ac56f0c-15cb-4b74-8561-c33d2a53577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564060903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3564060903
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2544138445
Short name T459
Test name
Test status
Simulation time 124274372894 ps
CPU time 230.18 seconds
Started Mar 24 02:37:35 PM PDT 24
Finished Mar 24 02:41:26 PM PDT 24
Peak memory 257000 kb
Host smart-1c174a7a-5147-4211-b214-f7d22555024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544138445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2544138445
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3722346691
Short name T52
Test name
Test status
Simulation time 5821576406 ps
CPU time 28.87 seconds
Started Mar 24 02:37:34 PM PDT 24
Finished Mar 24 02:38:03 PM PDT 24
Peak memory 238352 kb
Host smart-7fa5e005-1ce7-4209-8935-1af68ca24ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722346691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3722346691
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3944362553
Short name T720
Test name
Test status
Simulation time 769217376 ps
CPU time 2.77 seconds
Started Mar 24 02:37:34 PM PDT 24
Finished Mar 24 02:37:37 PM PDT 24
Peak memory 223956 kb
Host smart-4d507e95-0d8a-4c6a-86b3-85f2b05b6d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944362553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3944362553
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.406052891
Short name T958
Test name
Test status
Simulation time 2835136144 ps
CPU time 14.74 seconds
Started Mar 24 02:37:38 PM PDT 24
Finished Mar 24 02:37:53 PM PDT 24
Peak memory 232296 kb
Host smart-a386d230-408a-4f13-8f0a-030fa52a5802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406052891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.406052891
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.198200408
Short name T882
Test name
Test status
Simulation time 14627986 ps
CPU time 1.04 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 217420 kb
Host smart-87435063-393f-4cef-a7a5-ff8cbfef379f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198200408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.198200408
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4189811622
Short name T3
Test name
Test status
Simulation time 1622884868 ps
CPU time 7.85 seconds
Started Mar 24 02:37:34 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 233680 kb
Host smart-fe2e3cb7-eb30-4327-8691-2b6afbb168a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189811622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4189811622
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4008791335
Short name T567
Test name
Test status
Simulation time 147932978 ps
CPU time 3.56 seconds
Started Mar 24 02:37:38 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 232308 kb
Host smart-456ca299-e25e-4e18-9c30-5050aae4f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008791335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4008791335
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3753843761
Short name T936
Test name
Test status
Simulation time 20878636 ps
CPU time 0.75 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 215840 kb
Host smart-ca4efe6e-c5a6-43ba-b48f-fbdf8e8617bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753843761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3753843761
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3586356512
Short name T123
Test name
Test status
Simulation time 1065535635 ps
CPU time 4.33 seconds
Started Mar 24 02:37:35 PM PDT 24
Finished Mar 24 02:37:40 PM PDT 24
Peak memory 220088 kb
Host smart-07640ebd-1351-4ac3-981e-8f1b165675f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586356512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3586356512
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3354910002
Short name T68
Test name
Test status
Simulation time 155880997 ps
CPU time 1.03 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:45 PM PDT 24
Peak memory 235168 kb
Host smart-511e56eb-ade9-4dce-9969-28ce2c189745
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354910002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3354910002
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1120230966
Short name T331
Test name
Test status
Simulation time 497993343 ps
CPU time 1.06 seconds
Started Mar 24 02:37:43 PM PDT 24
Finished Mar 24 02:37:44 PM PDT 24
Peak memory 214644 kb
Host smart-776c8440-bd23-44cc-b150-4968d11d1081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120230966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1120230966
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.147017047
Short name T646
Test name
Test status
Simulation time 4648111306 ps
CPU time 25.43 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:38:03 PM PDT 24
Peak memory 216040 kb
Host smart-d3245454-7404-4fa2-8378-73f00c0fbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147017047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.147017047
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2003075190
Short name T78
Test name
Test status
Simulation time 14709688983 ps
CPU time 25.19 seconds
Started Mar 24 02:37:35 PM PDT 24
Finished Mar 24 02:38:00 PM PDT 24
Peak memory 216040 kb
Host smart-85261fdb-20d9-46ab-80e8-8dea35cffd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003075190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2003075190
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2441164385
Short name T819
Test name
Test status
Simulation time 183225228 ps
CPU time 5.02 seconds
Started Mar 24 02:37:37 PM PDT 24
Finished Mar 24 02:37:43 PM PDT 24
Peak memory 216312 kb
Host smart-736cda78-472b-4c3c-8273-8e7b30db0270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441164385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2441164385
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2462513527
Short name T795
Test name
Test status
Simulation time 87551186 ps
CPU time 0.88 seconds
Started Mar 24 02:37:33 PM PDT 24
Finished Mar 24 02:37:34 PM PDT 24
Peak memory 205192 kb
Host smart-5ffa3fa5-9a4b-41f1-a78a-e9eeb8deb9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462513527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2462513527
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2631920081
Short name T955
Test name
Test status
Simulation time 3009367428 ps
CPU time 8.53 seconds
Started Mar 24 02:37:36 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 240456 kb
Host smart-d1c07af2-20de-4322-b7f6-7fb5398a0ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631920081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2631920081
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1799896028
Short name T1
Test name
Test status
Simulation time 37714218 ps
CPU time 0.71 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 205188 kb
Host smart-b560bf52-92a3-4e37-a7a1-418ae9218406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799896028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1799896028
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3160896073
Short name T358
Test name
Test status
Simulation time 31997607 ps
CPU time 2.26 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 218184 kb
Host smart-c5637766-9c6e-4adb-945f-5f238bd24e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160896073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3160896073
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2033474365
Short name T728
Test name
Test status
Simulation time 17496133 ps
CPU time 0.76 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 204856 kb
Host smart-bcb46557-4dec-4e73-9620-511179bfbfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033474365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2033474365
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2871111645
Short name T239
Test name
Test status
Simulation time 23535905997 ps
CPU time 72.34 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:39:59 PM PDT 24
Peak memory 235836 kb
Host smart-778b1030-fce5-411f-9cd5-a32785506ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871111645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2871111645
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1994467823
Short name T37
Test name
Test status
Simulation time 1249397718 ps
CPU time 7.31 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 233220 kb
Host smart-7150e70b-5166-43e0-809d-df8380769d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994467823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1994467823
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1128514795
Short name T628
Test name
Test status
Simulation time 1949514969 ps
CPU time 7.63 seconds
Started Mar 24 02:38:43 PM PDT 24
Finished Mar 24 02:38:50 PM PDT 24
Peak memory 223684 kb
Host smart-73647ecb-c081-4b1b-8e3e-1ff7dde2e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128514795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1128514795
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.482827735
Short name T915
Test name
Test status
Simulation time 210604456 ps
CPU time 3.65 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 220184 kb
Host smart-281bddf4-d0a8-4009-9cd0-62bf7536a7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482827735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.482827735
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2849102092
Short name T189
Test name
Test status
Simulation time 1707873742 ps
CPU time 6.53 seconds
Started Mar 24 02:38:42 PM PDT 24
Finished Mar 24 02:38:49 PM PDT 24
Peak memory 233384 kb
Host smart-be8575e3-d10c-40a7-a17e-25e4cc4cedd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849102092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2849102092
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3347331563
Short name T674
Test name
Test status
Simulation time 2114677485 ps
CPU time 7.28 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 219904 kb
Host smart-5c5fcb92-28a2-4404-b482-8f051ba8d86d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347331563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3347331563
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2630425954
Short name T944
Test name
Test status
Simulation time 4829066117 ps
CPU time 67.1 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 240004 kb
Host smart-329d4577-51ab-449b-9128-f94876baacaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630425954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2630425954
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3905126061
Short name T609
Test name
Test status
Simulation time 1703182015 ps
CPU time 13.55 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:39:06 PM PDT 24
Peak memory 216188 kb
Host smart-3086361c-942c-4a31-a11b-d77e2fccf214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905126061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3905126061
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3148551208
Short name T774
Test name
Test status
Simulation time 1185161291 ps
CPU time 4.03 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 215948 kb
Host smart-3c1d8b0d-708a-441f-9d2f-bd0223ee6533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148551208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3148551208
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.669847433
Short name T299
Test name
Test status
Simulation time 175933342 ps
CPU time 1.42 seconds
Started Mar 24 02:38:42 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 215736 kb
Host smart-f98343a6-cceb-47f8-8ab0-fbeb01fc7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669847433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.669847433
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4187979845
Short name T463
Test name
Test status
Simulation time 231783206 ps
CPU time 0.77 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 205180 kb
Host smart-5f31f3d0-9d8d-4001-ac15-30331cbff3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187979845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4187979845
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3103830292
Short name T839
Test name
Test status
Simulation time 1729610084 ps
CPU time 4.63 seconds
Started Mar 24 02:38:44 PM PDT 24
Finished Mar 24 02:38:49 PM PDT 24
Peak memory 218212 kb
Host smart-332705f4-5ce2-44bd-9627-12cad5d99af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103830292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3103830292
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2799168048
Short name T890
Test name
Test status
Simulation time 61464744 ps
CPU time 0.7 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:38:52 PM PDT 24
Peak memory 204792 kb
Host smart-45d22bb9-e3fb-472a-be30-c638c892c48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799168048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2799168048
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3868436682
Short name T554
Test name
Test status
Simulation time 2221542112 ps
CPU time 8.96 seconds
Started Mar 24 02:38:48 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 233176 kb
Host smart-4988df28-b931-4dbb-9802-9701b5bb60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868436682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3868436682
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3599107933
Short name T629
Test name
Test status
Simulation time 81950409 ps
CPU time 0.77 seconds
Started Mar 24 02:38:48 PM PDT 24
Finished Mar 24 02:38:49 PM PDT 24
Peak memory 205248 kb
Host smart-f5196778-eb85-4b6c-b6fd-f70623f17dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599107933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3599107933
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2086592490
Short name T952
Test name
Test status
Simulation time 6678725273 ps
CPU time 43.65 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:39:31 PM PDT 24
Peak memory 240236 kb
Host smart-e0ee4b5e-928b-4290-a174-f8493e74acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086592490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2086592490
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3264921165
Short name T527
Test name
Test status
Simulation time 5744780488 ps
CPU time 10.94 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 224296 kb
Host smart-7d8182e9-e08f-4f0f-a1b7-cf0cf007d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264921165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3264921165
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1167947567
Short name T525
Test name
Test status
Simulation time 15674507734 ps
CPU time 10.91 seconds
Started Mar 24 02:38:50 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 218592 kb
Host smart-ca354097-6730-4315-9bb2-4c5446a21812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167947567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1167947567
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1357657407
Short name T333
Test name
Test status
Simulation time 431574571 ps
CPU time 3.76 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:38:51 PM PDT 24
Peak memory 218012 kb
Host smart-4cb64dad-c1ed-457a-9fb4-f5ab9878009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357657407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1357657407
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.546007821
Short name T213
Test name
Test status
Simulation time 1416220375 ps
CPU time 11.67 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 224052 kb
Host smart-76725ab5-c1fc-47c0-a423-b3bceda1ccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546007821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.546007821
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.647967758
Short name T320
Test name
Test status
Simulation time 53931334809 ps
CPU time 17.46 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 216456 kb
Host smart-e9745890-439f-4a7e-9225-9117b4e74fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647967758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.647967758
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1723961073
Short name T524
Test name
Test status
Simulation time 6598892722 ps
CPU time 6.35 seconds
Started Mar 24 02:38:49 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 219704 kb
Host smart-9d817704-a454-4ddd-9e4a-4d717e9cd00b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1723961073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1723961073
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2128179705
Short name T77
Test name
Test status
Simulation time 110148794714 ps
CPU time 376.63 seconds
Started Mar 24 02:38:50 PM PDT 24
Finished Mar 24 02:45:07 PM PDT 24
Peak memory 252944 kb
Host smart-e22901c9-973f-43ca-bdc5-38a71dfe23fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128179705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2128179705
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.524797154
Short name T537
Test name
Test status
Simulation time 10381699245 ps
CPU time 13.35 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 215916 kb
Host smart-09d9c85b-3137-43cc-8c3d-69e583d7f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524797154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.524797154
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2747901469
Short name T273
Test name
Test status
Simulation time 4361216698 ps
CPU time 13.8 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:39:00 PM PDT 24
Peak memory 216040 kb
Host smart-dfb9063e-5f0e-4573-a573-2ebf8ecb80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747901469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2747901469
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1257369812
Short name T53
Test name
Test status
Simulation time 97765853 ps
CPU time 1.27 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 206680 kb
Host smart-11879825-3aea-404c-94bf-700f9127c0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257369812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1257369812
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1863963302
Short name T488
Test name
Test status
Simulation time 508614473 ps
CPU time 1.12 seconds
Started Mar 24 02:38:47 PM PDT 24
Finished Mar 24 02:38:48 PM PDT 24
Peak memory 206332 kb
Host smart-3371a1e7-7f5b-4ad3-ba23-b93ddd6bc507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863963302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1863963302
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1857521298
Short name T614
Test name
Test status
Simulation time 4397236577 ps
CPU time 10 seconds
Started Mar 24 02:38:46 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 233904 kb
Host smart-c94686a0-fde3-406d-84c1-5113ad7cdc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857521298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1857521298
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1416387840
Short name T692
Test name
Test status
Simulation time 17059587 ps
CPU time 0.79 seconds
Started Mar 24 02:38:57 PM PDT 24
Finished Mar 24 02:38:58 PM PDT 24
Peak memory 204244 kb
Host smart-bfd58a7c-3813-40a8-8141-d17f223dc609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416387840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1416387840
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3861957310
Short name T566
Test name
Test status
Simulation time 313643123 ps
CPU time 3.36 seconds
Started Mar 24 02:38:53 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 239024 kb
Host smart-3f0bff0a-ccf1-425c-af72-c1a8da0f90b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861957310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3861957310
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.753029594
Short name T565
Test name
Test status
Simulation time 50834041 ps
CPU time 0.75 seconds
Started Mar 24 02:38:55 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 204920 kb
Host smart-d0f082a8-72fb-40e7-a35d-acb99be31b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753029594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.753029594
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3211389480
Short name T38
Test name
Test status
Simulation time 521696652219 ps
CPU time 222.88 seconds
Started Mar 24 02:38:53 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 256952 kb
Host smart-8f7332d0-5bd9-4f94-85eb-789b22dc4605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211389480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3211389480
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2388147443
Short name T634
Test name
Test status
Simulation time 9343723425 ps
CPU time 46.66 seconds
Started Mar 24 02:38:50 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 249924 kb
Host smart-eb9ad979-e44d-4e31-a960-62c07945152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388147443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2388147443
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3090484124
Short name T128
Test name
Test status
Simulation time 5770034129 ps
CPU time 25.29 seconds
Started Mar 24 02:38:55 PM PDT 24
Finished Mar 24 02:39:20 PM PDT 24
Peak memory 232884 kb
Host smart-ba282773-8866-4c7e-87c4-5e00b6e10f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090484124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3090484124
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3423860048
Short name T389
Test name
Test status
Simulation time 555272992 ps
CPU time 3.36 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:38:54 PM PDT 24
Peak memory 217292 kb
Host smart-c0597408-acec-401d-b25e-f6a8abe05713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423860048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3423860048
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2829231808
Short name T785
Test name
Test status
Simulation time 5376414982 ps
CPU time 21.11 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 237520 kb
Host smart-a739dd61-1df1-45e6-8845-bcdf4c8669fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829231808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2829231808
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.640375935
Short name T807
Test name
Test status
Simulation time 118630478 ps
CPU time 2.51 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:38:54 PM PDT 24
Peak memory 232604 kb
Host smart-2b2ecb3f-d9da-4e49-bc87-7e8f5203df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640375935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.640375935
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.554895325
Short name T347
Test name
Test status
Simulation time 25952905871 ps
CPU time 23.8 seconds
Started Mar 24 02:38:53 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 219336 kb
Host smart-e183e5f9-c5bc-483a-9b2b-96a2ff39ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554895325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.554895325
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4211781649
Short name T526
Test name
Test status
Simulation time 836800607 ps
CPU time 5.29 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 219392 kb
Host smart-848c5e1c-2e2a-4147-924e-b851a82a5ffd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4211781649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4211781649
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2878666138
Short name T145
Test name
Test status
Simulation time 8377521822 ps
CPU time 51.77 seconds
Started Mar 24 02:38:56 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 255848 kb
Host smart-9d9b0bb3-05d8-4285-b28a-86dd13038858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878666138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2878666138
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1988739404
Short name T899
Test name
Test status
Simulation time 26743746886 ps
CPU time 76.27 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 216056 kb
Host smart-a4c61c23-99a2-4c73-be02-6638ca6292e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988739404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1988739404
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.912556507
Short name T337
Test name
Test status
Simulation time 4779471696 ps
CPU time 5.59 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 216024 kb
Host smart-8e2a9882-0c02-484a-97f5-eb6dcaad67b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912556507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.912556507
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.131506200
Short name T779
Test name
Test status
Simulation time 245923980 ps
CPU time 1.35 seconds
Started Mar 24 02:38:51 PM PDT 24
Finished Mar 24 02:38:52 PM PDT 24
Peak memory 207644 kb
Host smart-449009ee-8e34-44a1-8a89-a900a2b14be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131506200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.131506200
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2796234287
Short name T10
Test name
Test status
Simulation time 182504094 ps
CPU time 0.95 seconds
Started Mar 24 02:38:52 PM PDT 24
Finished Mar 24 02:38:53 PM PDT 24
Peak memory 206344 kb
Host smart-f4813ed7-e966-4979-b320-fbfb2809fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796234287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2796234287
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3797813389
Short name T605
Test name
Test status
Simulation time 696485455 ps
CPU time 6.63 seconds
Started Mar 24 02:38:54 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 237708 kb
Host smart-3502c03c-88f9-4609-8ebe-b312cde2155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797813389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3797813389
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2307299240
Short name T983
Test name
Test status
Simulation time 24950069 ps
CPU time 0.75 seconds
Started Mar 24 02:39:04 PM PDT 24
Finished Mar 24 02:39:05 PM PDT 24
Peak memory 205024 kb
Host smart-0730c8b7-692d-443a-be7d-55ba7c14a672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307299240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2307299240
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3889677567
Short name T712
Test name
Test status
Simulation time 281849691 ps
CPU time 2.93 seconds
Started Mar 24 02:38:59 PM PDT 24
Finished Mar 24 02:39:02 PM PDT 24
Peak memory 217756 kb
Host smart-4659b021-2434-4853-a4e0-d5ba955c086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889677567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3889677567
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1682893518
Short name T874
Test name
Test status
Simulation time 15728941 ps
CPU time 0.76 seconds
Started Mar 24 02:38:58 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 205304 kb
Host smart-ea5fd5ec-92ec-497e-9c54-a278012f16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682893518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1682893518
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1957658855
Short name T235
Test name
Test status
Simulation time 77227019898 ps
CPU time 393.07 seconds
Started Mar 24 02:38:57 PM PDT 24
Finished Mar 24 02:45:31 PM PDT 24
Peak memory 265344 kb
Host smart-bc4d953b-f80c-493b-a8f9-b3200178bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957658855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1957658855
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.14026137
Short name T219
Test name
Test status
Simulation time 139178434528 ps
CPU time 165.46 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 261000 kb
Host smart-316e1831-419e-4b18-b25c-d30e2825fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14026137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.14026137
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2043017656
Short name T495
Test name
Test status
Simulation time 44698069645 ps
CPU time 78.55 seconds
Started Mar 24 02:39:02 PM PDT 24
Finished Mar 24 02:40:21 PM PDT 24
Peak memory 253708 kb
Host smart-0ea4c1b1-5430-4da2-b76f-9f1bb46f5b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043017656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2043017656
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3589977184
Short name T809
Test name
Test status
Simulation time 525254634 ps
CPU time 7.48 seconds
Started Mar 24 02:38:56 PM PDT 24
Finished Mar 24 02:39:03 PM PDT 24
Peak memory 245256 kb
Host smart-cdd6ecfc-7012-4d07-8c06-bbb11192dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589977184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3589977184
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2990410468
Short name T508
Test name
Test status
Simulation time 170749412 ps
CPU time 3.2 seconds
Started Mar 24 02:38:57 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 224136 kb
Host smart-d666f96d-8032-460a-a052-993f3444d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990410468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2990410468
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4292104045
Short name T786
Test name
Test status
Simulation time 9267706304 ps
CPU time 30.64 seconds
Started Mar 24 02:38:59 PM PDT 24
Finished Mar 24 02:39:29 PM PDT 24
Peak memory 256812 kb
Host smart-45bb379c-3664-49f9-8db8-e83fb2292ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292104045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4292104045
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2379099930
Short name T49
Test name
Test status
Simulation time 8658348409 ps
CPU time 10.43 seconds
Started Mar 24 02:39:00 PM PDT 24
Finished Mar 24 02:39:10 PM PDT 24
Peak memory 224156 kb
Host smart-6c354d05-6961-41f3-9bfb-5a97b3b5adef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379099930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2379099930
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.431849889
Short name T784
Test name
Test status
Simulation time 23021435156 ps
CPU time 14.83 seconds
Started Mar 24 02:38:57 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 228928 kb
Host smart-5b47aa4a-ec5d-4040-9675-f0ddb05bf925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431849889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.431849889
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.911943167
Short name T14
Test name
Test status
Simulation time 8790830855 ps
CPU time 5.4 seconds
Started Mar 24 02:38:57 PM PDT 24
Finished Mar 24 02:39:03 PM PDT 24
Peak memory 222660 kb
Host smart-ba0be92d-38a7-4fa6-9ee5-ead3bc5ff6f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=911943167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.911943167
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3713247921
Short name T632
Test name
Test status
Simulation time 230180293736 ps
CPU time 467.16 seconds
Started Mar 24 02:39:03 PM PDT 24
Finished Mar 24 02:46:50 PM PDT 24
Peak memory 262208 kb
Host smart-e0f65295-cf8e-494d-b7a1-6c57e7017c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713247921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3713247921
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2800059270
Short name T762
Test name
Test status
Simulation time 1671095255 ps
CPU time 13.17 seconds
Started Mar 24 02:38:59 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 216008 kb
Host smart-caa103c7-f91b-4a8b-b02f-55424e223634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800059270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2800059270
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.389061286
Short name T690
Test name
Test status
Simulation time 3733907871 ps
CPU time 3.73 seconds
Started Mar 24 02:39:00 PM PDT 24
Finished Mar 24 02:39:04 PM PDT 24
Peak memory 216084 kb
Host smart-0bf5fc9a-0039-4bce-97f5-5b659b3c45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389061286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.389061286
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1114888467
Short name T909
Test name
Test status
Simulation time 505429067 ps
CPU time 2.94 seconds
Started Mar 24 02:38:56 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 207900 kb
Host smart-6bf5e9ff-3942-4e37-90bd-492629f1f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114888467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1114888467
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2653209640
Short name T530
Test name
Test status
Simulation time 112335011 ps
CPU time 0.87 seconds
Started Mar 24 02:38:56 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 205304 kb
Host smart-7b5fbe50-a3a8-4e9a-bfd7-1575397405a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653209640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2653209640
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2123553427
Short name T218
Test name
Test status
Simulation time 1185337995 ps
CPU time 7.57 seconds
Started Mar 24 02:38:55 PM PDT 24
Finished Mar 24 02:39:03 PM PDT 24
Peak memory 233552 kb
Host smart-a9829bf4-05d2-4644-ada5-e20b42dfb12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123553427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2123553427
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.522874281
Short name T336
Test name
Test status
Simulation time 22073894 ps
CPU time 0.73 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:02 PM PDT 24
Peak memory 204864 kb
Host smart-51569c81-2be0-47f6-b74a-8fbb49026b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522874281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.522874281
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.277087612
Short name T475
Test name
Test status
Simulation time 523307434 ps
CPU time 2.87 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:04 PM PDT 24
Peak memory 233480 kb
Host smart-e4d1e597-fa17-4925-93dd-39fb3bed1d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277087612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.277087612
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3138552786
Short name T636
Test name
Test status
Simulation time 16514630 ps
CPU time 0.77 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 205920 kb
Host smart-49ec902c-bdce-4234-b152-b2195f4fef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138552786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3138552786
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2968912479
Short name T32
Test name
Test status
Simulation time 10486764830 ps
CPU time 45.07 seconds
Started Mar 24 02:39:03 PM PDT 24
Finished Mar 24 02:39:49 PM PDT 24
Peak memory 255824 kb
Host smart-df8e18e0-d11f-455a-b692-4c79cd44ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968912479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2968912479
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3060817543
Short name T623
Test name
Test status
Simulation time 7286023307 ps
CPU time 22.7 seconds
Started Mar 24 02:39:00 PM PDT 24
Finished Mar 24 02:39:23 PM PDT 24
Peak memory 235400 kb
Host smart-9dc02193-f079-400d-a520-4b9382f90f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060817543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3060817543
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3504614799
Short name T546
Test name
Test status
Simulation time 10552540995 ps
CPU time 50.8 seconds
Started Mar 24 02:39:04 PM PDT 24
Finished Mar 24 02:39:55 PM PDT 24
Peak memory 248448 kb
Host smart-3b057bd8-ae13-474a-b660-4f60601c8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504614799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3504614799
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1849952752
Short name T825
Test name
Test status
Simulation time 291137634 ps
CPU time 4.88 seconds
Started Mar 24 02:39:07 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 233932 kb
Host smart-ad9cff2f-bf7c-42f6-bfcc-10c75a2eb7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849952752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1849952752
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3991988291
Short name T449
Test name
Test status
Simulation time 9394483530 ps
CPU time 11.09 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 234880 kb
Host smart-2e9cf6cd-2fa2-49fe-8ca7-0196bf06e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991988291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3991988291
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2621729704
Short name T701
Test name
Test status
Simulation time 1402908934 ps
CPU time 4.13 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:10 PM PDT 24
Peak memory 218020 kb
Host smart-a5dc9697-0eb7-4371-b81b-13bb1268a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621729704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2621729704
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4062325916
Short name T599
Test name
Test status
Simulation time 3785031075 ps
CPU time 9.11 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:14 PM PDT 24
Peak memory 224028 kb
Host smart-0a831c7d-a9dd-40d2-af85-dacd5cf512e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062325916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4062325916
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4144838147
Short name T324
Test name
Test status
Simulation time 702734236 ps
CPU time 4.84 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:06 PM PDT 24
Peak memory 218632 kb
Host smart-c149967b-f1ce-45fd-8d88-e085e1be10fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4144838147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4144838147
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.198884981
Short name T133
Test name
Test status
Simulation time 206421964605 ps
CPU time 314.86 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:44:21 PM PDT 24
Peak memory 249564 kb
Host smart-ba1c15fb-ddc0-4043-bfcf-a615cff716e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198884981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.198884981
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3648731123
Short name T548
Test name
Test status
Simulation time 9032285250 ps
CPU time 47.94 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 215924 kb
Host smart-aa02b60f-d5c9-422c-a42b-6f7e23f940b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648731123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3648731123
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3053236495
Short name T323
Test name
Test status
Simulation time 42657027751 ps
CPU time 27.41 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:28 PM PDT 24
Peak memory 216000 kb
Host smart-af7ec3ac-7507-43eb-8409-87db8b3585c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053236495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3053236495
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1103899673
Short name T312
Test name
Test status
Simulation time 185393983 ps
CPU time 3.06 seconds
Started Mar 24 02:39:01 PM PDT 24
Finished Mar 24 02:39:04 PM PDT 24
Peak memory 216148 kb
Host smart-af599185-4eea-476f-a293-68a7927aa120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103899673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1103899673
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1404180745
Short name T550
Test name
Test status
Simulation time 56303738 ps
CPU time 0.86 seconds
Started Mar 24 02:39:03 PM PDT 24
Finished Mar 24 02:39:04 PM PDT 24
Peak memory 205296 kb
Host smart-b6fbdb9a-844b-41b1-8399-cdde1066055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404180745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1404180745
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.538536798
Short name T503
Test name
Test status
Simulation time 4828163587 ps
CPU time 9.31 seconds
Started Mar 24 02:39:04 PM PDT 24
Finished Mar 24 02:39:13 PM PDT 24
Peak memory 218348 kb
Host smart-9290c3a0-e52d-4c73-a9be-8295efda17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538536798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.538536798
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.461993224
Short name T390
Test name
Test status
Simulation time 44270092 ps
CPU time 0.72 seconds
Started Mar 24 02:39:10 PM PDT 24
Finished Mar 24 02:39:11 PM PDT 24
Peak memory 204800 kb
Host smart-8b806d97-e4e7-4611-8eb6-59843065602d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461993224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.461993224
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1053627879
Short name T731
Test name
Test status
Simulation time 449262038 ps
CPU time 3.97 seconds
Started Mar 24 02:39:07 PM PDT 24
Finished Mar 24 02:39:11 PM PDT 24
Peak memory 232804 kb
Host smart-2d60af81-1f24-4289-b653-28b06364ccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053627879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1053627879
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.541579611
Short name T666
Test name
Test status
Simulation time 34341742 ps
CPU time 0.8 seconds
Started Mar 24 02:39:03 PM PDT 24
Finished Mar 24 02:39:04 PM PDT 24
Peak memory 206268 kb
Host smart-eeff5e98-6ffe-4331-890f-8db442529ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541579611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.541579611
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1629750934
Short name T185
Test name
Test status
Simulation time 5001642382 ps
CPU time 51.3 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 248708 kb
Host smart-1d293938-ea4f-4ede-a39e-784ebb773e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629750934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1629750934
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3639918613
Short name T30
Test name
Test status
Simulation time 40361360645 ps
CPU time 266.66 seconds
Started Mar 24 02:39:03 PM PDT 24
Finished Mar 24 02:43:30 PM PDT 24
Peak memory 249912 kb
Host smart-9a1394b8-a347-4276-ae41-531fb9822c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639918613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3639918613
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3381484629
Short name T763
Test name
Test status
Simulation time 24171096788 ps
CPU time 34.12 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:39 PM PDT 24
Peak memory 232256 kb
Host smart-ac62ad7e-19bb-484e-80f6-ca12d3d614da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381484629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3381484629
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2082084212
Short name T70
Test name
Test status
Simulation time 1316383293 ps
CPU time 5.4 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:11 PM PDT 24
Peak memory 218788 kb
Host smart-597bfea2-4ac9-43d9-949e-f6d38aced0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082084212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2082084212
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1512370325
Short name T479
Test name
Test status
Simulation time 13569746278 ps
CPU time 41.11 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:47 PM PDT 24
Peak memory 248736 kb
Host smart-b667dbfd-94dc-482c-b9cb-12e3dc8ba3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512370325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1512370325
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1279712243
Short name T48
Test name
Test status
Simulation time 3985527449 ps
CPU time 17.94 seconds
Started Mar 24 02:39:04 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 240308 kb
Host smart-6655c87c-4b11-45df-a4a9-e582d5ddf414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279712243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1279712243
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.48420841
Short name T580
Test name
Test status
Simulation time 3835446439 ps
CPU time 11.18 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 233328 kb
Host smart-522daf97-56ec-4365-a08a-d085d4f9765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48420841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.48420841
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3552997976
Short name T710
Test name
Test status
Simulation time 129007361 ps
CPU time 3.3 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:10 PM PDT 24
Peak memory 219448 kb
Host smart-12bffd3a-349d-4f70-8b30-445248868868
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3552997976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3552997976
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.197997486
Short name T770
Test name
Test status
Simulation time 33083410 ps
CPU time 0.9 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:06 PM PDT 24
Peak memory 205500 kb
Host smart-cef8f6b7-2e6d-4e8f-bdc3-20dbcbb038d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197997486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.197997486
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4198826891
Short name T264
Test name
Test status
Simulation time 1465648597 ps
CPU time 12 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:18 PM PDT 24
Peak memory 217572 kb
Host smart-f09f1445-9986-459e-83bf-61348de30dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198826891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4198826891
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1724270668
Short name T494
Test name
Test status
Simulation time 5032863049 ps
CPU time 5.03 seconds
Started Mar 24 02:39:00 PM PDT 24
Finished Mar 24 02:39:05 PM PDT 24
Peak memory 216040 kb
Host smart-11eeeb0e-01c3-49e9-a9a0-ca454e5b286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724270668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1724270668
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3531398294
Short name T267
Test name
Test status
Simulation time 93917445 ps
CPU time 1.87 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:07 PM PDT 24
Peak memory 215928 kb
Host smart-02cf4956-46f8-4f4b-9636-fd27edc0d5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531398294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3531398294
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3086370909
Short name T665
Test name
Test status
Simulation time 956269943 ps
CPU time 0.93 seconds
Started Mar 24 02:39:07 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 205296 kb
Host smart-1b710f65-9cc0-4713-ab57-d91d14f40dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086370909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3086370909
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3283580680
Short name T673
Test name
Test status
Simulation time 715608138 ps
CPU time 10.3 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 230088 kb
Host smart-9fa5b9c9-294c-42b2-9d88-ba68f4e532ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283580680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3283580680
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.269767767
Short name T980
Test name
Test status
Simulation time 14187153 ps
CPU time 0.69 seconds
Started Mar 24 02:39:09 PM PDT 24
Finished Mar 24 02:39:10 PM PDT 24
Peak memory 204860 kb
Host smart-19eb1343-80c0-41bb-8276-3d0d3eafe06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269767767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.269767767
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.176378774
Short name T469
Test name
Test status
Simulation time 105724667 ps
CPU time 3.36 seconds
Started Mar 24 02:39:12 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 233412 kb
Host smart-a073e94b-2fd1-4e4f-80c8-496dcef065d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176378774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.176378774
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1632084795
Short name T292
Test name
Test status
Simulation time 13326434 ps
CPU time 0.83 seconds
Started Mar 24 02:39:07 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 205944 kb
Host smart-c3eaf97b-2f4d-40e9-8236-0fa72a4aa95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632084795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1632084795
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3465424233
Short name T195
Test name
Test status
Simulation time 1199518791 ps
CPU time 10.2 seconds
Started Mar 24 02:39:12 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 238944 kb
Host smart-ae0cc340-2bc3-476f-9173-ac52ff5bfcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465424233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3465424233
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.637526863
Short name T607
Test name
Test status
Simulation time 23294086979 ps
CPU time 173.04 seconds
Started Mar 24 02:39:10 PM PDT 24
Finished Mar 24 02:42:03 PM PDT 24
Peak memory 257068 kb
Host smart-57f38218-7055-4130-979a-226424b015e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637526863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.637526863
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1283227733
Short name T633
Test name
Test status
Simulation time 56755011398 ps
CPU time 189.56 seconds
Started Mar 24 02:39:09 PM PDT 24
Finished Mar 24 02:42:18 PM PDT 24
Peak memory 261772 kb
Host smart-362423ba-953b-4f2c-820a-37207943bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283227733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1283227733
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1063192687
Short name T759
Test name
Test status
Simulation time 16734016604 ps
CPU time 31.63 seconds
Started Mar 24 02:39:13 PM PDT 24
Finished Mar 24 02:39:45 PM PDT 24
Peak memory 224400 kb
Host smart-492a2c2e-b781-4a24-ab4e-5602135c47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063192687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1063192687
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3557279990
Short name T793
Test name
Test status
Simulation time 1249387495 ps
CPU time 7.15 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 233240 kb
Host smart-0a5accbb-4d39-4bec-b4b7-cd8f370878eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557279990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3557279990
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3947607713
Short name T168
Test name
Test status
Simulation time 3246513544 ps
CPU time 15.85 seconds
Started Mar 24 02:39:12 PM PDT 24
Finished Mar 24 02:39:28 PM PDT 24
Peak memory 240572 kb
Host smart-0427a508-6dea-4438-a0cb-5834a1b95e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947607713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3947607713
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.878118191
Short name T237
Test name
Test status
Simulation time 1061034335 ps
CPU time 2.91 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:09 PM PDT 24
Peak memory 217936 kb
Host smart-7ca2e155-0a5f-4785-b1ea-1b18267697af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878118191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.878118191
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2229741926
Short name T404
Test name
Test status
Simulation time 237133989 ps
CPU time 3.67 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:10 PM PDT 24
Peak memory 217584 kb
Host smart-d26efd5d-101f-49f6-9eb7-ec7c46c28e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229741926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2229741926
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2996780590
Short name T313
Test name
Test status
Simulation time 3452414642 ps
CPU time 5.11 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:16 PM PDT 24
Peak memory 222308 kb
Host smart-8e289784-bded-4545-8a7e-830c8ce74fc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2996780590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2996780590
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1046886715
Short name T283
Test name
Test status
Simulation time 24284030926 ps
CPU time 48.37 seconds
Started Mar 24 02:39:06 PM PDT 24
Finished Mar 24 02:39:55 PM PDT 24
Peak memory 215936 kb
Host smart-6f57c4b9-adc4-489e-ad2b-0edbd6ca6ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046886715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1046886715
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3795840436
Short name T830
Test name
Test status
Simulation time 38227667265 ps
CPU time 22.93 seconds
Started Mar 24 02:39:08 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 215980 kb
Host smart-0c59500e-ad20-454e-9504-541ef1721c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795840436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3795840436
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4061068735
Short name T540
Test name
Test status
Simulation time 119167986 ps
CPU time 1.11 seconds
Started Mar 24 02:39:07 PM PDT 24
Finished Mar 24 02:39:08 PM PDT 24
Peak memory 206452 kb
Host smart-700ef208-53e2-42fd-8aae-8a33553ade4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061068735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4061068735
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3297179290
Short name T520
Test name
Test status
Simulation time 89440212 ps
CPU time 0.76 seconds
Started Mar 24 02:39:05 PM PDT 24
Finished Mar 24 02:39:06 PM PDT 24
Peak memory 205268 kb
Host smart-11d990e4-8a28-4f43-9cd3-19f3db15ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297179290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3297179290
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2965978884
Short name T325
Test name
Test status
Simulation time 1648601921 ps
CPU time 9.45 seconds
Started Mar 24 02:39:10 PM PDT 24
Finished Mar 24 02:39:20 PM PDT 24
Peak memory 224068 kb
Host smart-4ae30223-381b-474b-bd12-9dbe7e6550bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965978884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2965978884
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.952345040
Short name T303
Test name
Test status
Simulation time 15028902 ps
CPU time 0.73 seconds
Started Mar 24 02:39:20 PM PDT 24
Finished Mar 24 02:39:21 PM PDT 24
Peak memory 204768 kb
Host smart-a078076e-05c6-4572-990e-440967074c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952345040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.952345040
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.884968963
Short name T203
Test name
Test status
Simulation time 52719546 ps
CPU time 2.6 seconds
Started Mar 24 02:39:13 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 233088 kb
Host smart-3301a60f-a834-4eb5-94a1-33295475b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884968963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.884968963
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3033814754
Short name T308
Test name
Test status
Simulation time 297005368 ps
CPU time 0.77 seconds
Started Mar 24 02:39:13 PM PDT 24
Finished Mar 24 02:39:14 PM PDT 24
Peak memory 205852 kb
Host smart-62882f85-db6c-4d30-b83b-60b6526531b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033814754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3033814754
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1788234758
Short name T328
Test name
Test status
Simulation time 1825486373 ps
CPU time 8.92 seconds
Started Mar 24 02:39:15 PM PDT 24
Finished Mar 24 02:39:24 PM PDT 24
Peak memory 235816 kb
Host smart-05fa487d-f84c-4929-b7c7-7e2d8b8e3fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788234758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1788234758
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4022462689
Short name T978
Test name
Test status
Simulation time 35278128007 ps
CPU time 264.6 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:43:40 PM PDT 24
Peak memory 256592 kb
Host smart-e77110c1-5a18-44ae-b1ec-fdb38b5143b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022462689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4022462689
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1647381857
Short name T885
Test name
Test status
Simulation time 25818197963 ps
CPU time 167.29 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 265264 kb
Host smart-e82c94d4-7bb5-40ab-9852-079a9274b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647381857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1647381857
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3221311862
Short name T773
Test name
Test status
Simulation time 13094923357 ps
CPU time 55.26 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 249228 kb
Host smart-ee25d548-b78b-41b2-acf0-027dd68d8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221311862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3221311862
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1935659004
Short name T155
Test name
Test status
Simulation time 1285023589 ps
CPU time 4.37 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:16 PM PDT 24
Peak memory 233080 kb
Host smart-36cfac5b-9dd2-47b9-96a3-c64256b974d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935659004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1935659004
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2164032258
Short name T223
Test name
Test status
Simulation time 6730841489 ps
CPU time 21.07 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 240472 kb
Host smart-2eb8874d-f37c-4213-b2c3-60bd14aa21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164032258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2164032258
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1683445790
Short name T754
Test name
Test status
Simulation time 17149972668 ps
CPU time 26.6 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 238244 kb
Host smart-d9d17dab-2c9d-475b-85f6-a438b148e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683445790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1683445790
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2454000640
Short name T836
Test name
Test status
Simulation time 825228192 ps
CPU time 7.03 seconds
Started Mar 24 02:39:10 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 234100 kb
Host smart-32bea7dd-e004-4aa3-ae74-a3e93b9adcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454000640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2454000640
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3824137873
Short name T898
Test name
Test status
Simulation time 443935432 ps
CPU time 3.78 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:15 PM PDT 24
Peak memory 222484 kb
Host smart-28bb60d3-5e33-4838-a499-231f613b2114
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824137873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3824137873
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1830154077
Short name T737
Test name
Test status
Simulation time 51008752 ps
CPU time 1.12 seconds
Started Mar 24 02:39:15 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 206384 kb
Host smart-cc1b0e45-43b6-42f6-b07b-3699f3445d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830154077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1830154077
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.505388612
Short name T489
Test name
Test status
Simulation time 18953947703 ps
CPU time 28.45 seconds
Started Mar 24 02:39:10 PM PDT 24
Finished Mar 24 02:39:39 PM PDT 24
Peak memory 215988 kb
Host smart-12473768-e8d6-45bd-9fec-264bb94d1e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505388612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.505388612
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1455056730
Short name T873
Test name
Test status
Simulation time 106730426350 ps
CPU time 13.22 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:39:27 PM PDT 24
Peak memory 215832 kb
Host smart-f78f3a17-62b6-4bd2-b9da-56a65347718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455056730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1455056730
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3430965248
Short name T477
Test name
Test status
Simulation time 140775547 ps
CPU time 3.08 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:14 PM PDT 24
Peak memory 216032 kb
Host smart-208211df-0a7b-47e5-9913-172920208b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430965248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3430965248
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2294353867
Short name T887
Test name
Test status
Simulation time 41176309 ps
CPU time 0.72 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:12 PM PDT 24
Peak memory 205308 kb
Host smart-6df0eabf-8091-4329-802e-2918beeb0c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294353867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2294353867
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2656017922
Short name T402
Test name
Test status
Simulation time 183984841 ps
CPU time 2.79 seconds
Started Mar 24 02:39:11 PM PDT 24
Finished Mar 24 02:39:14 PM PDT 24
Peak memory 223992 kb
Host smart-bf34ae1e-4c38-4940-900a-f43f61c6efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656017922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2656017922
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.69227095
Short name T413
Test name
Test status
Simulation time 31247790 ps
CPU time 0.73 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 204884 kb
Host smart-bf85ee52-61fc-4e6c-aff3-a5f543c506ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69227095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.69227095
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3652500580
Short name T418
Test name
Test status
Simulation time 84286908 ps
CPU time 2.69 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:39:18 PM PDT 24
Peak memory 218300 kb
Host smart-375cf7dd-afb0-4bd1-80ec-1daba63aea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652500580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3652500580
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2159960400
Short name T397
Test name
Test status
Simulation time 105763671 ps
CPU time 0.75 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 204872 kb
Host smart-b324d7e2-caa9-453c-941d-59ad4f652cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159960400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2159960400
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.359310261
Short name T394
Test name
Test status
Simulation time 4970500863 ps
CPU time 91.41 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:40:52 PM PDT 24
Peak memory 250948 kb
Host smart-9cd27d9e-cb6d-4c21-ada9-17d9de0d5fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359310261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.359310261
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1548268169
Short name T797
Test name
Test status
Simulation time 5693953022 ps
CPU time 115.52 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 256280 kb
Host smart-9c00c81e-cc32-4d2e-aa44-c3427ef57a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548268169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1548268169
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1525626878
Short name T911
Test name
Test status
Simulation time 31337031901 ps
CPU time 39.23 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:39:55 PM PDT 24
Peak memory 239668 kb
Host smart-b5a140cf-fce4-4163-b0e6-cf857833895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525626878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1525626878
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3655116577
Short name T827
Test name
Test status
Simulation time 255009523 ps
CPU time 4 seconds
Started Mar 24 02:39:20 PM PDT 24
Finished Mar 24 02:39:24 PM PDT 24
Peak memory 233356 kb
Host smart-446f6b90-3a7a-4e65-a3a6-852847af1068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655116577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3655116577
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.492594058
Short name T706
Test name
Test status
Simulation time 1996076885 ps
CPU time 16.52 seconds
Started Mar 24 02:39:17 PM PDT 24
Finished Mar 24 02:39:33 PM PDT 24
Peak memory 250268 kb
Host smart-e5cfb60d-c0b0-4113-baeb-f7054766943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492594058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.492594058
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1808380851
Short name T385
Test name
Test status
Simulation time 2896336637 ps
CPU time 6.37 seconds
Started Mar 24 02:39:16 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 232780 kb
Host smart-e25f6627-207a-4611-95ba-15b0889dc853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808380851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1808380851
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.371816552
Short name T461
Test name
Test status
Simulation time 8737139452 ps
CPU time 7.12 seconds
Started Mar 24 02:39:18 PM PDT 24
Finished Mar 24 02:39:25 PM PDT 24
Peak memory 232732 kb
Host smart-337f87ab-5f54-4b2f-845a-d6ce4a6591ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371816552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.371816552
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1297738278
Short name T486
Test name
Test status
Simulation time 3010759557 ps
CPU time 5.55 seconds
Started Mar 24 02:39:17 PM PDT 24
Finished Mar 24 02:39:23 PM PDT 24
Peak memory 218872 kb
Host smart-b14581d7-a2ba-4e17-bd6e-c136affed784
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297738278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1297738278
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2472978469
Short name T707
Test name
Test status
Simulation time 301707901473 ps
CPU time 507.6 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:47:41 PM PDT 24
Peak memory 255636 kb
Host smart-a0865981-8f40-4a59-ae81-65c419172a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472978469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2472978469
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.345529944
Short name T552
Test name
Test status
Simulation time 3773680968 ps
CPU time 30.07 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:39:44 PM PDT 24
Peak memory 216040 kb
Host smart-843850ca-e2cb-455a-8e7f-92481fa8300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345529944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.345529944
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1347250382
Short name T982
Test name
Test status
Simulation time 489794649 ps
CPU time 3.1 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:24 PM PDT 24
Peak memory 215940 kb
Host smart-c8c48abd-bda1-45f5-9b78-7b34c7e28b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347250382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1347250382
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2434845519
Short name T761
Test name
Test status
Simulation time 373673743 ps
CPU time 2.18 seconds
Started Mar 24 02:39:14 PM PDT 24
Finished Mar 24 02:39:17 PM PDT 24
Peak memory 216144 kb
Host smart-f112c87b-ec05-4242-b2a1-e13b8c5f51e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434845519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2434845519
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2201418546
Short name T529
Test name
Test status
Simulation time 49240008 ps
CPU time 0.83 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 205228 kb
Host smart-b2edf222-9c96-49e9-a03c-b084176b60b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201418546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2201418546
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2182459720
Short name T756
Test name
Test status
Simulation time 701176075 ps
CPU time 4.18 seconds
Started Mar 24 02:39:22 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 226644 kb
Host smart-b7ad62fc-f23c-4455-9e77-c4545a83be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182459720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2182459720
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2779998098
Short name T450
Test name
Test status
Simulation time 12291173 ps
CPU time 0.72 seconds
Started Mar 24 02:39:29 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 204824 kb
Host smart-a3a9e998-26dd-46c3-8332-117b7ccffb15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779998098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2779998098
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3592682084
Short name T695
Test name
Test status
Simulation time 475733173 ps
CPU time 3.6 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:34 PM PDT 24
Peak memory 218712 kb
Host smart-3ba4b3bb-208b-45ed-86c5-03e9c0ab343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592682084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3592682084
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1264809623
Short name T558
Test name
Test status
Simulation time 14233468 ps
CPU time 0.81 seconds
Started Mar 24 02:39:18 PM PDT 24
Finished Mar 24 02:39:19 PM PDT 24
Peak memory 206488 kb
Host smart-e043bd0b-996f-4660-85d9-f209740b1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264809623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1264809623
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1975082481
Short name T204
Test name
Test status
Simulation time 127745163376 ps
CPU time 135.65 seconds
Started Mar 24 02:39:29 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 248772 kb
Host smart-71563ec9-2816-4608-993e-9092e634ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975082481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1975082481
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2706377171
Short name T120
Test name
Test status
Simulation time 354994618671 ps
CPU time 111.86 seconds
Started Mar 24 02:39:19 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 237748 kb
Host smart-d120a1cf-9b33-469e-a3a8-5f6e69b317ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706377171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2706377171
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3900304595
Short name T24
Test name
Test status
Simulation time 35599201353 ps
CPU time 140.87 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 251248 kb
Host smart-f402a99d-8d24-4d82-9404-622c62a6eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900304595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3900304595
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2641820366
Short name T621
Test name
Test status
Simulation time 2381779581 ps
CPU time 6.78 seconds
Started Mar 24 02:39:19 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 232112 kb
Host smart-fdd4bd56-004b-4a15-9ec2-4a2bba7b9e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641820366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2641820366
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1236319933
Short name T497
Test name
Test status
Simulation time 3496261484 ps
CPU time 12.86 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:34 PM PDT 24
Peak memory 218060 kb
Host smart-6065b479-d674-45b2-9487-1db8154cb025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236319933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1236319933
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1793440153
Short name T217
Test name
Test status
Simulation time 17084334294 ps
CPU time 16 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:37 PM PDT 24
Peak memory 233296 kb
Host smart-5715f5ec-7556-4045-8a03-0586ab18084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793440153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1793440153
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1931522223
Short name T212
Test name
Test status
Simulation time 17830592084 ps
CPU time 23.76 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 234068 kb
Host smart-6c18fb07-916c-46c2-9d5b-8f0bc1b005b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931522223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1931522223
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2640120849
Short name T564
Test name
Test status
Simulation time 321288897 ps
CPU time 2.89 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:24 PM PDT 24
Peak memory 234040 kb
Host smart-e68431af-dbde-4837-bfec-9a605cb60ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640120849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2640120849
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3240372650
Short name T391
Test name
Test status
Simulation time 1918668156 ps
CPU time 4.16 seconds
Started Mar 24 02:39:29 PM PDT 24
Finished Mar 24 02:39:33 PM PDT 24
Peak memory 219804 kb
Host smart-fbec4397-1387-4ffc-9f73-d4259309bbf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240372650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3240372650
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2236201067
Short name T160
Test name
Test status
Simulation time 81684880599 ps
CPU time 201.47 seconds
Started Mar 24 02:39:29 PM PDT 24
Finished Mar 24 02:42:51 PM PDT 24
Peak memory 249900 kb
Host smart-13ecad4e-bb8c-4038-aca4-7209fef8aebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236201067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2236201067
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3593888457
Short name T474
Test name
Test status
Simulation time 1347718212 ps
CPU time 21.15 seconds
Started Mar 24 02:39:22 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 215932 kb
Host smart-18d04f0a-94a6-467e-8bca-61d5e826f2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593888457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3593888457
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1329306499
Short name T591
Test name
Test status
Simulation time 1269036934 ps
CPU time 8.03 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:38 PM PDT 24
Peak memory 216016 kb
Host smart-f0773efd-f7bf-437b-afb9-a64ce5384f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329306499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1329306499
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4063230106
Short name T560
Test name
Test status
Simulation time 22833603 ps
CPU time 0.8 seconds
Started Mar 24 02:39:22 PM PDT 24
Finished Mar 24 02:39:22 PM PDT 24
Peak memory 205280 kb
Host smart-d0dfd2fd-4b3e-4250-9a36-bb1b57c5a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063230106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4063230106
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.167618436
Short name T641
Test name
Test status
Simulation time 289939173 ps
CPU time 1.05 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 206328 kb
Host smart-7e916f2f-39df-4e83-a930-085d1764d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167618436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.167618436
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3957558261
Short name T523
Test name
Test status
Simulation time 797591800 ps
CPU time 4.67 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:35 PM PDT 24
Peak memory 235268 kb
Host smart-da39a4ff-8188-4a7a-b781-7503e9efa492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957558261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3957558261
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3474368448
Short name T808
Test name
Test status
Simulation time 45985812 ps
CPU time 0.75 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 204816 kb
Host smart-8ee66863-c9aa-43b7-94ff-fc0ba72de221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474368448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
474368448
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2729740411
Short name T282
Test name
Test status
Simulation time 1278025564 ps
CPU time 6.54 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:47 PM PDT 24
Peak memory 233728 kb
Host smart-0ec2e234-2604-4065-bcb4-b33a463af159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729740411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2729740411
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1305938018
Short name T749
Test name
Test status
Simulation time 60256388 ps
CPU time 0.73 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 206236 kb
Host smart-03da4d78-0db1-4d1a-a4b9-e2ab9ac5e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305938018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1305938018
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.347865014
Short name T214
Test name
Test status
Simulation time 196067822183 ps
CPU time 219.86 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:41:22 PM PDT 24
Peak memory 249108 kb
Host smart-e3128443-fa0e-4c38-8b99-0fc1b75d47ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347865014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.347865014
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2411158431
Short name T121
Test name
Test status
Simulation time 36721951433 ps
CPU time 103.76 seconds
Started Mar 24 02:37:45 PM PDT 24
Finished Mar 24 02:39:28 PM PDT 24
Peak memory 257036 kb
Host smart-83ed5a5e-2001-4321-b132-d1f6a80f7bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411158431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2411158431
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2259102365
Short name T963
Test name
Test status
Simulation time 54183308494 ps
CPU time 74.04 seconds
Started Mar 24 02:37:41 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 232532 kb
Host smart-5f867bfe-c1b3-4195-a422-4f4e57446bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259102365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2259102365
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3414615703
Short name T799
Test name
Test status
Simulation time 285458165 ps
CPU time 8.47 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:37:50 PM PDT 24
Peak memory 239764 kb
Host smart-39c3bb53-978f-4c26-b60b-3d6233b5d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414615703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3414615703
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1719492706
Short name T618
Test name
Test status
Simulation time 2850756770 ps
CPU time 4.17 seconds
Started Mar 24 02:37:43 PM PDT 24
Finished Mar 24 02:37:48 PM PDT 24
Peak memory 233440 kb
Host smart-bba63f3c-d1d1-4273-91ca-7fc69ae00900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719492706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1719492706
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3551676270
Short name T948
Test name
Test status
Simulation time 4263958205 ps
CPU time 12.08 seconds
Started Mar 24 02:37:41 PM PDT 24
Finished Mar 24 02:37:53 PM PDT 24
Peak memory 224108 kb
Host smart-46a6dcce-f472-4678-9d7f-7aefda99870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551676270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3551676270
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.645467965
Short name T831
Test name
Test status
Simulation time 106935079 ps
CPU time 1.06 seconds
Started Mar 24 02:37:39 PM PDT 24
Finished Mar 24 02:37:40 PM PDT 24
Peak memory 217488 kb
Host smart-f486bc9f-3473-4a83-b6a2-2807e026b671
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645467965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.645467965
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1264795632
Short name T645
Test name
Test status
Simulation time 1907110528 ps
CPU time 4.18 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 224028 kb
Host smart-8f25caf1-f075-4eac-b21f-8df86d03b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264795632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1264795632
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3664506093
Short name T448
Test name
Test status
Simulation time 146834013 ps
CPU time 3.15 seconds
Started Mar 24 02:37:41 PM PDT 24
Finished Mar 24 02:37:44 PM PDT 24
Peak memory 232732 kb
Host smart-f9d995be-b5b5-4276-befd-db605ffe8023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664506093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3664506093
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.873492276
Short name T669
Test name
Test status
Simulation time 18450601 ps
CPU time 0.75 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:37:43 PM PDT 24
Peak memory 215792 kb
Host smart-5660a85a-9e13-4ae1-b89c-2170f2dcf82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873492276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.873492276
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2618694250
Short name T436
Test name
Test status
Simulation time 4049989800 ps
CPU time 5.98 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 222684 kb
Host smart-7f1668d3-5009-44a3-95dd-01dbbe55f3df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2618694250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2618694250
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1384758199
Short name T67
Test name
Test status
Simulation time 111647234 ps
CPU time 1.21 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 235244 kb
Host smart-0030fca1-5f3b-4105-a1f4-5f72e6acfda3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384758199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1384758199
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1541708769
Short name T732
Test name
Test status
Simulation time 74915633468 ps
CPU time 247.92 seconds
Started Mar 24 02:37:38 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 265236 kb
Host smart-defb9884-58d3-4a63-9766-218ae1d94f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541708769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1541708769
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.251119046
Short name T515
Test name
Test status
Simulation time 7728065399 ps
CPU time 50.77 seconds
Started Mar 24 02:37:40 PM PDT 24
Finished Mar 24 02:38:30 PM PDT 24
Peak memory 216080 kb
Host smart-61af42b9-6a17-4da6-b534-fc9ec315fabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251119046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.251119046
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.986363260
Short name T362
Test name
Test status
Simulation time 270036151 ps
CPU time 1.51 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 207512 kb
Host smart-07457e4a-e2bc-4e1b-8c34-e2ae88188d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986363260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.986363260
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4254662062
Short name T284
Test name
Test status
Simulation time 268285425 ps
CPU time 1.9 seconds
Started Mar 24 02:37:39 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 215996 kb
Host smart-bfb2e5a2-6e57-4331-9c95-b8680224b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254662062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4254662062
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1454847824
Short name T270
Test name
Test status
Simulation time 86199184 ps
CPU time 0.84 seconds
Started Mar 24 02:37:41 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 205512 kb
Host smart-fa73cd72-735c-4714-8b90-c7fa9bcd2f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454847824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1454847824
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1664765387
Short name T415
Test name
Test status
Simulation time 7239174243 ps
CPU time 25.14 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:38:13 PM PDT 24
Peak memory 233604 kb
Host smart-2e797190-edee-4683-a0a4-150541f152b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664765387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1664765387
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3795742579
Short name T573
Test name
Test status
Simulation time 53495494 ps
CPU time 0.71 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:25 PM PDT 24
Peak memory 204244 kb
Host smart-032712a3-633e-4f3f-aa8b-3d2696c3dc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795742579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3795742579
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.910942790
Short name T322
Test name
Test status
Simulation time 553919911 ps
CPU time 4.1 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:34 PM PDT 24
Peak memory 219600 kb
Host smart-3e2393a6-8b7f-483b-917c-2e6781e8122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910942790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.910942790
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3066223199
Short name T276
Test name
Test status
Simulation time 20650068 ps
CPU time 0.81 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:31 PM PDT 24
Peak memory 206268 kb
Host smart-bfc602ee-c21c-45c1-81bc-cb6ba00bc3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066223199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3066223199
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1226460760
Short name T319
Test name
Test status
Simulation time 1419241050 ps
CPU time 6.91 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:31 PM PDT 24
Peak memory 221240 kb
Host smart-6dc2c235-9b9e-4707-a4c0-9507cc4e27fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226460760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1226460760
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2096442517
Short name T926
Test name
Test status
Simulation time 2718593497 ps
CPU time 50.35 seconds
Started Mar 24 02:39:27 PM PDT 24
Finished Mar 24 02:40:17 PM PDT 24
Peak memory 248780 kb
Host smart-958e21dc-2ba0-4f7a-b562-1de66aad23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096442517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2096442517
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1697344789
Short name T757
Test name
Test status
Simulation time 19188394402 ps
CPU time 45.87 seconds
Started Mar 24 02:39:26 PM PDT 24
Finished Mar 24 02:40:12 PM PDT 24
Peak memory 232436 kb
Host smart-08e22a88-5066-404d-b12b-8eb9a7530a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697344789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1697344789
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.98440916
Short name T616
Test name
Test status
Simulation time 1212286402 ps
CPU time 7.47 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 233220 kb
Host smart-6c306e8c-5942-409e-82fa-757a5de821bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98440916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.98440916
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2186480313
Short name T910
Test name
Test status
Simulation time 1889954718 ps
CPU time 8.48 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:39 PM PDT 24
Peak memory 233248 kb
Host smart-fee8fa49-0f18-4115-8009-005f235c5581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186480313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2186480313
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2541223917
Short name T987
Test name
Test status
Simulation time 7906445507 ps
CPU time 6.35 seconds
Started Mar 24 02:39:19 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 216348 kb
Host smart-aa8d8433-ef92-46c1-8486-87d02389458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541223917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2541223917
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2192467455
Short name T933
Test name
Test status
Simulation time 8587144552 ps
CPU time 27.21 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 233252 kb
Host smart-a7cc411d-6c29-47e2-9f1d-e9c38dc62f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192467455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2192467455
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2753618698
Short name T432
Test name
Test status
Simulation time 636077815 ps
CPU time 4.92 seconds
Started Mar 24 02:39:21 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 224048 kb
Host smart-a016d19e-3e1c-4a50-80be-c845e79332dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753618698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2753618698
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3563404646
Short name T723
Test name
Test status
Simulation time 525555500 ps
CPU time 4.64 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 222268 kb
Host smart-74c31182-1820-4c29-b8f8-d5bae96bc066
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563404646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3563404646
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.474509434
Short name T730
Test name
Test status
Simulation time 52221786 ps
CPU time 1.07 seconds
Started Mar 24 02:39:28 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 206500 kb
Host smart-45fb2f57-8c1d-4d3b-9150-0551743db736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474509434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.474509434
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.210826245
Short name T734
Test name
Test status
Simulation time 8582054721 ps
CPU time 12.67 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 215996 kb
Host smart-eb6adfee-57ca-4268-842e-79a0e45cfd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210826245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.210826245
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.209047634
Short name T317
Test name
Test status
Simulation time 3973026893 ps
CPU time 10.66 seconds
Started Mar 24 02:39:18 PM PDT 24
Finished Mar 24 02:39:29 PM PDT 24
Peak memory 216004 kb
Host smart-b86919ac-5af3-48cc-8eb3-647b0dcb32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209047634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.209047634
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2769314631
Short name T968
Test name
Test status
Simulation time 181341308 ps
CPU time 1.43 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 207648 kb
Host smart-f87017b7-c8e8-4088-a53d-3d7ade8402c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769314631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2769314631
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3509718518
Short name T71
Test name
Test status
Simulation time 76411023 ps
CPU time 0.96 seconds
Started Mar 24 02:39:20 PM PDT 24
Finished Mar 24 02:39:21 PM PDT 24
Peak memory 205272 kb
Host smart-cba07bc9-9787-4d16-8c61-f71ef62d7be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509718518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3509718518
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1443926156
Short name T577
Test name
Test status
Simulation time 1900695540 ps
CPU time 3.62 seconds
Started Mar 24 02:39:23 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 233660 kb
Host smart-144c8210-2631-4779-a0e8-be76107cf0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443926156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1443926156
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2676221190
Short name T447
Test name
Test status
Simulation time 46228978 ps
CPU time 0.71 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 204844 kb
Host smart-e55bd314-a3ce-4572-9bb5-e4026a75dd25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676221190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2676221190
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3287968188
Short name T200
Test name
Test status
Simulation time 127284395 ps
CPU time 2.74 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:27 PM PDT 24
Peak memory 218244 kb
Host smart-39c93d8d-0525-4ced-bdfe-110294d73a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287968188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3287968188
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2176082634
Short name T7
Test name
Test status
Simulation time 35534472 ps
CPU time 0.74 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 204792 kb
Host smart-019601e2-5a1b-4c28-828e-6f2375c6aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176082634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2176082634
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1657139919
Short name T248
Test name
Test status
Simulation time 194324994930 ps
CPU time 377.01 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:45:47 PM PDT 24
Peak memory 249112 kb
Host smart-3daa369f-569f-4cac-af35-fc138f1cbb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657139919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1657139919
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2821849092
Short name T971
Test name
Test status
Simulation time 20542323985 ps
CPU time 63.84 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 235672 kb
Host smart-8b98bf31-1fbe-4b82-ba70-abc1864a242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821849092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2821849092
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.862167405
Short name T714
Test name
Test status
Simulation time 20367485178 ps
CPU time 13.11 seconds
Started Mar 24 02:39:26 PM PDT 24
Finished Mar 24 02:39:39 PM PDT 24
Peak memory 231436 kb
Host smart-c5419dd1-2a52-43ca-90de-6020fe83c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862167405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.862167405
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1548530005
Short name T961
Test name
Test status
Simulation time 5611306135 ps
CPU time 11.09 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 233172 kb
Host smart-830da6e8-d0cd-4b52-9e09-d417c988031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548530005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1548530005
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3645913854
Short name T4
Test name
Test status
Simulation time 439041226 ps
CPU time 2.43 seconds
Started Mar 24 02:39:28 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 218236 kb
Host smart-0dfe245c-315c-49e8-9260-18fc418f895d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645913854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3645913854
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.58587904
Short name T584
Test name
Test status
Simulation time 9827232154 ps
CPU time 10.38 seconds
Started Mar 24 02:39:26 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 217544 kb
Host smart-df471b2f-4c5e-454a-a730-9f16e5ea1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58587904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.58587904
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1386651373
Short name T709
Test name
Test status
Simulation time 905316472 ps
CPU time 5.17 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 227316 kb
Host smart-943c2dc8-14b0-48ac-aa92-6a0821b4a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386651373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1386651373
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.13564891
Short name T339
Test name
Test status
Simulation time 613082663 ps
CPU time 4.78 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 219452 kb
Host smart-48f377f4-6ea3-4c2a-87a4-bb7f6b76434f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13564891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direc
t.13564891
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.716044298
Short name T23
Test name
Test status
Simulation time 62172319393 ps
CPU time 161.44 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:42:12 PM PDT 24
Peak memory 261892 kb
Host smart-ecc431f6-8c7e-40c2-ba55-237712ad6801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716044298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.716044298
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2865530011
Short name T381
Test name
Test status
Simulation time 6665174203 ps
CPU time 34 seconds
Started Mar 24 02:39:23 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 216000 kb
Host smart-0f616468-e62d-4342-8ac1-d54e4f19012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865530011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2865530011
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1697696897
Short name T582
Test name
Test status
Simulation time 6363101377 ps
CPU time 17.41 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 216068 kb
Host smart-fb66e313-c36e-43a7-80a5-110e4676ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697696897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1697696897
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.278165622
Short name T724
Test name
Test status
Simulation time 72258750 ps
CPU time 0.87 seconds
Started Mar 24 02:39:24 PM PDT 24
Finished Mar 24 02:39:25 PM PDT 24
Peak memory 206328 kb
Host smart-f87cd198-5f24-4f5e-80c8-38a17a76daf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278165622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.278165622
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2865029118
Short name T962
Test name
Test status
Simulation time 106717249 ps
CPU time 1.04 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:26 PM PDT 24
Peak memory 206320 kb
Host smart-a47837a3-175d-402c-88c2-ff60c3d6c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865029118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2865029118
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.96714017
Short name T848
Test name
Test status
Simulation time 2669256367 ps
CPU time 4.64 seconds
Started Mar 24 02:39:25 PM PDT 24
Finished Mar 24 02:39:30 PM PDT 24
Peak memory 219576 kb
Host smart-ed463e1b-2e30-4a1c-9b3a-722f06cf2ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96714017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.96714017
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1721523761
Short name T927
Test name
Test status
Simulation time 14755642 ps
CPU time 0.73 seconds
Started Mar 24 02:39:41 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 204248 kb
Host smart-8f0aba3b-502c-4e7a-a22e-cf79520aa4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721523761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1721523761
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3891571488
Short name T210
Test name
Test status
Simulation time 2362089563 ps
CPU time 4.28 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 233472 kb
Host smart-10c50b44-3fb3-44d6-b404-c263bc99ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891571488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3891571488
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.419182947
Short name T372
Test name
Test status
Simulation time 79611600 ps
CPU time 0.8 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 204872 kb
Host smart-74c39abe-c775-4aa5-844b-67d48492a8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419182947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.419182947
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2243562709
Short name T687
Test name
Test status
Simulation time 42622198818 ps
CPU time 142.52 seconds
Started Mar 24 02:39:35 PM PDT 24
Finished Mar 24 02:41:58 PM PDT 24
Peak memory 250744 kb
Host smart-2b0354b2-961e-415c-9539-74da8f0137c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243562709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2243562709
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4091719692
Short name T22
Test name
Test status
Simulation time 106625459829 ps
CPU time 767.67 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:52:19 PM PDT 24
Peak memory 270172 kb
Host smart-c9a65532-dce5-46d8-90dd-7a6c6e2b89ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091719692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4091719692
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1426276939
Short name T234
Test name
Test status
Simulation time 45471459112 ps
CPU time 222.15 seconds
Started Mar 24 02:39:33 PM PDT 24
Finished Mar 24 02:43:16 PM PDT 24
Peak memory 236460 kb
Host smart-bf9509dc-f0e4-49be-9c33-dec92ede65d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426276939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1426276939
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3210968156
Short name T698
Test name
Test status
Simulation time 6471037253 ps
CPU time 35.78 seconds
Started Mar 24 02:39:32 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 237500 kb
Host smart-8cbe10c9-e59e-47f3-aed1-02a79e1b8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210968156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3210968156
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.643897097
Short name T545
Test name
Test status
Simulation time 693338696 ps
CPU time 4.21 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 217320 kb
Host smart-c1b2f353-44f6-4f53-8879-023e7a0f6681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643897097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.643897097
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.569529657
Short name T593
Test name
Test status
Simulation time 18390392987 ps
CPU time 16.28 seconds
Started Mar 24 02:39:35 PM PDT 24
Finished Mar 24 02:39:52 PM PDT 24
Peak memory 226956 kb
Host smart-971e55a1-f135-45ec-bed3-a9b6033c9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569529657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.569529657
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1106336014
Short name T677
Test name
Test status
Simulation time 27326077315 ps
CPU time 27.04 seconds
Started Mar 24 02:39:32 PM PDT 24
Finished Mar 24 02:40:00 PM PDT 24
Peak memory 219112 kb
Host smart-bb92c0ce-17e0-4ea5-8cf9-e5a11baf5313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106336014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1106336014
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3999534576
Short name T355
Test name
Test status
Simulation time 3945358952 ps
CPU time 12.05 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 233804 kb
Host smart-370b6f56-d681-487a-b9f5-62644ba9012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999534576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3999534576
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.412608011
Short name T699
Test name
Test status
Simulation time 750386453 ps
CPU time 5.25 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 218856 kb
Host smart-7f048967-d401-4b84-a388-db1eff19378b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412608011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.412608011
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2299634843
Short name T45
Test name
Test status
Simulation time 24696856135 ps
CPU time 228.4 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:43:19 PM PDT 24
Peak memory 255196 kb
Host smart-55c3ca70-d34e-4966-86b4-970da0a3e0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299634843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2299634843
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1154376931
Short name T703
Test name
Test status
Simulation time 12979370979 ps
CPU time 71.58 seconds
Started Mar 24 02:39:28 PM PDT 24
Finished Mar 24 02:40:41 PM PDT 24
Peak memory 215980 kb
Host smart-9c5d410f-d209-4b55-b828-15dea301fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154376931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1154376931
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2894415171
Short name T587
Test name
Test status
Simulation time 2357386006 ps
CPU time 7.5 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:38 PM PDT 24
Peak memory 216056 kb
Host smart-c12f46a2-45c6-4edb-8415-02e046bc70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894415171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2894415171
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2802242907
Short name T745
Test name
Test status
Simulation time 1704455740 ps
CPU time 14.36 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:46 PM PDT 24
Peak memory 216184 kb
Host smart-7afb88f5-fe3f-4cb5-b548-8165ebe569fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802242907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2802242907
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1124612412
Short name T318
Test name
Test status
Simulation time 153000585 ps
CPU time 1.01 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:32 PM PDT 24
Peak memory 206248 kb
Host smart-4512d266-76b4-464a-9e22-4eb23a8780af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124612412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1124612412
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.110615794
Short name T206
Test name
Test status
Simulation time 348857797 ps
CPU time 4.23 seconds
Started Mar 24 02:39:31 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 218016 kb
Host smart-12e987ea-6695-4f04-933b-be3e9b1e360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110615794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.110615794
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2827745103
Short name T608
Test name
Test status
Simulation time 43775728 ps
CPU time 0.74 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 204816 kb
Host smart-eaaa3bd9-ba88-4e23-8072-fe26a8068550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827745103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2827745103
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2641642084
Short name T144
Test name
Test status
Simulation time 1974133188 ps
CPU time 9.01 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 220232 kb
Host smart-9ba3cc01-a253-4151-aa0b-5d00fed53ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641642084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2641642084
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.457292802
Short name T847
Test name
Test status
Simulation time 15633894 ps
CPU time 0.78 seconds
Started Mar 24 02:39:34 PM PDT 24
Finished Mar 24 02:39:35 PM PDT 24
Peak memory 204908 kb
Host smart-79d8aceb-8090-4b38-8483-0c2f82804c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457292802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.457292802
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.914624383
Short name T255
Test name
Test status
Simulation time 48155014913 ps
CPU time 140.14 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:41:59 PM PDT 24
Peak memory 234924 kb
Host smart-09e13349-bcd8-4c36-bf86-a6d0297094d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914624383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.914624383
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1533746288
Short name T976
Test name
Test status
Simulation time 388264236 ps
CPU time 4.36 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:39:45 PM PDT 24
Peak memory 222552 kb
Host smart-c5a58c68-05e1-4e16-b20a-e8c117633e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533746288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1533746288
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1598978891
Short name T896
Test name
Test status
Simulation time 2623447239 ps
CPU time 7.34 seconds
Started Mar 24 02:39:35 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 236340 kb
Host smart-414875e4-fcf7-4c1f-b12a-57d8926dd9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598978891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1598978891
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3365150909
Short name T557
Test name
Test status
Simulation time 6674791886 ps
CPU time 11.96 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:39:51 PM PDT 24
Peak memory 224080 kb
Host smart-e307612f-d7d4-458d-86d1-437f677c728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365150909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3365150909
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2842899120
Short name T815
Test name
Test status
Simulation time 12475240853 ps
CPU time 11.13 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 233244 kb
Host smart-1176b5d2-83e9-4f62-8490-0eb045c163fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842899120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2842899120
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.460057827
Short name T193
Test name
Test status
Simulation time 982494046 ps
CPU time 4.83 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 224012 kb
Host smart-b28c155a-c186-4ffd-957f-f749373aac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460057827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.460057827
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1577751240
Short name T429
Test name
Test status
Simulation time 1171852761 ps
CPU time 4.28 seconds
Started Mar 24 02:39:36 PM PDT 24
Finished Mar 24 02:39:40 PM PDT 24
Peak memory 218744 kb
Host smart-14617d0f-0a9a-4afa-bf7f-7bc8a03800b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577751240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1577751240
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.88887927
Short name T725
Test name
Test status
Simulation time 152424163884 ps
CPU time 270.91 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:44:08 PM PDT 24
Peak memory 268092 kb
Host smart-9e8d3965-26d9-4be4-bd99-574f44a275d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88887927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress
_all.88887927
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2056217020
Short name T630
Test name
Test status
Simulation time 10213358832 ps
CPU time 28.58 seconds
Started Mar 24 02:39:30 PM PDT 24
Finished Mar 24 02:39:59 PM PDT 24
Peak memory 215964 kb
Host smart-4ce6789f-af2f-4491-8b31-905646b53988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056217020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2056217020
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3148610718
Short name T288
Test name
Test status
Simulation time 34755673380 ps
CPU time 7.47 seconds
Started Mar 24 02:39:32 PM PDT 24
Finished Mar 24 02:39:40 PM PDT 24
Peak memory 216012 kb
Host smart-9e2ec93f-850b-45f7-b4b7-ccab51166baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148610718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3148610718
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3888686602
Short name T332
Test name
Test status
Simulation time 1520008202 ps
CPU time 4.56 seconds
Started Mar 24 02:39:43 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 215936 kb
Host smart-25e0c338-0020-4d35-b009-eabf450cf572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888686602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3888686602
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2946744665
Short name T19
Test name
Test status
Simulation time 108977571 ps
CPU time 0.98 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:38 PM PDT 24
Peak memory 205252 kb
Host smart-a68ee785-829f-40aa-8d6b-28f8de47948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946744665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2946744665
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.425621603
Short name T306
Test name
Test status
Simulation time 5703673202 ps
CPU time 24.76 seconds
Started Mar 24 02:39:38 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 233420 kb
Host smart-1d7cbb96-c70e-4721-b1da-cb39879a1928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425621603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.425621603
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3805661333
Short name T194
Test name
Test status
Simulation time 121345133 ps
CPU time 2.79 seconds
Started Mar 24 02:39:38 PM PDT 24
Finished Mar 24 02:39:41 PM PDT 24
Peak memory 219568 kb
Host smart-2bccf041-8eda-47af-a458-8b3d0703620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805661333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3805661333
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1637452269
Short name T880
Test name
Test status
Simulation time 21009845 ps
CPU time 0.77 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:38 PM PDT 24
Peak memory 205252 kb
Host smart-42b9c8bc-d8a3-43f9-b025-57dcdcccb16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637452269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1637452269
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4064160505
Short name T423
Test name
Test status
Simulation time 2442608777 ps
CPU time 43.56 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:40:25 PM PDT 24
Peak memory 247200 kb
Host smart-9e61d658-d2ae-4520-9867-4b7ecb3ab7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064160505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4064160505
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1200141366
Short name T791
Test name
Test status
Simulation time 25492900240 ps
CPU time 82.57 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 253196 kb
Host smart-c194f74d-eeaa-469c-aaa4-fbfc8b6146d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200141366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1200141366
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1395674256
Short name T230
Test name
Test status
Simulation time 24761790584 ps
CPU time 171.44 seconds
Started Mar 24 02:39:44 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 253316 kb
Host smart-deb52c96-c469-470c-82c6-44ec6f5f785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395674256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1395674256
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.816738608
Short name T257
Test name
Test status
Simulation time 13696877331 ps
CPU time 40.73 seconds
Started Mar 24 02:39:38 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 232384 kb
Host smart-d8cc3dad-eb41-41c5-be97-39662649db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816738608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.816738608
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2773731283
Short name T664
Test name
Test status
Simulation time 585043454 ps
CPU time 4.84 seconds
Started Mar 24 02:39:36 PM PDT 24
Finished Mar 24 02:39:41 PM PDT 24
Peak memory 233836 kb
Host smart-4615b290-3537-4634-9a17-5f486d7c5440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773731283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2773731283
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3202673736
Short name T916
Test name
Test status
Simulation time 2122589974 ps
CPU time 4.47 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:41 PM PDT 24
Peak memory 218196 kb
Host smart-77949bc5-b597-40ec-be41-5ef86f488fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202673736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3202673736
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.25943834
Short name T374
Test name
Test status
Simulation time 7358474621 ps
CPU time 13.31 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:39:52 PM PDT 24
Peak memory 227044 kb
Host smart-48b3505d-4064-4304-807d-51969f108761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25943834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.25943834
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2346004350
Short name T224
Test name
Test status
Simulation time 379408187 ps
CPU time 3.13 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:39:44 PM PDT 24
Peak memory 216544 kb
Host smart-95757459-14ec-456d-99a9-195e7c28380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346004350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2346004350
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.378985281
Short name T507
Test name
Test status
Simulation time 3119941233 ps
CPU time 3.87 seconds
Started Mar 24 02:39:38 PM PDT 24
Finished Mar 24 02:39:42 PM PDT 24
Peak memory 220116 kb
Host smart-1be91b65-1b39-4561-a902-de209eaf98d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=378985281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.378985281
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.824522330
Short name T823
Test name
Test status
Simulation time 67857118715 ps
CPU time 52.04 seconds
Started Mar 24 02:39:35 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 215984 kb
Host smart-558f2634-290b-470b-9396-6772abca69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824522330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.824522330
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.662619371
Short name T272
Test name
Test status
Simulation time 8328551090 ps
CPU time 6.76 seconds
Started Mar 24 02:39:39 PM PDT 24
Finished Mar 24 02:39:46 PM PDT 24
Peak memory 215988 kb
Host smart-38143bc8-e2a0-4ed4-948f-e6fe5827aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662619371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.662619371
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2973971835
Short name T364
Test name
Test status
Simulation time 303874486 ps
CPU time 1.34 seconds
Started Mar 24 02:39:37 PM PDT 24
Finished Mar 24 02:39:39 PM PDT 24
Peak memory 215952 kb
Host smart-bde36527-9574-4804-a5f2-b02de2d19dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973971835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2973971835
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2409609514
Short name T581
Test name
Test status
Simulation time 88362195 ps
CPU time 0.88 seconds
Started Mar 24 02:39:35 PM PDT 24
Finished Mar 24 02:39:36 PM PDT 24
Peak memory 206348 kb
Host smart-11091802-5ea8-4e87-b31b-fa2792f88bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409609514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2409609514
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2233363551
Short name T441
Test name
Test status
Simulation time 2901822501 ps
CPU time 7.7 seconds
Started Mar 24 02:39:43 PM PDT 24
Finished Mar 24 02:39:51 PM PDT 24
Peak memory 218220 kb
Host smart-ca2c6e42-b04a-4524-bb73-ee86cf56ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233363551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2233363551
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1145780608
Short name T824
Test name
Test status
Simulation time 35081334 ps
CPU time 0.8 seconds
Started Mar 24 02:39:51 PM PDT 24
Finished Mar 24 02:39:52 PM PDT 24
Peak memory 205248 kb
Host smart-d404eded-771a-4fea-8d85-67466d6d7ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145780608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1145780608
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1296588794
Short name T439
Test name
Test status
Simulation time 116475092 ps
CPU time 2.43 seconds
Started Mar 24 02:39:41 PM PDT 24
Finished Mar 24 02:39:44 PM PDT 24
Peak memory 219384 kb
Host smart-52970401-31bc-4546-8585-d2ab0e4bc233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296588794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1296588794
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2469825296
Short name T549
Test name
Test status
Simulation time 21445477 ps
CPU time 0.81 seconds
Started Mar 24 02:39:43 PM PDT 24
Finished Mar 24 02:39:44 PM PDT 24
Peak memory 206268 kb
Host smart-8c5ab6e5-08cb-47d5-a7c9-c2e5b25aad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469825296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2469825296
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.181712494
Short name T11
Test name
Test status
Simulation time 5462188991 ps
CPU time 22.35 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 249896 kb
Host smart-87bd3b00-301a-47a2-8018-96a87fc2cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181712494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.181712494
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1515082084
Short name T586
Test name
Test status
Simulation time 20946382691 ps
CPU time 65.58 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 234552 kb
Host smart-32b15a17-52d8-427c-9006-41ec518eabb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515082084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1515082084
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3198729437
Short name T357
Test name
Test status
Simulation time 220983124100 ps
CPU time 376.07 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:45:59 PM PDT 24
Peak memory 251912 kb
Host smart-6d458980-b133-4cd8-8362-f6de31da3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198729437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3198729437
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3624277917
Short name T435
Test name
Test status
Simulation time 28608617243 ps
CPU time 50.39 seconds
Started Mar 24 02:39:51 PM PDT 24
Finished Mar 24 02:40:41 PM PDT 24
Peak memory 240544 kb
Host smart-5ee0827a-2878-44cd-909f-fde04282b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624277917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3624277917
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3407685483
Short name T789
Test name
Test status
Simulation time 204717413 ps
CPU time 4 seconds
Started Mar 24 02:39:43 PM PDT 24
Finished Mar 24 02:39:47 PM PDT 24
Peak memory 233288 kb
Host smart-2cb55cbd-fcdb-49bd-9212-b01d6d08183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407685483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3407685483
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1289595476
Short name T867
Test name
Test status
Simulation time 60734186807 ps
CPU time 45.47 seconds
Started Mar 24 02:39:44 PM PDT 24
Finished Mar 24 02:40:30 PM PDT 24
Peak memory 230900 kb
Host smart-27063a1a-6c2d-49ce-a135-4ef5f7ca093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289595476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1289595476
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2806885885
Short name T613
Test name
Test status
Simulation time 115133144 ps
CPU time 2.42 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:39:44 PM PDT 24
Peak memory 232272 kb
Host smart-dd2dd82c-37ec-4ce0-8dda-d8f00edd4277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806885885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2806885885
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2718065584
Short name T383
Test name
Test status
Simulation time 943974524 ps
CPU time 7.78 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:39:49 PM PDT 24
Peak memory 219752 kb
Host smart-c4cc7709-cd7e-42bc-b4f7-d2478979252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718065584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2718065584
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.200469501
Short name T416
Test name
Test status
Simulation time 2540935353 ps
CPU time 4.67 seconds
Started Mar 24 02:39:40 PM PDT 24
Finished Mar 24 02:39:46 PM PDT 24
Peak memory 221676 kb
Host smart-22c94a87-5999-4353-84f5-db79af77cee7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=200469501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.200469501
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3937822396
Short name T146
Test name
Test status
Simulation time 11017841498 ps
CPU time 105.59 seconds
Started Mar 24 02:39:41 PM PDT 24
Finished Mar 24 02:41:27 PM PDT 24
Peak memory 264716 kb
Host smart-a2872af9-15a0-47b7-8524-a3637000e6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937822396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3937822396
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2680734048
Short name T610
Test name
Test status
Simulation time 66188212586 ps
CPU time 77.69 seconds
Started Mar 24 02:39:41 PM PDT 24
Finished Mar 24 02:40:59 PM PDT 24
Peak memory 216008 kb
Host smart-24650d2f-0416-42ee-9cae-e3df3c84f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680734048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2680734048
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3015636634
Short name T506
Test name
Test status
Simulation time 2165224868 ps
CPU time 11.69 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 216068 kb
Host smart-cdd09f28-04fa-4520-a64b-1be37a182371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015636634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3015636634
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.732435727
Short name T697
Test name
Test status
Simulation time 69415602 ps
CPU time 2.33 seconds
Started Mar 24 02:39:44 PM PDT 24
Finished Mar 24 02:39:46 PM PDT 24
Peak memory 216024 kb
Host smart-ea57bbcb-c922-41f5-9d90-22a642e8d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732435727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.732435727
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.400110429
Short name T588
Test name
Test status
Simulation time 96921536 ps
CPU time 0.77 seconds
Started Mar 24 02:39:42 PM PDT 24
Finished Mar 24 02:39:43 PM PDT 24
Peak memory 205288 kb
Host smart-b319b90d-51cf-4c4f-bd7d-b6294ba6abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400110429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.400110429
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.115544552
Short name T752
Test name
Test status
Simulation time 5472728466 ps
CPU time 7.45 seconds
Started Mar 24 02:39:43 PM PDT 24
Finished Mar 24 02:39:51 PM PDT 24
Peak memory 232840 kb
Host smart-72fc2f1f-5873-4be0-92e0-756a1c2ba295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115544552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.115544552
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4272699360
Short name T600
Test name
Test status
Simulation time 44330970 ps
CPU time 0.7 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:39:47 PM PDT 24
Peak memory 204840 kb
Host smart-57008147-0635-4a6f-8faa-1b85b2fa9559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272699360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4272699360
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1454970703
Short name T589
Test name
Test status
Simulation time 340505477 ps
CPU time 2.29 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:39:52 PM PDT 24
Peak memory 216356 kb
Host smart-26593449-9177-46d7-8a9d-00f4e480e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454970703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1454970703
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.209613520
Short name T454
Test name
Test status
Simulation time 70697060 ps
CPU time 0.7 seconds
Started Mar 24 02:39:44 PM PDT 24
Finished Mar 24 02:39:45 PM PDT 24
Peak memory 205220 kb
Host smart-5bfb05d5-3cb1-427f-bb61-8d727921fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209613520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.209613520
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.680781047
Short name T157
Test name
Test status
Simulation time 476905857130 ps
CPU time 282.94 seconds
Started Mar 24 02:39:48 PM PDT 24
Finished Mar 24 02:44:32 PM PDT 24
Peak memory 263056 kb
Host smart-c9d60b3c-3d74-4845-af20-a158c6c5df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680781047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.680781047
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.784012520
Short name T722
Test name
Test status
Simulation time 30369087872 ps
CPU time 103.54 seconds
Started Mar 24 02:39:47 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 240640 kb
Host smart-a1a26033-3317-4dfc-a7b7-ca8374ee7329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784012520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.784012520
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2097508999
Short name T169
Test name
Test status
Simulation time 194261374581 ps
CPU time 632.45 seconds
Started Mar 24 02:39:47 PM PDT 24
Finished Mar 24 02:50:20 PM PDT 24
Peak memory 266488 kb
Host smart-c3769148-c677-4a7d-883a-68f02be67e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097508999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2097508999
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.95145638
Short name T644
Test name
Test status
Simulation time 1424961237 ps
CPU time 8.09 seconds
Started Mar 24 02:39:45 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 233120 kb
Host smart-5e6590c4-6a60-49bb-8db6-9557a33c64c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95145638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.95145638
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2689405920
Short name T938
Test name
Test status
Simulation time 14337922423 ps
CPU time 40.53 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:40:27 PM PDT 24
Peak memory 230832 kb
Host smart-c166e7f3-6c7c-41b5-b080-ed0234c07595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689405920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2689405920
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.786702884
Short name T426
Test name
Test status
Simulation time 130910381 ps
CPU time 3.78 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:39:50 PM PDT 24
Peak memory 233264 kb
Host smart-fde2355a-b6fd-4fc5-b032-c1527de115e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786702884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.786702884
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3546040617
Short name T538
Test name
Test status
Simulation time 21308780194 ps
CPU time 21.79 seconds
Started Mar 24 02:39:45 PM PDT 24
Finished Mar 24 02:40:07 PM PDT 24
Peak memory 218312 kb
Host smart-470bf8c9-e52f-413e-9439-3841ece80cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546040617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3546040617
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2294785021
Short name T895
Test name
Test status
Simulation time 123075436 ps
CPU time 3.64 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:39:50 PM PDT 24
Peak memory 221784 kb
Host smart-fb209b53-fc59-4f2c-bb90-1d2da7b80733
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2294785021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2294785021
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3311462684
Short name T906
Test name
Test status
Simulation time 4172671735 ps
CPU time 24.91 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 216044 kb
Host smart-e6dc3a76-3d5f-4c63-b6b1-46f8b3a8c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311462684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3311462684
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3056773199
Short name T662
Test name
Test status
Simulation time 779362914 ps
CPU time 5.26 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 215992 kb
Host smart-7780828f-5213-4078-90fd-dc7522f271b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056773199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3056773199
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.512019765
Short name T660
Test name
Test status
Simulation time 122616199 ps
CPU time 2.09 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:39:48 PM PDT 24
Peak memory 216156 kb
Host smart-4ebf2448-6fab-4d93-adf2-f0af8e5edf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512019765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.512019765
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3625125029
Short name T467
Test name
Test status
Simulation time 70039672 ps
CPU time 0.87 seconds
Started Mar 24 02:39:48 PM PDT 24
Finished Mar 24 02:39:50 PM PDT 24
Peak memory 205308 kb
Host smart-243d24c0-1773-4633-a319-ba34a7e92380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625125029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3625125029
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.832392713
Short name T835
Test name
Test status
Simulation time 29373787501 ps
CPU time 22.22 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 217188 kb
Host smart-f0dc338c-9c60-449a-9741-2de24e47f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832392713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.832392713
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2518164389
Short name T914
Test name
Test status
Simulation time 14624230 ps
CPU time 0.75 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 204796 kb
Host smart-5f7ddf6d-a3cc-4865-adf2-88a6d269e776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518164389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2518164389
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3207066968
Short name T917
Test name
Test status
Simulation time 696317438 ps
CPU time 4.79 seconds
Started Mar 24 02:39:53 PM PDT 24
Finished Mar 24 02:39:58 PM PDT 24
Peak memory 224044 kb
Host smart-8229303d-1b07-4c35-953a-5750edd19d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207066968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3207066968
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2423680421
Short name T886
Test name
Test status
Simulation time 24256826 ps
CPU time 0.83 seconds
Started Mar 24 02:39:44 PM PDT 24
Finished Mar 24 02:39:45 PM PDT 24
Peak memory 205940 kb
Host smart-498adb46-0f1d-4296-9de9-ce3a5a6dd2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423680421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2423680421
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.926775721
Short name T940
Test name
Test status
Simulation time 16349385380 ps
CPU time 67.48 seconds
Started Mar 24 02:39:51 PM PDT 24
Finished Mar 24 02:40:59 PM PDT 24
Peak memory 237064 kb
Host smart-2d4e4476-65b5-4ece-830a-b5bf8e7f4500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926775721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.926775721
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.678287514
Short name T180
Test name
Test status
Simulation time 34327102495 ps
CPU time 162.72 seconds
Started Mar 24 02:39:53 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 259028 kb
Host smart-8795832c-ba25-4ee1-978d-c625914f2704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678287514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.678287514
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2205524792
Short name T261
Test name
Test status
Simulation time 138770011199 ps
CPU time 208.54 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:43:18 PM PDT 24
Peak memory 252624 kb
Host smart-8ba6dc02-47f3-4209-a382-8e721eae71f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205524792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2205524792
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.304859813
Short name T617
Test name
Test status
Simulation time 5928710686 ps
CPU time 31.83 seconds
Started Mar 24 02:39:51 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 246996 kb
Host smart-441caa3c-ce8b-4689-8086-ff20a68b276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304859813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.304859813
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2010635730
Short name T412
Test name
Test status
Simulation time 163552798 ps
CPU time 4.3 seconds
Started Mar 24 02:39:50 PM PDT 24
Finished Mar 24 02:39:54 PM PDT 24
Peak memory 233520 kb
Host smart-aa7889b8-36ad-4ce0-9c76-93e218e258f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010635730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2010635730
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2406733721
Short name T868
Test name
Test status
Simulation time 25810301099 ps
CPU time 74.49 seconds
Started Mar 24 02:39:55 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 240292 kb
Host smart-f1ebbfbc-2f1a-4ebd-826e-98e98d600e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406733721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2406733721
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3698136048
Short name T408
Test name
Test status
Simulation time 518171914 ps
CPU time 5.29 seconds
Started Mar 24 02:39:52 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 232716 kb
Host smart-04fd4ee2-e957-4d61-8920-90f0f9d52f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698136048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3698136048
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.395795205
Short name T176
Test name
Test status
Simulation time 3706633703 ps
CPU time 13.56 seconds
Started Mar 24 02:39:52 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 218236 kb
Host smart-f1b08744-ba52-4430-8558-7fc487ad9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395795205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.395795205
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3629642507
Short name T369
Test name
Test status
Simulation time 2234600614 ps
CPU time 5.43 seconds
Started Mar 24 02:39:50 PM PDT 24
Finished Mar 24 02:39:56 PM PDT 24
Peak memory 219604 kb
Host smart-2d1c6cee-e0f0-47ce-8499-8680aa8f65dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3629642507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3629642507
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1348027303
Short name T376
Test name
Test status
Simulation time 50483357035 ps
CPU time 79.56 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 216008 kb
Host smart-4fffd755-6971-4f44-af25-ec7a0b39cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348027303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1348027303
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2190501584
Short name T351
Test name
Test status
Simulation time 3802192426 ps
CPU time 15.26 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:40:01 PM PDT 24
Peak memory 215984 kb
Host smart-f73473fa-667f-44fd-a86e-93f4547940b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190501584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2190501584
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2980965620
Short name T502
Test name
Test status
Simulation time 956365203 ps
CPU time 4.08 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:39:53 PM PDT 24
Peak memory 216000 kb
Host smart-84b36411-e822-4ffc-828b-1acc9f17e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980965620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2980965620
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1119586892
Short name T343
Test name
Test status
Simulation time 194119438 ps
CPU time 0.9 seconds
Started Mar 24 02:39:46 PM PDT 24
Finished Mar 24 02:39:47 PM PDT 24
Peak memory 206368 kb
Host smart-9aac04dc-29c5-42fe-aeda-5d14abc862ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119586892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1119586892
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1219717873
Short name T675
Test name
Test status
Simulation time 282778074 ps
CPU time 2.67 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:39:52 PM PDT 24
Peak memory 233480 kb
Host smart-cb9a9d2f-e648-487d-af23-745420eadb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219717873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1219717873
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3407037504
Short name T716
Test name
Test status
Simulation time 86717476 ps
CPU time 0.68 seconds
Started Mar 24 02:39:54 PM PDT 24
Finished Mar 24 02:39:55 PM PDT 24
Peak memory 205204 kb
Host smart-aa385803-9600-4de2-bf72-acdbb92bf223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407037504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3407037504
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1634190621
Short name T974
Test name
Test status
Simulation time 84046174 ps
CPU time 2.54 seconds
Started Mar 24 02:39:54 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 233272 kb
Host smart-ecce843e-ac9b-4216-9508-d564c5320adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634190621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1634190621
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.722495278
Short name T414
Test name
Test status
Simulation time 15934011 ps
CPU time 0.73 seconds
Started Mar 24 02:39:52 PM PDT 24
Finished Mar 24 02:39:53 PM PDT 24
Peak memory 206160 kb
Host smart-64f92fca-07f4-4bc8-b976-61c094e3c04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722495278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.722495278
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4159574271
Short name T405
Test name
Test status
Simulation time 5360323302 ps
CPU time 32.21 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 238772 kb
Host smart-a31bbbd7-6f4f-4cdf-9ba2-84fafb96bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159574271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4159574271
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1380603887
Short name T263
Test name
Test status
Simulation time 40753746553 ps
CPU time 262.46 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:44:23 PM PDT 24
Peak memory 249820 kb
Host smart-befe6434-0fb0-4de7-b113-b3b9f775f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380603887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1380603887
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3331634608
Short name T471
Test name
Test status
Simulation time 7517256502 ps
CPU time 100.64 seconds
Started Mar 24 02:40:00 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 256320 kb
Host smart-61526be9-0e75-45ea-9bf0-9d2a0565f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331634608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3331634608
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4204559506
Short name T924
Test name
Test status
Simulation time 1248929665 ps
CPU time 11.85 seconds
Started Mar 24 02:39:57 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 233536 kb
Host smart-8d92e3ce-67d8-437d-b2f3-55e983128ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204559506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4204559506
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.304866646
Short name T455
Test name
Test status
Simulation time 1229995345 ps
CPU time 3.86 seconds
Started Mar 24 02:39:53 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 218192 kb
Host smart-bc68918c-5dda-4c5d-91f1-f3a1260b8d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304866646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.304866646
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1561820701
Short name T346
Test name
Test status
Simulation time 3849510381 ps
CPU time 11.05 seconds
Started Mar 24 02:39:50 PM PDT 24
Finished Mar 24 02:40:02 PM PDT 24
Peak memory 252912 kb
Host smart-6a72b0b1-7bfa-41f7-8100-082511cc4a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561820701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1561820701
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2912105275
Short name T620
Test name
Test status
Simulation time 1549451101 ps
CPU time 6.02 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:39:55 PM PDT 24
Peak memory 232924 kb
Host smart-f1a62669-9206-4b77-b99d-5b1f367ade14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912105275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2912105275
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4214560413
Short name T164
Test name
Test status
Simulation time 58325402092 ps
CPU time 14.75 seconds
Started Mar 24 02:39:50 PM PDT 24
Finished Mar 24 02:40:05 PM PDT 24
Peak memory 224048 kb
Host smart-ececf972-be53-4a35-a141-b16dff12fbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214560413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4214560413
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.442034766
Short name T801
Test name
Test status
Simulation time 208103217 ps
CPU time 3.85 seconds
Started Mar 24 02:39:58 PM PDT 24
Finished Mar 24 02:40:02 PM PDT 24
Peak memory 222280 kb
Host smart-918f1243-0469-4255-97d1-43df2fc18d2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=442034766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.442034766
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1682564920
Short name T443
Test name
Test status
Simulation time 49985189858 ps
CPU time 52.11 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 240912 kb
Host smart-b2719398-f48b-4bc6-b0c0-dd5bcef7143d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682564920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1682564920
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3109199496
Short name T842
Test name
Test status
Simulation time 6150194128 ps
CPU time 43.84 seconds
Started Mar 24 02:39:49 PM PDT 24
Finished Mar 24 02:40:33 PM PDT 24
Peak memory 216084 kb
Host smart-76afbdd5-eb86-4365-8edb-ef5ea08d1546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109199496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3109199496
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.230685254
Short name T637
Test name
Test status
Simulation time 1614778994 ps
CPU time 7.2 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:40:04 PM PDT 24
Peak memory 215924 kb
Host smart-3d55d2b5-95ef-4d60-b6e6-86658c014011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230685254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.230685254
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1939151894
Short name T465
Test name
Test status
Simulation time 336439448 ps
CPU time 6.61 seconds
Started Mar 24 02:39:50 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 216028 kb
Host smart-8b7767ad-2fca-433a-ade0-1bbd5119af16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939151894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1939151894
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.454747592
Short name T535
Test name
Test status
Simulation time 128572768 ps
CPU time 1.05 seconds
Started Mar 24 02:39:52 PM PDT 24
Finished Mar 24 02:39:53 PM PDT 24
Peak memory 205300 kb
Host smart-dc474601-2241-4c94-8d99-261417df302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454747592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.454747592
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3150788592
Short name T442
Test name
Test status
Simulation time 5534113506 ps
CPU time 5.99 seconds
Started Mar 24 02:39:51 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 224416 kb
Host smart-ef0569df-96f2-40c5-8386-a1a318a2cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150788592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3150788592
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.256659699
Short name T790
Test name
Test status
Simulation time 31503875 ps
CPU time 0.71 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:40:01 PM PDT 24
Peak memory 204296 kb
Host smart-27d53b32-6735-4d46-bcc4-8b326f21e22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256659699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.256659699
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.282670602
Short name T735
Test name
Test status
Simulation time 675349591 ps
CPU time 2.43 seconds
Started Mar 24 02:39:59 PM PDT 24
Finished Mar 24 02:40:01 PM PDT 24
Peak memory 216444 kb
Host smart-bff53834-b089-41bb-9cb1-88022e9f25e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282670602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.282670602
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2836938518
Short name T746
Test name
Test status
Simulation time 171695959 ps
CPU time 0.8 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 205904 kb
Host smart-168f6b73-da3c-4605-8735-e0ef419d5a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836938518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2836938518
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4164178937
Short name T226
Test name
Test status
Simulation time 18295628478 ps
CPU time 126.84 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 250772 kb
Host smart-6ec1ad7c-0069-47fa-b53a-7eb963201572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164178937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4164178937
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1534045760
Short name T187
Test name
Test status
Simulation time 488337467991 ps
CPU time 787.74 seconds
Started Mar 24 02:40:00 PM PDT 24
Finished Mar 24 02:53:08 PM PDT 24
Peak memory 265044 kb
Host smart-13ba5569-c835-4319-8c55-6ca90d3ee5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534045760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1534045760
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.522991531
Short name T742
Test name
Test status
Simulation time 22922354905 ps
CPU time 70.91 seconds
Started Mar 24 02:40:03 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 240508 kb
Host smart-b65cd624-b9ff-42e5-8c28-5c25576831dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522991531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.522991531
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3989134629
Short name T373
Test name
Test status
Simulation time 15647678218 ps
CPU time 13.26 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 233172 kb
Host smart-c7d31046-577c-4356-be63-42090c014e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989134629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3989134629
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4278766043
Short name T718
Test name
Test status
Simulation time 9541692400 ps
CPU time 32.81 seconds
Started Mar 24 02:39:59 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 233204 kb
Host smart-fdd29b95-f887-40bd-a230-c70a2c252e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278766043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4278766043
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2819238937
Short name T211
Test name
Test status
Simulation time 5866136472 ps
CPU time 20.23 seconds
Started Mar 24 02:39:58 PM PDT 24
Finished Mar 24 02:40:18 PM PDT 24
Peak memory 224180 kb
Host smart-b41876d1-c98b-478d-bd8d-ac61e42e6f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819238937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2819238937
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1909533794
Short name T199
Test name
Test status
Simulation time 33894022921 ps
CPU time 27.57 seconds
Started Mar 24 02:39:53 PM PDT 24
Finished Mar 24 02:40:20 PM PDT 24
Peak memory 232320 kb
Host smart-2757aa5f-6d3c-4701-a682-c2224c05f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909533794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1909533794
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1514745249
Short name T802
Test name
Test status
Simulation time 2819038691 ps
CPU time 5.6 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 221872 kb
Host smart-a193090f-5643-40a6-ba8e-2c0e69583dae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514745249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1514745249
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4251456085
Short name T140
Test name
Test status
Simulation time 9827045972 ps
CPU time 115.03 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 264548 kb
Host smart-798d1499-7d82-4812-95f3-7b3744759b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251456085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4251456085
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1748182604
Short name T740
Test name
Test status
Simulation time 3395578122 ps
CPU time 33.03 seconds
Started Mar 24 02:39:57 PM PDT 24
Finished Mar 24 02:40:30 PM PDT 24
Peak memory 216000 kb
Host smart-13cacd40-8528-4043-8a3d-91a327e03e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748182604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1748182604
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3020999385
Short name T855
Test name
Test status
Simulation time 37118101566 ps
CPU time 22.61 seconds
Started Mar 24 02:39:55 PM PDT 24
Finished Mar 24 02:40:18 PM PDT 24
Peak memory 216000 kb
Host smart-427ce897-0fd6-4e07-b9a0-87a1b3c2c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020999385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3020999385
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2891208715
Short name T711
Test name
Test status
Simulation time 25146624 ps
CPU time 1.29 seconds
Started Mar 24 02:39:57 PM PDT 24
Finished Mar 24 02:39:59 PM PDT 24
Peak memory 207732 kb
Host smart-be5410fd-5064-4a83-bb98-a78ea196a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891208715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2891208715
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4031647474
Short name T984
Test name
Test status
Simulation time 193748655 ps
CPU time 0.95 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:39:57 PM PDT 24
Peak memory 205304 kb
Host smart-9ba4bfeb-2f3b-427b-ad7a-fed2a909d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031647474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4031647474
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3038442551
Short name T768
Test name
Test status
Simulation time 154546561 ps
CPU time 4.31 seconds
Started Mar 24 02:39:56 PM PDT 24
Finished Mar 24 02:40:01 PM PDT 24
Peak memory 232944 kb
Host smart-0335ee22-9588-4e84-acf4-702bebed9acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038442551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3038442551
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2026854951
Short name T659
Test name
Test status
Simulation time 12268827 ps
CPU time 0.71 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:45 PM PDT 24
Peak memory 204816 kb
Host smart-5dade815-3ff1-470d-8063-1be5c404a1ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026854951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
026854951
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2469889335
Short name T202
Test name
Test status
Simulation time 534310391 ps
CPU time 2.74 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 218440 kb
Host smart-9f3b8ecf-0e87-49bb-b609-74ac0ef709e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469889335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2469889335
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1520147775
Short name T17
Test name
Test status
Simulation time 23879515 ps
CPU time 0.73 seconds
Started Mar 24 02:37:39 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 204888 kb
Host smart-4a1cbbcb-e4fb-457f-94b2-c4d0de6428d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520147775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1520147775
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3980721490
Short name T638
Test name
Test status
Simulation time 3473654877 ps
CPU time 16.31 seconds
Started Mar 24 02:37:45 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 236348 kb
Host smart-36f7b574-1059-4179-86d9-b47f05466d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980721490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3980721490
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2753525104
Short name T532
Test name
Test status
Simulation time 41717489386 ps
CPU time 174.11 seconds
Started Mar 24 02:37:46 PM PDT 24
Finished Mar 24 02:40:41 PM PDT 24
Peak memory 252180 kb
Host smart-80293636-8bf2-47ea-9d29-8909aa6d8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753525104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2753525104
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3510996578
Short name T365
Test name
Test status
Simulation time 2693941448 ps
CPU time 45.49 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:38:29 PM PDT 24
Peak memory 240576 kb
Host smart-d9004b04-1cd1-4bb8-84d4-00b609b66b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510996578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3510996578
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1169612343
Short name T653
Test name
Test status
Simulation time 7527374564 ps
CPU time 22.83 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:38:11 PM PDT 24
Peak memory 242700 kb
Host smart-c88e4ae7-f863-4909-8efa-2bffcee248ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169612343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1169612343
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.758031563
Short name T780
Test name
Test status
Simulation time 563230273 ps
CPU time 4.82 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:37:53 PM PDT 24
Peak memory 224040 kb
Host smart-3e8da264-5307-470f-b1f1-77c2ec5dd3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758031563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.758031563
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1707437636
Short name T393
Test name
Test status
Simulation time 28662343112 ps
CPU time 47.46 seconds
Started Mar 24 02:37:46 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 248760 kb
Host smart-1327adba-98d0-4fdd-8215-ab11cf42c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707437636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1707437636
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1043562359
Short name T26
Test name
Test status
Simulation time 54971542 ps
CPU time 1.03 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:37:43 PM PDT 24
Peak memory 216248 kb
Host smart-c82670c2-5244-428c-8e8e-855633fca1e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043562359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1043562359
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3176223757
Short name T736
Test name
Test status
Simulation time 1592863590 ps
CPU time 6.3 seconds
Started Mar 24 02:37:46 PM PDT 24
Finished Mar 24 02:37:53 PM PDT 24
Peak memory 217956 kb
Host smart-25763176-7456-4481-a5a8-dd3a3679298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176223757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3176223757
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3411342828
Short name T478
Test name
Test status
Simulation time 3427186436 ps
CPU time 14.38 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 234656 kb
Host smart-ed7ddae7-734a-4f92-a1cd-7fa2419b9155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411342828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3411342828
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.569355657
Short name T777
Test name
Test status
Simulation time 23057607 ps
CPU time 0.75 seconds
Started Mar 24 02:37:42 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 216048 kb
Host smart-0fe21fae-71e8-4870-9104-40a9b3a46ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569355657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.569355657
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3518255473
Short name T655
Test name
Test status
Simulation time 872489030 ps
CPU time 4.69 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 219592 kb
Host smart-7232c8ff-0b4d-4be6-8e95-8c2bbe9c1603
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3518255473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3518255473
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3743963744
Short name T66
Test name
Test status
Simulation time 115543502 ps
CPU time 1.07 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 235068 kb
Host smart-22df373b-1f31-48b3-88a3-f86ae72e5cb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743963744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3743963744
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2450740927
Short name T137
Test name
Test status
Simulation time 40119461 ps
CPU time 0.93 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:45 PM PDT 24
Peak memory 206276 kb
Host smart-7e64bc63-2b29-48e7-8d01-96dfd3f3dfba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450740927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2450740927
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1289205794
Short name T741
Test name
Test status
Simulation time 7274390680 ps
CPU time 32.92 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:38:21 PM PDT 24
Peak memory 215976 kb
Host smart-581b9537-8c5d-47ea-b2b7-28dd5e5e6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289205794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1289205794
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.128216702
Short name T387
Test name
Test status
Simulation time 5027640192 ps
CPU time 14.19 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 215992 kb
Host smart-5de48913-39db-467f-942e-8bd003434fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128216702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.128216702
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1421570654
Short name T907
Test name
Test status
Simulation time 810881147 ps
CPU time 2.16 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 216164 kb
Host smart-e83b70af-eb62-4bd6-bc1f-5ba2478675c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421570654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1421570654
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1701100989
Short name T79
Test name
Test status
Simulation time 194372376 ps
CPU time 1.05 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 206308 kb
Host smart-a52af531-816b-4a72-9cbf-5e6682f2cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701100989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1701100989
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2071645274
Short name T849
Test name
Test status
Simulation time 11298406205 ps
CPU time 19.93 seconds
Started Mar 24 02:37:46 PM PDT 24
Finished Mar 24 02:38:06 PM PDT 24
Peak memory 233420 kb
Host smart-0526ef8f-1480-4ecc-92bb-ec5b67e196f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071645274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2071645274
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.259617309
Short name T310
Test name
Test status
Simulation time 13058979 ps
CPU time 0.73 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 204844 kb
Host smart-0b8b5427-9947-410c-b0df-19e86d221412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259617309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.259617309
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1333023194
Short name T826
Test name
Test status
Simulation time 577771556 ps
CPU time 2.77 seconds
Started Mar 24 02:40:06 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 217220 kb
Host smart-061ab060-bd8c-41e7-9722-2987120735ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333023194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1333023194
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3620874047
Short name T794
Test name
Test status
Simulation time 18956006 ps
CPU time 0.81 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 205876 kb
Host smart-1da4ec19-d153-4f72-9fe9-639db140fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620874047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3620874047
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2980411133
Short name T253
Test name
Test status
Simulation time 245011896906 ps
CPU time 330.83 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:45:34 PM PDT 24
Peak memory 264768 kb
Host smart-db7db83f-de08-4310-8078-21faf223d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980411133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2980411133
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4158883279
Short name T29
Test name
Test status
Simulation time 7938983469 ps
CPU time 63.97 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:41:08 PM PDT 24
Peak memory 248916 kb
Host smart-a26cdd26-8452-48b2-9aed-201cef85858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158883279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4158883279
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.756329253
Short name T399
Test name
Test status
Simulation time 287150706117 ps
CPU time 189.31 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:43:12 PM PDT 24
Peak memory 249836 kb
Host smart-e76abc7a-608d-4405-883b-4394c7d09a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756329253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.756329253
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.592098834
Short name T977
Test name
Test status
Simulation time 1035859606 ps
CPU time 9.08 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:40:13 PM PDT 24
Peak memory 240372 kb
Host smart-fa07c9a6-c18d-47aa-9a2c-772b01f976ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592098834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.592098834
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3699379132
Short name T398
Test name
Test status
Simulation time 446747562 ps
CPU time 3.14 seconds
Started Mar 24 02:40:03 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 232680 kb
Host smart-21068fe2-3330-4243-9071-879547e8cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699379132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3699379132
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4209828364
Short name T326
Test name
Test status
Simulation time 7697300910 ps
CPU time 21.84 seconds
Started Mar 24 02:40:00 PM PDT 24
Finished Mar 24 02:40:22 PM PDT 24
Peak memory 238800 kb
Host smart-9e8e06ba-b38d-4510-8419-3814597815d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209828364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4209828364
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1906091
Short name T918
Test name
Test status
Simulation time 11605161020 ps
CPU time 9.2 seconds
Started Mar 24 02:40:03 PM PDT 24
Finished Mar 24 02:40:13 PM PDT 24
Peak memory 232328 kb
Host smart-ca421430-c47a-4389-8457-b501829df6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1906091
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3769019258
Short name T837
Test name
Test status
Simulation time 31061306340 ps
CPU time 40.44 seconds
Started Mar 24 02:40:00 PM PDT 24
Finished Mar 24 02:40:41 PM PDT 24
Peak memory 237732 kb
Host smart-00a70c2d-5e7f-4f9d-a053-3b7bcb7ddf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769019258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3769019258
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4156274965
Short name T661
Test name
Test status
Simulation time 3973722461 ps
CPU time 4.81 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:14 PM PDT 24
Peak memory 222424 kb
Host smart-616b2bea-9605-4e35-abcc-0377602ad3ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156274965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4156274965
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1687418424
Short name T241
Test name
Test status
Simulation time 114324182871 ps
CPU time 246.64 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:44:12 PM PDT 24
Peak memory 270004 kb
Host smart-f9dd1957-28ec-45b0-8276-1eb862a3e419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687418424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1687418424
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2771955135
Short name T551
Test name
Test status
Simulation time 11093043451 ps
CPU time 20.53 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 216056 kb
Host smart-042e8a8a-c5d6-43b3-9c43-d4b78788b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771955135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2771955135
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3323816850
Short name T658
Test name
Test status
Simulation time 1202275534 ps
CPU time 1.76 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 207412 kb
Host smart-6b578e9a-752f-4989-9fb2-0f14b82ccfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323816850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3323816850
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.164841842
Short name T335
Test name
Test status
Simulation time 40659224 ps
CPU time 1.3 seconds
Started Mar 24 02:40:01 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 216012 kb
Host smart-e90d13fc-c6f9-4cc5-967d-a890cbcff1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164841842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.164841842
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2224366125
Short name T419
Test name
Test status
Simulation time 17284109 ps
CPU time 0.75 seconds
Started Mar 24 02:40:02 PM PDT 24
Finished Mar 24 02:40:03 PM PDT 24
Peak memory 205304 kb
Host smart-29cef50c-3ebf-4d3e-b394-d9df50180441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224366125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2224366125
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1274020689
Short name T192
Test name
Test status
Simulation time 4799469654 ps
CPU time 7.07 seconds
Started Mar 24 02:40:03 PM PDT 24
Finished Mar 24 02:40:10 PM PDT 24
Peak memory 234380 kb
Host smart-aa78f33e-37f5-4336-a600-83800d6d513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274020689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1274020689
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.950089183
Short name T872
Test name
Test status
Simulation time 42793782 ps
CPU time 0.72 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 205136 kb
Host smart-2e48dfb5-61f4-453d-8be8-a28dd3ae1b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950089183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.950089183
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1525000658
Short name T307
Test name
Test status
Simulation time 10032877707 ps
CPU time 9.11 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:40:16 PM PDT 24
Peak memory 234812 kb
Host smart-733eba09-0ccb-47bb-9814-2ef43b7f9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525000658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1525000658
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.542544974
Short name T410
Test name
Test status
Simulation time 20371684 ps
CPU time 0.82 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 206136 kb
Host smart-0d8eb7cf-34b3-4501-9095-7939f472a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542544974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.542544974
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1668480125
Short name T556
Test name
Test status
Simulation time 80607167212 ps
CPU time 108.81 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 248732 kb
Host smart-d970f6ea-928f-42a6-8d8a-030d3b9506d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668480125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1668480125
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1251402564
Short name T493
Test name
Test status
Simulation time 750099383 ps
CPU time 13.91 seconds
Started Mar 24 02:40:06 PM PDT 24
Finished Mar 24 02:40:21 PM PDT 24
Peak memory 224144 kb
Host smart-31e0f7eb-0581-49d8-9cef-5d841f798840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251402564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1251402564
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3219551018
Short name T510
Test name
Test status
Simulation time 3988335837 ps
CPU time 9.83 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 232688 kb
Host smart-5296f05d-6617-4b23-9ef2-241e65fa4a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219551018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3219551018
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2338535470
Short name T197
Test name
Test status
Simulation time 1736087850 ps
CPU time 6.93 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 238936 kb
Host smart-b289773f-57e6-4c41-9830-1bf13c03e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338535470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2338535470
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2653055728
Short name T956
Test name
Test status
Simulation time 3947218318 ps
CPU time 10.84 seconds
Started Mar 24 02:40:04 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 234564 kb
Host smart-c6c2f483-0936-4079-9ae4-3911f85ac2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653055728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2653055728
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1453463123
Short name T539
Test name
Test status
Simulation time 5617780880 ps
CPU time 5.48 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:14 PM PDT 24
Peak memory 233196 kb
Host smart-7f1a679f-27a3-45a0-95c6-83f99c05c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453463123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1453463123
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.75946876
Short name T411
Test name
Test status
Simulation time 1551471044 ps
CPU time 6.74 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:16 PM PDT 24
Peak memory 219956 kb
Host smart-120db43e-41b9-46c8-93b8-3416a355d280
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75946876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.75946876
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4120749585
Short name T715
Test name
Test status
Simulation time 84161125105 ps
CPU time 167.24 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:42:54 PM PDT 24
Peak memory 249528 kb
Host smart-213c12c6-f618-4a4d-a202-27481dda8310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120749585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4120749585
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3380586616
Short name T368
Test name
Test status
Simulation time 3608788684 ps
CPU time 24.71 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 215984 kb
Host smart-bcfdd242-517e-48c3-b70e-67a84ed7a1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380586616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3380586616
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.38390178
Short name T891
Test name
Test status
Simulation time 8250187737 ps
CPU time 7.4 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:16 PM PDT 24
Peak memory 215972 kb
Host smart-a3ec9859-1e46-4d61-8729-9655f9eaeb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38390178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.38390178
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1311997837
Short name T603
Test name
Test status
Simulation time 32238869 ps
CPU time 1.25 seconds
Started Mar 24 02:40:10 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 207020 kb
Host smart-c2147cfb-63d2-454e-9bef-2d5a4383c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311997837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1311997837
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1586556644
Short name T856
Test name
Test status
Simulation time 14535331 ps
CPU time 0.8 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:08 PM PDT 24
Peak memory 205252 kb
Host smart-9319915d-74e4-4fa9-8da3-4b97a128a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586556644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1586556644
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1290468212
Short name T729
Test name
Test status
Simulation time 905779425 ps
CPU time 11.83 seconds
Started Mar 24 02:40:10 PM PDT 24
Finished Mar 24 02:40:22 PM PDT 24
Peak memory 232316 kb
Host smart-ca8d3e06-3bc3-4674-883f-743a0f4263ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290468212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1290468212
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2655321817
Short name T559
Test name
Test status
Simulation time 14229779 ps
CPU time 0.75 seconds
Started Mar 24 02:40:14 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 204856 kb
Host smart-f675e58e-9276-40df-a59f-835dca9578c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655321817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2655321817
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3074187231
Short name T901
Test name
Test status
Simulation time 1423060793 ps
CPU time 4.34 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:14 PM PDT 24
Peak memory 219160 kb
Host smart-9b9e1953-238d-4b5f-823b-ef24ad9111e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074187231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3074187231
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2508572237
Short name T883
Test name
Test status
Simulation time 17290566 ps
CPU time 0.77 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:40:08 PM PDT 24
Peak memory 204880 kb
Host smart-f1b3439f-61b9-46f0-acab-79c76a376655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508572237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2508572237
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2312960059
Short name T840
Test name
Test status
Simulation time 5265634713 ps
CPU time 88.24 seconds
Started Mar 24 02:40:12 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 256928 kb
Host smart-74e8f08a-6712-4dc6-95ae-2ae60c4bbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312960059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2312960059
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1471932829
Short name T766
Test name
Test status
Simulation time 11665360702 ps
CPU time 61.54 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 248888 kb
Host smart-321cca85-405b-4946-9d7f-d6e745f20624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471932829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1471932829
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.474984963
Short name T47
Test name
Test status
Simulation time 308754786009 ps
CPU time 360.15 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:46:08 PM PDT 24
Peak memory 264904 kb
Host smart-dc87d2b1-e5bd-4b16-ba93-b12fde6bf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474984963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.474984963
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.104862528
Short name T755
Test name
Test status
Simulation time 18431242455 ps
CPU time 35.09 seconds
Started Mar 24 02:40:11 PM PDT 24
Finished Mar 24 02:40:47 PM PDT 24
Peak memory 231804 kb
Host smart-6a68631b-c0ed-4811-99ca-7224dcefdf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104862528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.104862528
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4173025567
Short name T592
Test name
Test status
Simulation time 881830259 ps
CPU time 3.25 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 233360 kb
Host smart-d71523ad-391b-466a-962d-bf1301c29adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173025567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4173025567
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2828737667
Short name T516
Test name
Test status
Simulation time 7415723739 ps
CPU time 23.06 seconds
Started Mar 24 02:40:13 PM PDT 24
Finished Mar 24 02:40:36 PM PDT 24
Peak memory 224116 kb
Host smart-0de83275-0b73-4047-8859-4ad2c82a19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828737667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2828737667
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2307192201
Short name T563
Test name
Test status
Simulation time 34351989525 ps
CPU time 18.27 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 239816 kb
Host smart-34f90716-7648-473e-89bb-142cb87e752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307192201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2307192201
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4075759666
Short name T555
Test name
Test status
Simulation time 24528540967 ps
CPU time 20.83 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 218300 kb
Host smart-6a7ffb94-035a-45a3-9949-792acfef5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075759666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4075759666
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3178203605
Short name T296
Test name
Test status
Simulation time 1503033202 ps
CPU time 3.15 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 219608 kb
Host smart-d6a4eca5-88f5-4a47-a450-147e1a020525
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178203605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3178203605
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.332736531
Short name T893
Test name
Test status
Simulation time 160123909567 ps
CPU time 584.5 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:49:54 PM PDT 24
Peak memory 271668 kb
Host smart-1899967a-1a0c-4037-99df-c7ed1fbc5f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332736531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.332736531
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3440830822
Short name T945
Test name
Test status
Simulation time 2473565310 ps
CPU time 38.15 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:47 PM PDT 24
Peak memory 215980 kb
Host smart-df68faf0-d456-4e3e-a402-4f57940a6a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440830822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3440830822
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3268886123
Short name T986
Test name
Test status
Simulation time 12710135244 ps
CPU time 19.24 seconds
Started Mar 24 02:40:07 PM PDT 24
Finished Mar 24 02:40:26 PM PDT 24
Peak memory 216084 kb
Host smart-4fb39390-e239-4635-a638-a52d32353a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268886123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3268886123
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1349210134
Short name T738
Test name
Test status
Simulation time 134864543 ps
CPU time 2.55 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:10 PM PDT 24
Peak memory 216156 kb
Host smart-726ce8ca-717f-4389-a971-29b3e8f10240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349210134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1349210134
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1864330422
Short name T733
Test name
Test status
Simulation time 39235912 ps
CPU time 0.9 seconds
Started Mar 24 02:40:05 PM PDT 24
Finished Mar 24 02:40:06 PM PDT 24
Peak memory 206312 kb
Host smart-c6ee1388-ce12-466c-bdcc-f9ba6fa772f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864330422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1864330422
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1290555587
Short name T427
Test name
Test status
Simulation time 136691538 ps
CPU time 3.75 seconds
Started Mar 24 02:40:11 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 232976 kb
Host smart-159a2612-f16f-454d-a3cb-3fa02879da7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290555587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1290555587
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2144782827
Short name T892
Test name
Test status
Simulation time 33396343 ps
CPU time 0.73 seconds
Started Mar 24 02:40:14 PM PDT 24
Finished Mar 24 02:40:15 PM PDT 24
Peak memory 204296 kb
Host smart-32e6c61b-d13d-4fff-9d75-157a52193b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144782827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2144782827
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1102431626
Short name T490
Test name
Test status
Simulation time 4588325922 ps
CPU time 5.24 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 224180 kb
Host smart-2986e295-2724-438b-9a33-d206d9d737f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102431626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1102431626
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3440221295
Short name T685
Test name
Test status
Simulation time 19871453 ps
CPU time 0.81 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:09 PM PDT 24
Peak memory 206236 kb
Host smart-43926fa2-df8a-4a00-91ed-64b453d212ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440221295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3440221295
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1207345175
Short name T186
Test name
Test status
Simulation time 112616749735 ps
CPU time 199.38 seconds
Started Mar 24 02:40:15 PM PDT 24
Finished Mar 24 02:43:35 PM PDT 24
Peak memory 264652 kb
Host smart-f55a3db9-ae18-40bf-9f1e-38e7c61e279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207345175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1207345175
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2724952686
Short name T148
Test name
Test status
Simulation time 166030272735 ps
CPU time 186.24 seconds
Started Mar 24 02:40:15 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 257140 kb
Host smart-065d2a8b-d469-4445-8e88-810077fe7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724952686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2724952686
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.842960316
Short name T349
Test name
Test status
Simulation time 15038800145 ps
CPU time 109.08 seconds
Started Mar 24 02:40:14 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 233452 kb
Host smart-87f3db1f-bc9d-4781-a3de-f0e29c8941c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842960316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.842960316
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2365106980
Short name T55
Test name
Test status
Simulation time 1419316892 ps
CPU time 12.09 seconds
Started Mar 24 02:40:17 PM PDT 24
Finished Mar 24 02:40:29 PM PDT 24
Peak memory 247188 kb
Host smart-733baf20-87b4-4df7-b471-80eb9efdca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365106980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2365106980
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2616349683
Short name T370
Test name
Test status
Simulation time 1128581078 ps
CPU time 5.51 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:25 PM PDT 24
Peak memory 217944 kb
Host smart-1a16a381-4991-4aff-b90a-f87cf97515c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616349683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2616349683
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2918184579
Short name T216
Test name
Test status
Simulation time 1608400537 ps
CPU time 6.65 seconds
Started Mar 24 02:40:16 PM PDT 24
Finished Mar 24 02:40:23 PM PDT 24
Peak memory 217884 kb
Host smart-cc16ef23-f9c6-4466-a131-a5e688efe1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918184579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2918184579
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1456887541
Short name T767
Test name
Test status
Simulation time 3613653321 ps
CPU time 14.16 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:23 PM PDT 24
Peak memory 242532 kb
Host smart-dd5445a5-2d48-4c43-ab5d-9d90c5ed4fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456887541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1456887541
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4270576272
Short name T382
Test name
Test status
Simulation time 375121809 ps
CPU time 8.75 seconds
Started Mar 24 02:40:10 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 237264 kb
Host smart-38a626c1-4200-4618-b425-5176f361e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270576272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4270576272
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.933618730
Short name T311
Test name
Test status
Simulation time 2765363214 ps
CPU time 7.2 seconds
Started Mar 24 02:40:17 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 221364 kb
Host smart-74ac3fbe-0040-438e-aee4-06ba8c322c46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933618730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.933618730
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2928030896
Short name T800
Test name
Test status
Simulation time 38021766 ps
CPU time 1.01 seconds
Started Mar 24 02:40:15 PM PDT 24
Finished Mar 24 02:40:17 PM PDT 24
Peak memory 206528 kb
Host smart-080919ad-ca43-4ac0-87a1-741602f5afc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928030896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2928030896
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3186293145
Short name T501
Test name
Test status
Simulation time 4667605882 ps
CPU time 35.12 seconds
Started Mar 24 02:40:08 PM PDT 24
Finished Mar 24 02:40:44 PM PDT 24
Peak memory 215932 kb
Host smart-25e53640-4705-4842-9e36-f05fdc2f736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186293145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3186293145
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1408662061
Short name T570
Test name
Test status
Simulation time 1059852416 ps
CPU time 1.65 seconds
Started Mar 24 02:40:10 PM PDT 24
Finished Mar 24 02:40:12 PM PDT 24
Peak memory 207324 kb
Host smart-edbd0216-8797-4c0b-affc-104abf9c921a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408662061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1408662061
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2845323662
Short name T851
Test name
Test status
Simulation time 523180523 ps
CPU time 1.42 seconds
Started Mar 24 02:40:09 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 207672 kb
Host smart-4186463a-e485-4f24-a7c9-7f7cacc7856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845323662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2845323662
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1456618725
Short name T348
Test name
Test status
Simulation time 37168051 ps
CPU time 0.79 seconds
Started Mar 24 02:40:10 PM PDT 24
Finished Mar 24 02:40:11 PM PDT 24
Peak memory 205280 kb
Host smart-ba24f48d-e7a4-4253-baff-697937e39745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456618725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1456618725
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.939963708
Short name T175
Test name
Test status
Simulation time 145235574 ps
CPU time 3.14 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:22 PM PDT 24
Peak memory 217100 kb
Host smart-a593a2dd-347c-43d1-a506-d9d1c141f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939963708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.939963708
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2157054110
Short name T787
Test name
Test status
Simulation time 41425504 ps
CPU time 0.69 seconds
Started Mar 24 02:40:18 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 204844 kb
Host smart-7dc3d2dd-ec3e-4c26-8732-5d58084fa84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157054110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2157054110
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1511093965
Short name T693
Test name
Test status
Simulation time 1522005692 ps
CPU time 2.96 seconds
Started Mar 24 02:40:28 PM PDT 24
Finished Mar 24 02:40:31 PM PDT 24
Peak memory 218216 kb
Host smart-0ffed251-634d-4ef2-b375-cc28e7139082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511093965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1511093965
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1757781410
Short name T492
Test name
Test status
Simulation time 14100547 ps
CPU time 0.78 seconds
Started Mar 24 02:40:18 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 205844 kb
Host smart-5996cd98-7323-4ebb-9436-e20aeaca3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757781410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1757781410
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3267248312
Short name T238
Test name
Test status
Simulation time 9393676607 ps
CPU time 32.73 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:40:58 PM PDT 24
Peak memory 248700 kb
Host smart-c1d780e9-2f2b-4e4c-82f4-ca8188e74d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267248312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3267248312
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3457591617
Short name T820
Test name
Test status
Simulation time 230824660674 ps
CPU time 386.75 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:46:49 PM PDT 24
Peak memory 252760 kb
Host smart-05480f05-5385-4aa2-9acc-cc150d38f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457591617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3457591617
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.407326990
Short name T657
Test name
Test status
Simulation time 8573424308 ps
CPU time 49.23 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 235344 kb
Host smart-eb967063-c79f-4ac3-aee3-4b5547033ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407326990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.407326990
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.377297430
Short name T487
Test name
Test status
Simulation time 7508951687 ps
CPU time 32.36 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 240528 kb
Host smart-ed5ebbe9-5d3e-411e-879c-6a5aee22e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377297430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.377297430
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1772969796
Short name T929
Test name
Test status
Simulation time 445727471 ps
CPU time 2.3 seconds
Started Mar 24 02:40:16 PM PDT 24
Finished Mar 24 02:40:19 PM PDT 24
Peak memory 224068 kb
Host smart-5a4d5f95-f2b1-4edd-91ec-cede9a539029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772969796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1772969796
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.308302
Short name T649
Test name
Test status
Simulation time 19922737089 ps
CPU time 38.29 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:58 PM PDT 24
Peak memory 224332 kb
Host smart-25e5764c-24f4-4edd-b935-a6631807482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.308302
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3299910461
Short name T378
Test name
Test status
Simulation time 1804414693 ps
CPU time 5.72 seconds
Started Mar 24 02:40:17 PM PDT 24
Finished Mar 24 02:40:23 PM PDT 24
Peak memory 233252 kb
Host smart-be7c376e-ed7d-48ae-ad16-0a1d9130e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299910461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3299910461
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3016447148
Short name T433
Test name
Test status
Simulation time 12549223793 ps
CPU time 36.4 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 252596 kb
Host smart-eaafacb7-8565-4b2b-81d5-ecc954804b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016447148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3016447148
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1536720075
Short name T973
Test name
Test status
Simulation time 3028401571 ps
CPU time 5.28 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:40:27 PM PDT 24
Peak memory 222596 kb
Host smart-82bc7d8c-43d2-4815-8fb1-ebf89e244576
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1536720075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1536720075
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2150504963
Short name T934
Test name
Test status
Simulation time 4288276515 ps
CPU time 25.51 seconds
Started Mar 24 02:40:13 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 216032 kb
Host smart-f9bc72ad-adb0-4a30-b008-406237a0f97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150504963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2150504963
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.532610035
Short name T321
Test name
Test status
Simulation time 9488146337 ps
CPU time 29.1 seconds
Started Mar 24 02:40:13 PM PDT 24
Finished Mar 24 02:40:43 PM PDT 24
Peak memory 216084 kb
Host smart-3678f4cf-63e3-4d9f-b050-4d200e503cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532610035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.532610035
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3644228849
Short name T266
Test name
Test status
Simulation time 74797119 ps
CPU time 2.31 seconds
Started Mar 24 02:40:18 PM PDT 24
Finished Mar 24 02:40:20 PM PDT 24
Peak memory 215920 kb
Host smart-d71a0a89-3913-41fd-b692-fbb914b98d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644228849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3644228849
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2052778732
Short name T360
Test name
Test status
Simulation time 48030655 ps
CPU time 0.79 seconds
Started Mar 24 02:40:16 PM PDT 24
Finished Mar 24 02:40:17 PM PDT 24
Peak memory 205304 kb
Host smart-501646d2-f6b4-4ca6-a7be-351cce9f69b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052778732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2052778732
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1007084329
Short name T207
Test name
Test status
Simulation time 16438793864 ps
CPU time 15.02 seconds
Started Mar 24 02:40:17 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 233236 kb
Host smart-0f0696c8-47e9-4b05-a8cf-efb96c98bd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007084329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1007084329
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2763123700
Short name T950
Test name
Test status
Simulation time 70684869 ps
CPU time 0.7 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:20 PM PDT 24
Peak memory 204808 kb
Host smart-21d03909-33d2-4497-bdc2-8f68fa5f26e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763123700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2763123700
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.204445053
Short name T702
Test name
Test status
Simulation time 1568746248 ps
CPU time 3.75 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:29 PM PDT 24
Peak memory 234100 kb
Host smart-f56390d2-6cad-43bb-8e0d-8635ba6fe023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204445053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.204445053
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.214608703
Short name T316
Test name
Test status
Simulation time 15733646 ps
CPU time 0.75 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:27 PM PDT 24
Peak memory 205240 kb
Host smart-0b9af47f-b0ba-4d38-a28a-127a78fc5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214608703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.214608703
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2450999741
Short name T769
Test name
Test status
Simulation time 1970091823 ps
CPU time 20.35 seconds
Started Mar 24 02:40:24 PM PDT 24
Finished Mar 24 02:40:44 PM PDT 24
Peak memory 236128 kb
Host smart-03658169-1934-40bf-825d-8e6428bf41d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450999741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2450999741
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.397807886
Short name T798
Test name
Test status
Simulation time 2285035296 ps
CPU time 50.64 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:41:16 PM PDT 24
Peak memory 248728 kb
Host smart-b5f01185-05f2-47b9-8d2f-36e9ebb5e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397807886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.397807886
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3850530341
Short name T167
Test name
Test status
Simulation time 158150218459 ps
CPU time 591.3 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:50:12 PM PDT 24
Peak memory 281416 kb
Host smart-bd89145c-d974-4eb3-83c6-48a23e397fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850530341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3850530341
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2295158636
Short name T290
Test name
Test status
Simulation time 9137570265 ps
CPU time 42.31 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 237216 kb
Host smart-aa68ff28-4841-49c8-b5dc-3b200625e11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295158636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2295158636
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.382608251
Short name T843
Test name
Test status
Simulation time 1451557307 ps
CPU time 5.1 seconds
Started Mar 24 02:40:23 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 219476 kb
Host smart-68851d95-0409-4b87-9081-5549f8b64e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382608251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.382608251
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1588982574
Short name T821
Test name
Test status
Simulation time 688286664 ps
CPU time 9.61 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 240112 kb
Host smart-e27f94ba-b0e1-4a5e-8df8-fc8113571663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588982574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1588982574
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3934954010
Short name T946
Test name
Test status
Simulation time 32299878117 ps
CPU time 19.97 seconds
Started Mar 24 02:40:23 PM PDT 24
Finished Mar 24 02:40:44 PM PDT 24
Peak memory 236004 kb
Host smart-67915aa1-9d4c-4e89-a1f7-d89bf36d8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934954010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3934954010
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1703073542
Short name T861
Test name
Test status
Simulation time 2486765758 ps
CPU time 8.57 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:40:29 PM PDT 24
Peak memory 234552 kb
Host smart-cd49f28e-65e4-4b2f-bbb2-79d1c99d2da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703073542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1703073542
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2870777320
Short name T758
Test name
Test status
Simulation time 653654192 ps
CPU time 4.6 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 222468 kb
Host smart-f724dd82-1d84-46cb-9faa-dd7edd1367fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870777320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2870777320
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4120967837
Short name T297
Test name
Test status
Simulation time 1524272631 ps
CPU time 4.1 seconds
Started Mar 24 02:40:21 PM PDT 24
Finished Mar 24 02:40:25 PM PDT 24
Peak memory 216032 kb
Host smart-0494f4c9-9d85-4732-a8cd-a301f720b84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120967837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4120967837
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.584280434
Short name T985
Test name
Test status
Simulation time 56625173732 ps
CPU time 29.6 seconds
Started Mar 24 02:40:20 PM PDT 24
Finished Mar 24 02:40:49 PM PDT 24
Peak memory 216048 kb
Host smart-02dc6e18-7b4d-46cd-be0e-d6fad13efbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584280434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.584280434
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2399157040
Short name T858
Test name
Test status
Simulation time 93033476 ps
CPU time 2.02 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 215936 kb
Host smart-9300b752-c464-4544-9ebc-19e523a6bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399157040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2399157040
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2058371393
Short name T717
Test name
Test status
Simulation time 739845115 ps
CPU time 0.99 seconds
Started Mar 24 02:40:24 PM PDT 24
Finished Mar 24 02:40:26 PM PDT 24
Peak memory 206316 kb
Host smart-6b736100-9cbe-4a9f-bea8-43a1b418951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058371393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2058371393
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2355045936
Short name T753
Test name
Test status
Simulation time 4107851580 ps
CPU time 5.57 seconds
Started Mar 24 02:40:19 PM PDT 24
Finished Mar 24 02:40:25 PM PDT 24
Peak memory 218120 kb
Host smart-53e68bd8-64b0-4ab2-b8b9-35e6583e36d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355045936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2355045936
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.77701723
Short name T694
Test name
Test status
Simulation time 32523802 ps
CPU time 0.74 seconds
Started Mar 24 02:40:24 PM PDT 24
Finished Mar 24 02:40:24 PM PDT 24
Peak memory 204248 kb
Host smart-80fe03bc-ad71-46c1-8aa9-ee8b735254b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77701723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.77701723
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3262962447
Short name T852
Test name
Test status
Simulation time 2666746730 ps
CPU time 4.44 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:40:30 PM PDT 24
Peak memory 233400 kb
Host smart-4fd5b80e-d78d-43b2-a549-c90a4eac73ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262962447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3262962447
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1318359374
Short name T425
Test name
Test status
Simulation time 31867937 ps
CPU time 0.73 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:40:26 PM PDT 24
Peak memory 204896 kb
Host smart-7bddaef2-b1fc-4ad5-b7ac-438d7f1c54ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318359374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1318359374
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2547352374
Short name T575
Test name
Test status
Simulation time 18322942477 ps
CPU time 121.33 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 253676 kb
Host smart-d42afef9-e617-4ed0-b4db-31f94816cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547352374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2547352374
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.332753945
Short name T33
Test name
Test status
Simulation time 42506493632 ps
CPU time 299.72 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:45:22 PM PDT 24
Peak memory 249296 kb
Host smart-f8d740ab-07f5-4555-af5d-109b4b8db086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332753945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.332753945
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.431384173
Short name T327
Test name
Test status
Simulation time 43850566341 ps
CPU time 303.48 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:45:29 PM PDT 24
Peak memory 257016 kb
Host smart-7166653c-c4fc-470a-bb11-d428e6ac3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431384173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.431384173
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1917579998
Short name T688
Test name
Test status
Simulation time 21009544165 ps
CPU time 31.07 seconds
Started Mar 24 02:40:23 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 240536 kb
Host smart-33f19f2f-0d27-4da6-aafc-b45db1614b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917579998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1917579998
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2063464246
Short name T949
Test name
Test status
Simulation time 307425071 ps
CPU time 2.78 seconds
Started Mar 24 02:40:28 PM PDT 24
Finished Mar 24 02:40:31 PM PDT 24
Peak memory 224108 kb
Host smart-a3e99964-eacd-404e-82f7-b0974a6f0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063464246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2063464246
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4021803881
Short name T208
Test name
Test status
Simulation time 11824230902 ps
CPU time 45.19 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:41:07 PM PDT 24
Peak memory 248772 kb
Host smart-0bbcaa39-5efc-472b-9597-455f89e5d146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021803881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4021803881
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2011208770
Short name T921
Test name
Test status
Simulation time 1685379918 ps
CPU time 10.12 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 217376 kb
Host smart-37717445-6a7b-4b9d-ac26-32e59a24f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011208770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2011208770
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.645808692
Short name T988
Test name
Test status
Simulation time 1960911323 ps
CPU time 6.64 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:33 PM PDT 24
Peak memory 224124 kb
Host smart-e7211115-d6c5-42cd-a8a3-89880b8e0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645808692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.645808692
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.403376756
Short name T126
Test name
Test status
Simulation time 2966062078 ps
CPU time 3.45 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:29 PM PDT 24
Peak memory 219808 kb
Host smart-1b34e680-9a1c-42d2-8d23-54ee0fc72591
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=403376756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.403376756
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3997551711
Short name T245
Test name
Test status
Simulation time 17950285077 ps
CPU time 96.14 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:41:58 PM PDT 24
Peak memory 265256 kb
Host smart-2484e816-b671-4810-9b9d-a3b0a5f7d5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997551711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3997551711
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1589891232
Short name T522
Test name
Test status
Simulation time 5458034261 ps
CPU time 34.57 seconds
Started Mar 24 02:40:23 PM PDT 24
Finished Mar 24 02:40:58 PM PDT 24
Peak memory 216056 kb
Host smart-3e4f7c69-1fb9-4164-85a5-df8ef8d4be7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589891232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1589891232
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2751068780
Short name T407
Test name
Test status
Simulation time 77408379512 ps
CPU time 29.34 seconds
Started Mar 24 02:40:26 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 216076 kb
Host smart-756fa677-4a48-4686-ac14-5f1dc535e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751068780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2751068780
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3541284607
Short name T931
Test name
Test status
Simulation time 14149191 ps
CPU time 0.85 seconds
Started Mar 24 02:40:22 PM PDT 24
Finished Mar 24 02:40:23 PM PDT 24
Peak memory 205956 kb
Host smart-e9ab7c88-ce6e-43ca-a3cf-8fd7f363d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541284607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3541284607
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3908711125
Short name T287
Test name
Test status
Simulation time 95508278 ps
CPU time 0.94 seconds
Started Mar 24 02:40:21 PM PDT 24
Finished Mar 24 02:40:22 PM PDT 24
Peak memory 206316 kb
Host smart-69b16f2e-0437-460c-861e-79665b544759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908711125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3908711125
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2848680225
Short name T624
Test name
Test status
Simulation time 18190688539 ps
CPU time 11.56 seconds
Started Mar 24 02:40:24 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 233944 kb
Host smart-83d43afe-fe29-4661-bb0f-9832a9a3fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848680225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2848680225
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3401949302
Short name T937
Test name
Test status
Simulation time 36216456 ps
CPU time 0.72 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 204852 kb
Host smart-ff426cff-38f3-4bbf-ac48-b98e3e25f9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401949302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3401949302
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3109906861
Short name T340
Test name
Test status
Simulation time 837802791 ps
CPU time 5.27 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 219096 kb
Host smart-431da012-c601-45d2-a4b0-1ec4a30f7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109906861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3109906861
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1282400733
Short name T496
Test name
Test status
Simulation time 14686361 ps
CPU time 0.78 seconds
Started Mar 24 02:40:25 PM PDT 24
Finished Mar 24 02:40:26 PM PDT 24
Peak memory 206204 kb
Host smart-c0a68087-d4b6-4e43-8a6b-753201ef05ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282400733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1282400733
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1925137657
Short name T149
Test name
Test status
Simulation time 278100246452 ps
CPU time 199.48 seconds
Started Mar 24 02:40:24 PM PDT 24
Finished Mar 24 02:43:44 PM PDT 24
Peak memory 253100 kb
Host smart-0371a948-640d-4a06-a225-bc16166c5282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925137657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1925137657
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3885854284
Short name T161
Test name
Test status
Simulation time 9049122029 ps
CPU time 96.27 seconds
Started Mar 24 02:40:28 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 241380 kb
Host smart-deaf7ae2-37ec-4b00-97c2-b282416325c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885854284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3885854284
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.103830119
Short name T174
Test name
Test status
Simulation time 329962266756 ps
CPU time 204.07 seconds
Started Mar 24 02:40:29 PM PDT 24
Finished Mar 24 02:43:54 PM PDT 24
Peak memory 257064 kb
Host smart-8c033b2b-aefd-4ffb-9747-2eb395e23383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103830119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.103830119
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1975449640
Short name T678
Test name
Test status
Simulation time 7663362152 ps
CPU time 15.88 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:46 PM PDT 24
Peak memory 256948 kb
Host smart-98bceaff-83ee-4ea3-898f-48d765dbc892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975449640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1975449640
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.35804867
Short name T386
Test name
Test status
Simulation time 560038675 ps
CPU time 4.15 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:34 PM PDT 24
Peak memory 217636 kb
Host smart-c76f23de-8656-4b30-8d0c-3fb32c0639d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35804867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.35804867
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3047219409
Short name T536
Test name
Test status
Simulation time 16100147857 ps
CPU time 12.88 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 232852 kb
Host smart-7578d02f-7567-4221-98cc-2ea701bc575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047219409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3047219409
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3701163892
Short name T517
Test name
Test status
Simulation time 3665166610 ps
CPU time 12.79 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:40 PM PDT 24
Peak memory 237060 kb
Host smart-38752b7f-9bf4-4feb-ba1c-e078e8364ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701163892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3701163892
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2559942090
Short name T817
Test name
Test status
Simulation time 902074602 ps
CPU time 5.18 seconds
Started Mar 24 02:40:29 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 218540 kb
Host smart-96b27638-73a4-4d6a-b499-335e63066421
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559942090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2559942090
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.721801223
Short name T841
Test name
Test status
Simulation time 25948434518 ps
CPU time 42.7 seconds
Started Mar 24 02:40:28 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 240692 kb
Host smart-1875d35a-7b3b-4643-a014-a2ef991ca001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721801223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.721801223
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3744068559
Short name T9
Test name
Test status
Simulation time 1210569997 ps
CPU time 8.41 seconds
Started Mar 24 02:40:28 PM PDT 24
Finished Mar 24 02:40:36 PM PDT 24
Peak memory 215980 kb
Host smart-1a77aee4-64f0-47f3-9e73-1e58e84f32d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744068559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3744068559
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3500676990
Short name T622
Test name
Test status
Simulation time 7000194140 ps
CPU time 21.78 seconds
Started Mar 24 02:40:29 PM PDT 24
Finished Mar 24 02:40:51 PM PDT 24
Peak memory 216040 kb
Host smart-539d6b1e-bce4-41f9-940c-d874f0b82bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500676990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3500676990
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1348331748
Short name T598
Test name
Test status
Simulation time 252313770 ps
CPU time 3.28 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 216104 kb
Host smart-15827828-4516-427a-b671-1f3195c5205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348331748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1348331748
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2890447191
Short name T705
Test name
Test status
Simulation time 176844099 ps
CPU time 0.85 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:32 PM PDT 24
Peak memory 205304 kb
Host smart-afbe3dff-b604-4e8c-b9e3-f67640b7d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890447191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2890447191
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2441948281
Short name T796
Test name
Test status
Simulation time 10461738782 ps
CPU time 5.76 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:33 PM PDT 24
Peak memory 218128 kb
Host smart-c471227f-4723-4be4-98c9-ee3098bcc6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441948281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2441948281
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.97134413
Short name T602
Test name
Test status
Simulation time 13065217 ps
CPU time 0.74 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:31 PM PDT 24
Peak memory 204256 kb
Host smart-8ab51383-400e-45f0-ade7-a4681d245686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97134413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.97134413
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3217201239
Short name T912
Test name
Test status
Simulation time 3217264926 ps
CPU time 6.98 seconds
Started Mar 24 02:40:39 PM PDT 24
Finished Mar 24 02:40:46 PM PDT 24
Peak memory 233400 kb
Host smart-c0de31c9-460a-43ee-b381-dd0912f2ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217201239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3217201239
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.355260728
Short name T782
Test name
Test status
Simulation time 57540844 ps
CPU time 0.76 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 205116 kb
Host smart-21b33972-1522-4036-a774-f85e03069b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355260728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.355260728
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1929019121
Short name T222
Test name
Test status
Simulation time 45378086096 ps
CPU time 40.56 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 256920 kb
Host smart-d33889b6-8b92-4813-b581-9ecc5a537fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929019121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1929019121
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3817385202
Short name T236
Test name
Test status
Simulation time 66309583278 ps
CPU time 124.26 seconds
Started Mar 24 02:40:32 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 248884 kb
Host smart-6f4a9220-8c2f-4b3a-9ce2-287f236a756b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817385202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3817385202
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1505518023
Short name T541
Test name
Test status
Simulation time 2926455519 ps
CPU time 17.85 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:49 PM PDT 24
Peak memory 248984 kb
Host smart-b53cc03e-7682-436f-8ebc-01e1344a7262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505518023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1505518023
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3354239130
Short name T792
Test name
Test status
Simulation time 1507695576 ps
CPU time 6.58 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:37 PM PDT 24
Peak memory 218892 kb
Host smart-9445dd86-4652-4696-82fd-94ff3500f0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354239130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3354239130
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4103577760
Short name T960
Test name
Test status
Simulation time 2666772111 ps
CPU time 9.65 seconds
Started Mar 24 02:40:32 PM PDT 24
Finished Mar 24 02:40:42 PM PDT 24
Peak memory 229264 kb
Host smart-e37cbf5c-b984-4c2c-a169-556a60bda684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103577760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4103577760
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1348385842
Short name T314
Test name
Test status
Simulation time 14713689306 ps
CPU time 11.95 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:43 PM PDT 24
Peak memory 224156 kb
Host smart-a18cfa41-28a5-4935-9694-6238191cb0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348385842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1348385842
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3542737557
Short name T579
Test name
Test status
Simulation time 9393010862 ps
CPU time 5.01 seconds
Started Mar 24 02:40:32 PM PDT 24
Finished Mar 24 02:40:38 PM PDT 24
Peak memory 224200 kb
Host smart-adbf8c2e-2ce4-450e-9648-afe2b5736235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542737557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3542737557
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1769263833
Short name T691
Test name
Test status
Simulation time 667818813 ps
CPU time 4.61 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 218540 kb
Host smart-abd7b4e5-1f40-48d0-8d75-1e8fa02c1f48
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769263833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1769263833
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1352332493
Short name T138
Test name
Test status
Simulation time 342034758873 ps
CPU time 338.26 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:46:09 PM PDT 24
Peak memory 250656 kb
Host smart-ac4faf45-4334-4276-9ae1-38f5a5692703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352332493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1352332493
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2038629031
Short name T452
Test name
Test status
Simulation time 10616434441 ps
CPU time 49.66 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:41:17 PM PDT 24
Peak memory 216028 kb
Host smart-88da7a3e-87dd-48e1-9f1c-bcce06f52611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038629031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2038629031
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.348936603
Short name T590
Test name
Test status
Simulation time 6511641845 ps
CPU time 11.09 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:38 PM PDT 24
Peak memory 215992 kb
Host smart-47bdb0a6-bcc7-4dee-8ec2-5efd18a8c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348936603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.348936603
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.456553857
Short name T888
Test name
Test status
Simulation time 12810616 ps
CPU time 0.87 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 205284 kb
Host smart-9dbf916e-583c-40cc-ab56-33a8919aee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456553857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.456553857
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3158568204
Short name T301
Test name
Test status
Simulation time 56940355 ps
CPU time 0.94 seconds
Started Mar 24 02:40:27 PM PDT 24
Finished Mar 24 02:40:29 PM PDT 24
Peak memory 206284 kb
Host smart-86adf9cc-c187-49e5-8300-d7ca345675cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158568204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3158568204
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1261810479
Short name T813
Test name
Test status
Simulation time 4173736061 ps
CPU time 10.24 seconds
Started Mar 24 02:40:32 PM PDT 24
Finished Mar 24 02:40:43 PM PDT 24
Peak memory 234424 kb
Host smart-9683f474-bd76-4503-bd8c-1561b6a0d90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261810479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1261810479
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1527447620
Short name T981
Test name
Test status
Simulation time 13811368 ps
CPU time 0.69 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:40:34 PM PDT 24
Peak memory 204288 kb
Host smart-5a3fdb41-5e48-461a-944a-889f7c121e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527447620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1527447620
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3932038283
Short name T6
Test name
Test status
Simulation time 2752626733 ps
CPU time 4.43 seconds
Started Mar 24 02:40:35 PM PDT 24
Finished Mar 24 02:40:40 PM PDT 24
Peak memory 218808 kb
Host smart-c1dc9ac9-ac88-40bd-bc00-fb7430e6868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932038283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3932038283
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2583247331
Short name T967
Test name
Test status
Simulation time 43583725 ps
CPU time 0.76 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:31 PM PDT 24
Peak memory 204912 kb
Host smart-a7a459c6-e2ec-47f7-afc5-39e2b8e7ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583247331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2583247331
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3031333893
Short name T485
Test name
Test status
Simulation time 16239130328 ps
CPU time 33.17 seconds
Started Mar 24 02:40:36 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 237528 kb
Host smart-f090fb34-6f9b-497e-85ba-3a0c9fb81722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031333893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3031333893
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2596304839
Short name T242
Test name
Test status
Simulation time 4280078413 ps
CPU time 84.83 seconds
Started Mar 24 02:40:35 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 252532 kb
Host smart-627905f5-aad7-487b-b8cd-e4040de21d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596304839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2596304839
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2780623066
Short name T760
Test name
Test status
Simulation time 4163075829 ps
CPU time 13.76 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:40:50 PM PDT 24
Peak memory 233400 kb
Host smart-0b880275-6ba9-413a-bec7-37762933cf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780623066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2780623066
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.810917646
Short name T727
Test name
Test status
Simulation time 446089964 ps
CPU time 4.27 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:40:38 PM PDT 24
Peak memory 219608 kb
Host smart-94dac92e-5f95-4dcf-8ef3-78920a74dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810917646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.810917646
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4041881239
Short name T456
Test name
Test status
Simulation time 1181639280 ps
CPU time 5.32 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:37 PM PDT 24
Peak memory 216448 kb
Host smart-f5a0799a-0147-4182-960a-f1ec0bd6c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041881239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4041881239
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.130334151
Short name T354
Test name
Test status
Simulation time 8802935864 ps
CPU time 8.3 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 239240 kb
Host smart-bfed536c-503d-4097-a912-6e28a87ca269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130334151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.130334151
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1437964716
Short name T205
Test name
Test status
Simulation time 1603604383 ps
CPU time 9.86 seconds
Started Mar 24 02:40:30 PM PDT 24
Finished Mar 24 02:40:40 PM PDT 24
Peak memory 227052 kb
Host smart-548c71a7-1d59-461a-8ed6-7991b62a14a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437964716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1437964716
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3496119129
Short name T341
Test name
Test status
Simulation time 176847932 ps
CPU time 3.37 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:40:40 PM PDT 24
Peak memory 219608 kb
Host smart-e54fa6da-9d49-493d-8b66-ca56ffa5d750
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496119129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3496119129
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3210985981
Short name T953
Test name
Test status
Simulation time 300135477 ps
CPU time 1.11 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 207308 kb
Host smart-97027c74-d452-4c1e-9604-3a7b46d9f619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210985981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3210985981
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2783257268
Short name T342
Test name
Test status
Simulation time 15797889717 ps
CPU time 45.06 seconds
Started Mar 24 02:40:31 PM PDT 24
Finished Mar 24 02:41:16 PM PDT 24
Peak memory 216068 kb
Host smart-a7838841-b4f3-4347-83c2-925c35f3474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783257268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2783257268
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3675255480
Short name T472
Test name
Test status
Simulation time 48455927167 ps
CPU time 23.22 seconds
Started Mar 24 02:40:38 PM PDT 24
Finished Mar 24 02:41:02 PM PDT 24
Peak memory 215980 kb
Host smart-46ee0271-45a8-40fa-9166-b1807c3c52e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675255480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3675255480
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3598434763
Short name T748
Test name
Test status
Simulation time 19843268 ps
CPU time 1.14 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:40:35 PM PDT 24
Peak memory 207372 kb
Host smart-2348e424-bef0-40b2-9290-6c5469c6b46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598434763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3598434763
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.365549912
Short name T671
Test name
Test status
Simulation time 19613162 ps
CPU time 0.73 seconds
Started Mar 24 02:40:35 PM PDT 24
Finished Mar 24 02:40:36 PM PDT 24
Peak memory 205268 kb
Host smart-1e8fc5a2-e4ae-4108-a03e-8ff54fda6dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365549912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.365549912
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.938920279
Short name T864
Test name
Test status
Simulation time 469202825 ps
CPU time 7.88 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:40:45 PM PDT 24
Peak memory 222228 kb
Host smart-341b8d60-d6e7-4ae1-b222-af91b758975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938920279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.938920279
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1901927526
Short name T672
Test name
Test status
Simulation time 45034524 ps
CPU time 0.72 seconds
Started Mar 24 02:37:49 PM PDT 24
Finished Mar 24 02:37:50 PM PDT 24
Peak memory 205192 kb
Host smart-a74244c9-9686-4976-8656-1bf207139c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901927526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
901927526
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1025761290
Short name T860
Test name
Test status
Simulation time 9641913265 ps
CPU time 9.83 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:37:58 PM PDT 24
Peak memory 233064 kb
Host smart-457affea-b230-4cd8-bba4-f703c3793704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025761290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1025761290
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1423870659
Short name T361
Test name
Test status
Simulation time 43418112 ps
CPU time 0.74 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 204812 kb
Host smart-68142a6d-1625-4732-bf7b-0f8c8007a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423870659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1423870659
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4245357633
Short name T147
Test name
Test status
Simulation time 3284696521 ps
CPU time 46.69 seconds
Started Mar 24 02:37:51 PM PDT 24
Finished Mar 24 02:38:38 PM PDT 24
Peak memory 249960 kb
Host smart-dce9dd2a-e2ad-454d-ad55-52d90ed789b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245357633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4245357633
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.237851621
Short name T875
Test name
Test status
Simulation time 20173413793 ps
CPU time 46.03 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 248696 kb
Host smart-f8f73534-30dc-4882-9999-d958c4d7898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237851621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.237851621
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1440807614
Short name T853
Test name
Test status
Simulation time 11421954774 ps
CPU time 76.48 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:39:07 PM PDT 24
Peak memory 248880 kb
Host smart-69e770d9-be66-4d60-b8f0-ca901e5b9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440807614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1440807614
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1209742430
Short name T578
Test name
Test status
Simulation time 3130726933 ps
CPU time 11.05 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 235012 kb
Host smart-afe4367a-3f81-440d-a407-27d8e001dd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209742430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1209742430
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3756393857
Short name T894
Test name
Test status
Simulation time 5660017549 ps
CPU time 6.87 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 234712 kb
Host smart-0d8ea33b-1332-4261-8484-c3c1c6b0c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756393857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3756393857
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.529644798
Short name T178
Test name
Test status
Simulation time 4272447598 ps
CPU time 19.03 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:38:07 PM PDT 24
Peak memory 248092 kb
Host smart-fbc45654-1688-4e1a-9b87-f19afb63e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529644798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.529644798
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2530969475
Short name T484
Test name
Test status
Simulation time 16383002 ps
CPU time 1.05 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 216256 kb
Host smart-5872a287-6669-4d88-bbcc-3a8bb64a4d76
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530969475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2530969475
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1129996721
Short name T834
Test name
Test status
Simulation time 2326368429 ps
CPU time 8.04 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:52 PM PDT 24
Peak memory 229276 kb
Host smart-c5f70507-adde-4860-84ff-eb1ccbdaa0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129996721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1129996721
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.782612266
Short name T811
Test name
Test status
Simulation time 31860587976 ps
CPU time 22.49 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:38:11 PM PDT 24
Peak memory 233492 kb
Host smart-97fbaba1-54ba-4196-a320-2b21806be86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782612266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.782612266
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.784941545
Short name T63
Test name
Test status
Simulation time 21243493 ps
CPU time 0.74 seconds
Started Mar 24 02:37:45 PM PDT 24
Finished Mar 24 02:37:46 PM PDT 24
Peak memory 215844 kb
Host smart-632b5a56-df00-4051-951c-ea6dfe0543c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784941545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.784941545
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2198283046
Short name T460
Test name
Test status
Simulation time 475782445 ps
CPU time 4.49 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:37:54 PM PDT 24
Peak memory 221860 kb
Host smart-91e767b9-dc0d-4fda-89f1-5ba4fc8f625e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198283046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2198283046
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.214988889
Short name T254
Test name
Test status
Simulation time 123461342560 ps
CPU time 287.31 seconds
Started Mar 24 02:37:49 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 289744 kb
Host smart-8358a523-e536-4eec-adb5-2c7cb06c3eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214988889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.214988889
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1852295405
Short name T765
Test name
Test status
Simulation time 35573638507 ps
CPU time 48.87 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:38:37 PM PDT 24
Peak memory 216004 kb
Host smart-29c329cb-3f73-40bf-9fe4-76b5b549d1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852295405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1852295405
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3449528679
Short name T543
Test name
Test status
Simulation time 6573656696 ps
CPU time 9.4 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:37:57 PM PDT 24
Peak memory 215984 kb
Host smart-e428ee2d-91e0-4b7a-a098-a6d492812c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449528679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3449528679
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2079189676
Short name T972
Test name
Test status
Simulation time 46187520 ps
CPU time 2.23 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 216120 kb
Host smart-a7ee709d-2f80-44f6-9a7d-6244a331ef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079189676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2079189676
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1238759435
Short name T585
Test name
Test status
Simulation time 29459710 ps
CPU time 0.72 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 205304 kb
Host smart-06c8315b-4e41-43ab-80fa-3851900d30be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238759435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1238759435
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.316532795
Short name T428
Test name
Test status
Simulation time 6988908099 ps
CPU time 6.79 seconds
Started Mar 24 02:37:44 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 232292 kb
Host smart-2c7f4e00-0964-44f1-b4de-a1f0796715bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316532795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.316532795
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3813090322
Short name T58
Test name
Test status
Simulation time 68159584 ps
CPU time 0.71 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 205160 kb
Host smart-26a4e999-3b60-4ea7-8388-be5790911d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813090322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
813090322
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.247732334
Short name T338
Test name
Test status
Simulation time 392839794 ps
CPU time 3.22 seconds
Started Mar 24 02:37:49 PM PDT 24
Finished Mar 24 02:37:53 PM PDT 24
Peak memory 232920 kb
Host smart-eec1fb14-f18c-4b6f-9e79-6e9c6fb4ee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247732334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.247732334
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.263260072
Short name T274
Test name
Test status
Simulation time 13033603 ps
CPU time 0.75 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 204908 kb
Host smart-ae711454-6fce-4e52-baf5-3b880ccab92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263260072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.263260072
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.581630870
Short name T689
Test name
Test status
Simulation time 13462367763 ps
CPU time 43.83 seconds
Started Mar 24 02:37:51 PM PDT 24
Finished Mar 24 02:38:35 PM PDT 24
Peak memory 248748 kb
Host smart-321d43a4-050c-4f69-afe8-fdcaaae6648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581630870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.581630870
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2985361640
Short name T572
Test name
Test status
Simulation time 228966990604 ps
CPU time 384.47 seconds
Started Mar 24 02:37:51 PM PDT 24
Finished Mar 24 02:44:16 PM PDT 24
Peak memory 266124 kb
Host smart-9463bb8a-1c2c-43ba-bca6-6f80f09e8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985361640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2985361640
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3106512147
Short name T183
Test name
Test status
Simulation time 4619594779 ps
CPU time 20.91 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:38:09 PM PDT 24
Peak memory 234640 kb
Host smart-6b2fbb89-2db3-4918-b1e0-a1cf3b4cb461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106512147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3106512147
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.832972143
Short name T122
Test name
Test status
Simulation time 703380145 ps
CPU time 8.85 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 239484 kb
Host smart-86dbe8aa-f58d-421c-a9f1-6cfc391aa32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832972143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.832972143
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2096377867
Short name T159
Test name
Test status
Simulation time 21633216750 ps
CPU time 14.88 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:38:05 PM PDT 24
Peak memory 216412 kb
Host smart-6cf73660-fefb-4aa4-844b-aa7d8ca6f45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096377867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2096377867
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2686912316
Short name T201
Test name
Test status
Simulation time 19032960871 ps
CPU time 18.65 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 229468 kb
Host smart-720fdbb1-e327-4037-923f-a7fbbbb24280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686912316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2686912316
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3016660730
Short name T667
Test name
Test status
Simulation time 44794683 ps
CPU time 1 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 216248 kb
Host smart-177ce986-eabc-4dac-b52e-8931ab1486dd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016660730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3016660730
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2637666268
Short name T476
Test name
Test status
Simulation time 15830058851 ps
CPU time 14.76 seconds
Started Mar 24 02:37:47 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 233220 kb
Host smart-e6e6f2c9-410a-4ea1-9938-45698b05d286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637666268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2637666268
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.947098855
Short name T583
Test name
Test status
Simulation time 213461737 ps
CPU time 4.18 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:58 PM PDT 24
Peak memory 233024 kb
Host smart-1bcd78a1-b8d2-4459-bb35-a2f0a5215451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947098855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.947098855
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2168628607
Short name T65
Test name
Test status
Simulation time 30807990 ps
CPU time 0.77 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 215584 kb
Host smart-c9f1d915-016c-40b4-b7ef-4b63503ffd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168628607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2168628607
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2869181482
Short name T775
Test name
Test status
Simulation time 14144957052 ps
CPU time 5.82 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:38:00 PM PDT 24
Peak memory 222456 kb
Host smart-f242173d-edaa-4a7e-bb88-25bae87f2104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2869181482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2869181482
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4018297520
Short name T135
Test name
Test status
Simulation time 32782877427 ps
CPU time 38.64 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 254780 kb
Host smart-0ad7462f-f2ca-4d4c-ac28-1f45fd8c3d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018297520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4018297520
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1585059194
Short name T470
Test name
Test status
Simulation time 6479321153 ps
CPU time 45.96 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:38:34 PM PDT 24
Peak memory 215960 kb
Host smart-bcd61819-4325-4e03-8ee4-ad04d19f01f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585059194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1585059194
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3672424457
Short name T845
Test name
Test status
Simulation time 5532337620 ps
CPU time 7.6 seconds
Started Mar 24 02:37:49 PM PDT 24
Finished Mar 24 02:37:57 PM PDT 24
Peak memory 216128 kb
Host smart-deec4733-1b02-42e6-8082-9eba835ba466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672424457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3672424457
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1962032862
Short name T315
Test name
Test status
Simulation time 163622640 ps
CPU time 2.84 seconds
Started Mar 24 02:37:48 PM PDT 24
Finished Mar 24 02:37:51 PM PDT 24
Peak memory 216028 kb
Host smart-a959a4f6-63bd-4327-9ed5-aceb5b36d5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962032862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1962032862
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3724213512
Short name T679
Test name
Test status
Simulation time 320456097 ps
CPU time 0.91 seconds
Started Mar 24 02:37:51 PM PDT 24
Finished Mar 24 02:37:52 PM PDT 24
Peak memory 205300 kb
Host smart-07233503-caf1-40e2-812f-4eda00e1a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724213512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3724213512
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1005866594
Short name T828
Test name
Test status
Simulation time 3460454706 ps
CPU time 14.35 seconds
Started Mar 24 02:37:50 PM PDT 24
Finished Mar 24 02:38:05 PM PDT 24
Peak memory 239136 kb
Host smart-f1291570-c897-439f-88db-fd1a0fb7e09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005866594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1005866594
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1737828399
Short name T518
Test name
Test status
Simulation time 116650928 ps
CPU time 0.7 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 204864 kb
Host smart-5097a572-6bf8-4911-95ac-85b90d369a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737828399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
737828399
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1466408614
Short name T409
Test name
Test status
Simulation time 2219990943 ps
CPU time 7.87 seconds
Started Mar 24 02:37:57 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 224108 kb
Host smart-7c6b1e3b-a1a8-42aa-a5cc-8b9e20e065f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466408614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1466408614
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.204616207
Short name T783
Test name
Test status
Simulation time 46630567 ps
CPU time 0.76 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 204900 kb
Host smart-57bf1409-4751-40cf-a456-3d503026ddfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204616207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.204616207
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3810207576
Short name T806
Test name
Test status
Simulation time 6582516509 ps
CPU time 23.52 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 239808 kb
Host smart-e8b7148b-b0a6-464b-bb75-d0c432e144cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810207576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3810207576
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3565404114
Short name T838
Test name
Test status
Simulation time 2627890310 ps
CPU time 17.57 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:18 PM PDT 24
Peak memory 240372 kb
Host smart-7e92215e-ee49-4705-bc0b-6cd4c8e7cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565404114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3565404114
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3714987172
Short name T232
Test name
Test status
Simulation time 50936760851 ps
CPU time 204.19 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 256988 kb
Host smart-4e01cd41-b8ec-4be4-ba5d-b55931ab9485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714987172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3714987172
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2990397849
Short name T989
Test name
Test status
Simulation time 4633317016 ps
CPU time 27.91 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:38:22 PM PDT 24
Peak memory 247996 kb
Host smart-85d6fe70-5ef0-484d-bb43-a95261ecc592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990397849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2990397849
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.764343974
Short name T631
Test name
Test status
Simulation time 484656778 ps
CPU time 3.48 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:58 PM PDT 24
Peak memory 224020 kb
Host smart-954edb7d-319a-45ce-9059-c991e6f0633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764343974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.764343974
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.972670573
Short name T191
Test name
Test status
Simulation time 120264855213 ps
CPU time 49.35 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:38:44 PM PDT 24
Peak memory 251548 kb
Host smart-496ea3c1-37ee-4f2c-ae9e-afe6b31d7429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972670573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.972670573
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1385304783
Short name T352
Test name
Test status
Simulation time 49192593 ps
CPU time 0.96 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 217448 kb
Host smart-8577711f-c3fb-4c73-a513-e428f6142a86
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385304783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1385304783
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1225240204
Short name T877
Test name
Test status
Simulation time 11350747212 ps
CPU time 32.74 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:38:27 PM PDT 24
Peak memory 237096 kb
Host smart-1b337e1f-89cb-42b6-992b-6df9afede1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225240204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1225240204
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.336814493
Short name T171
Test name
Test status
Simulation time 353674915 ps
CPU time 3.76 seconds
Started Mar 24 02:37:55 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 232660 kb
Host smart-a6d976a5-fa1f-4723-adbb-23f80f5a6c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336814493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.336814493
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.162273678
Short name T366
Test name
Test status
Simulation time 30409879 ps
CPU time 0.7 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 216128 kb
Host smart-e892bb3b-a57a-47c0-82fd-c6806eae5a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162273678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.162273678
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3311329313
Short name T513
Test name
Test status
Simulation time 190078921 ps
CPU time 3.31 seconds
Started Mar 24 02:37:56 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 218532 kb
Host smart-a82d5c4c-ef2b-4b57-b247-689a8abc9111
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3311329313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3311329313
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3088340487
Short name T480
Test name
Test status
Simulation time 39575404 ps
CPU time 0.93 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 204988 kb
Host smart-90bcf83e-3e4e-4040-ad96-0e2e7be7dcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088340487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3088340487
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3075762126
Short name T291
Test name
Test status
Simulation time 9218675252 ps
CPU time 13.62 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 216024 kb
Host smart-dbc2ad2b-39d2-4482-a9a1-4d9c892bdc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075762126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3075762126
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2294740114
Short name T788
Test name
Test status
Simulation time 1050459993 ps
CPU time 4.19 seconds
Started Mar 24 02:37:58 PM PDT 24
Finished Mar 24 02:38:05 PM PDT 24
Peak memory 215944 kb
Host smart-4fcf59f7-49fe-4eff-89be-2f616ba3fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294740114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2294740114
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.912776215
Short name T20
Test name
Test status
Simulation time 43113114 ps
CPU time 0.91 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 206372 kb
Host smart-27d7e4da-a8cc-4435-a213-c0ac9dfa9841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912776215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.912776215
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2677430644
Short name T440
Test name
Test status
Simulation time 61226268 ps
CPU time 0.72 seconds
Started Mar 24 02:37:55 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 205308 kb
Host smart-bc346ccb-15c2-483e-b7a0-946f4afc16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677430644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2677430644
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1513948834
Short name T902
Test name
Test status
Simulation time 5014097853 ps
CPU time 18.39 seconds
Started Mar 24 02:37:52 PM PDT 24
Finished Mar 24 02:38:11 PM PDT 24
Peak memory 234012 kb
Host smart-6ec51ba8-e3cc-43c4-9e4f-e1a7abeb60c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513948834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1513948834
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2804526759
Short name T876
Test name
Test status
Simulation time 40959548 ps
CPU time 0.77 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 205132 kb
Host smart-3c0bd979-5eaf-45ab-8882-5cb9f7834e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804526759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
804526759
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2582442087
Short name T708
Test name
Test status
Simulation time 42336629 ps
CPU time 2.71 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:04 PM PDT 24
Peak memory 233904 kb
Host smart-1bd4b4fa-d96a-4c26-903c-3ffbf96384bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582442087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2582442087
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.930171354
Short name T305
Test name
Test status
Simulation time 38324356 ps
CPU time 0.83 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 205920 kb
Host smart-1749ed54-be31-44fc-92b2-337a466a8d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930171354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.930171354
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1075014998
Short name T246
Test name
Test status
Simulation time 20218929407 ps
CPU time 44.13 seconds
Started Mar 24 02:38:02 PM PDT 24
Finished Mar 24 02:38:47 PM PDT 24
Peak memory 252200 kb
Host smart-1fe60cd8-bad8-4e5b-b282-105fc27e04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075014998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1075014998
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.450563370
Short name T371
Test name
Test status
Simulation time 34125838173 ps
CPU time 94.25 seconds
Started Mar 24 02:37:57 PM PDT 24
Finished Mar 24 02:39:35 PM PDT 24
Peak memory 240112 kb
Host smart-2b03e306-479e-4cc5-8af6-2aecb5731b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450563370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.450563370
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3012246447
Short name T46
Test name
Test status
Simulation time 211196129916 ps
CPU time 370.02 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:44:10 PM PDT 24
Peak memory 257012 kb
Host smart-9103b0a6-9ed8-4af9-8b7f-564475a3ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012246447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3012246447
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2756727695
Short name T124
Test name
Test status
Simulation time 12446491772 ps
CPU time 14.12 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:19 PM PDT 24
Peak memory 232232 kb
Host smart-6009e1a1-e39f-4974-8dda-21137441337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756727695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2756727695
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.81859057
Short name T81
Test name
Test status
Simulation time 21675242391 ps
CPU time 7.88 seconds
Started Mar 24 02:37:57 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 236880 kb
Host smart-b0a6257b-9bce-4844-a704-15a1b8bdef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81859057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.81859057
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2138001884
Short name T396
Test name
Test status
Simulation time 4366407546 ps
CPU time 5.88 seconds
Started Mar 24 02:38:02 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 224052 kb
Host smart-dc45e090-8b90-46d9-9913-02f1fa465ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138001884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2138001884
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1673254841
Short name T647
Test name
Test status
Simulation time 27398580 ps
CPU time 0.99 seconds
Started Mar 24 02:37:53 PM PDT 24
Finished Mar 24 02:37:55 PM PDT 24
Peak memory 216236 kb
Host smart-482d0d77-cd55-4784-a6ae-1cddc6fea71d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673254841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1673254841
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1286487325
Short name T80
Test name
Test status
Simulation time 37588310139 ps
CPU time 32.8 seconds
Started Mar 24 02:37:58 PM PDT 24
Finished Mar 24 02:38:33 PM PDT 24
Peak memory 232340 kb
Host smart-29cc2126-4d70-4e37-9a6b-a1ad8237f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286487325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1286487325
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4241021079
Short name T889
Test name
Test status
Simulation time 8994322817 ps
CPU time 5.38 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:38:06 PM PDT 24
Peak memory 233076 kb
Host smart-a372abd0-eb71-41da-b0cf-d53236165c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241021079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4241021079
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2959084554
Short name T500
Test name
Test status
Simulation time 18978497 ps
CPU time 0.74 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:56 PM PDT 24
Peak memory 215844 kb
Host smart-7326741b-7e24-4af1-b689-2e0e8be9e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959084554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2959084554
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3413370224
Short name T576
Test name
Test status
Simulation time 2053586558 ps
CPU time 5.42 seconds
Started Mar 24 02:38:01 PM PDT 24
Finished Mar 24 02:38:07 PM PDT 24
Peak memory 218228 kb
Host smart-90fbe1aa-803a-4420-9ca7-5a581437fee8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3413370224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3413370224
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1497555348
Short name T850
Test name
Test status
Simulation time 650696196 ps
CPU time 1 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 206100 kb
Host smart-55b29f68-6635-4f0a-8e1b-9d7d66f2a7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497555348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1497555348
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3474498865
Short name T28
Test name
Test status
Simulation time 31372431308 ps
CPU time 45.56 seconds
Started Mar 24 02:37:57 PM PDT 24
Finished Mar 24 02:38:46 PM PDT 24
Peak memory 215964 kb
Host smart-3bff1950-4ad6-4ecb-8af1-cb3f01bbca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474498865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3474498865
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2284428520
Short name T275
Test name
Test status
Simulation time 2013015116 ps
CPU time 4.05 seconds
Started Mar 24 02:37:54 PM PDT 24
Finished Mar 24 02:37:59 PM PDT 24
Peak memory 215904 kb
Host smart-26cf7285-1e42-4f5a-a5dc-861b638f6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284428520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2284428520
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.499404863
Short name T285
Test name
Test status
Simulation time 69542452 ps
CPU time 1.35 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 215760 kb
Host smart-3181e1ae-4afb-4e96-8c3f-57595dbc5388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499404863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.499404863
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1170603328
Short name T424
Test name
Test status
Simulation time 540016873 ps
CPU time 0.88 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 205284 kb
Host smart-1d8801dd-4830-4328-978c-eceb2240d9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170603328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1170603328
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2454438428
Short name T188
Test name
Test status
Simulation time 1776668525 ps
CPU time 6.41 seconds
Started Mar 24 02:37:58 PM PDT 24
Finished Mar 24 02:38:07 PM PDT 24
Peak memory 236596 kb
Host smart-72863795-e439-44e6-a824-3a102edf80a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454438428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2454438428
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4174561074
Short name T881
Test name
Test status
Simulation time 21873634 ps
CPU time 0.73 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:07 PM PDT 24
Peak memory 204484 kb
Host smart-69ea6346-db6d-4061-b1e3-4881003fee18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174561074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
174561074
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2810418066
Short name T209
Test name
Test status
Simulation time 289830508 ps
CPU time 2.12 seconds
Started Mar 24 02:38:01 PM PDT 24
Finished Mar 24 02:38:03 PM PDT 24
Peak memory 218064 kb
Host smart-03ac508e-9768-45a2-9710-51f8cc0d3116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810418066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2810418066
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1684220023
Short name T897
Test name
Test status
Simulation time 22280130 ps
CPU time 0.81 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 205956 kb
Host smart-36327484-da77-4dc0-90ca-ac257be1918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684220023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1684220023
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3534908964
Short name T250
Test name
Test status
Simulation time 2506639366 ps
CPU time 33.04 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 237108 kb
Host smart-c12f1a2e-3986-4dbe-a6bb-91850f335b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534908964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3534908964
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1280540683
Short name T5
Test name
Test status
Simulation time 54450211628 ps
CPU time 409.69 seconds
Started Mar 24 02:38:17 PM PDT 24
Finished Mar 24 02:45:07 PM PDT 24
Peak memory 263600 kb
Host smart-599ec927-974e-4255-af40-4941acf28ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280540683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1280540683
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.962734078
Short name T262
Test name
Test status
Simulation time 2681018236 ps
CPU time 55.49 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 249352 kb
Host smart-e03c0c9a-9258-4ba9-84fa-d3cb51bacd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962734078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
962734078
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3094142686
Short name T684
Test name
Test status
Simulation time 666672683 ps
CPU time 9.35 seconds
Started Mar 24 02:38:06 PM PDT 24
Finished Mar 24 02:38:15 PM PDT 24
Peak memory 235736 kb
Host smart-a6e12d1d-ac18-4ff8-9ab0-39b7280931e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094142686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3094142686
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.213810912
Short name T511
Test name
Test status
Simulation time 694773140 ps
CPU time 2.97 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 217836 kb
Host smart-eb83221b-ac0c-49ff-9bfe-43f727e3cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213810912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.213810912
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1016631127
Short name T190
Test name
Test status
Simulation time 51607993604 ps
CPU time 38.58 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:40 PM PDT 24
Peak memory 235036 kb
Host smart-d579779e-75c2-4e6a-86a6-b582493388f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016631127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1016631127
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4077476338
Short name T519
Test name
Test status
Simulation time 25541161 ps
CPU time 1.14 seconds
Started Mar 24 02:38:01 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 216228 kb
Host smart-e3fc8f2e-6102-4642-ae32-42757dc71ca8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077476338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4077476338
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2150480480
Short name T215
Test name
Test status
Simulation time 4360157122 ps
CPU time 5.59 seconds
Started Mar 24 02:38:02 PM PDT 24
Finished Mar 24 02:38:08 PM PDT 24
Peak memory 233276 kb
Host smart-d6023a20-15f0-4172-999f-4b9fa9a285b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150480480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2150480480
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1638958794
Short name T696
Test name
Test status
Simulation time 31161373457 ps
CPU time 20.62 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:26 PM PDT 24
Peak memory 219944 kb
Host smart-9b936503-4b83-4384-9dda-b9ad17eaff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638958794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1638958794
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1508208823
Short name T764
Test name
Test status
Simulation time 17172148 ps
CPU time 0.75 seconds
Started Mar 24 02:38:01 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 215692 kb
Host smart-2e1dedad-485a-4746-934a-e825f2262587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508208823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1508208823
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.272243843
Short name T606
Test name
Test status
Simulation time 928233436 ps
CPU time 4.11 seconds
Started Mar 24 02:38:07 PM PDT 24
Finished Mar 24 02:38:11 PM PDT 24
Peak memory 222348 kb
Host smart-b72e6de8-b1f4-40cd-968f-791fdafd1d52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=272243843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.272243843
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1151914646
Short name T265
Test name
Test status
Simulation time 278560588 ps
CPU time 5.18 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:38:06 PM PDT 24
Peak memory 217480 kb
Host smart-68536661-88dc-4796-b787-34738fd7337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151914646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1151914646
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3243294636
Short name T431
Test name
Test status
Simulation time 23744556789 ps
CPU time 30.06 seconds
Started Mar 24 02:37:58 PM PDT 24
Finished Mar 24 02:38:30 PM PDT 24
Peak memory 216360 kb
Host smart-4b93051e-1342-4112-ae20-fd7b6fcc4af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243294636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3243294636
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4162929571
Short name T345
Test name
Test status
Simulation time 35374913 ps
CPU time 1.13 seconds
Started Mar 24 02:38:00 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 207528 kb
Host smart-33353193-eb08-4346-842c-239e3abdcf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162929571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4162929571
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2974807060
Short name T965
Test name
Test status
Simulation time 232849282 ps
CPU time 0.88 seconds
Started Mar 24 02:37:59 PM PDT 24
Finished Mar 24 02:38:01 PM PDT 24
Peak memory 205212 kb
Host smart-9acce26c-b208-4480-bb8b-29d9a9db58a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974807060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2974807060
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3289697013
Short name T422
Test name
Test status
Simulation time 2619823642 ps
CPU time 11.08 seconds
Started Mar 24 02:38:04 PM PDT 24
Finished Mar 24 02:38:16 PM PDT 24
Peak memory 233932 kb
Host smart-2582033a-cd90-4686-8075-7c4737aa1983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289697013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3289697013
Directory /workspace/9.spi_device_upload/latest
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