Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6576704	1			T1	15943		T2	1652		T3	1
all_values[1]	6576704	1			T1	15943		T2	1652		T3	1
all_values[2]	6576704	1			T1	15943		T2	1652		T3	1
all_values[3]	6576704	1			T1	15943		T2	1652		T3	1
all_values[4]	6576704	1			T1	15943		T2	1652		T3	1
all_values[5]	6576704	1			T1	15943		T2	1652		T3	1
all_values[6]	6576704	1			T1	15943		T2	1652		T3	1
all_values[7]	6576704	1			T1	15943		T2	1652		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50065346

1

T1

127544

T2

13216

T3

8

auto[1]

2548286

1

T4

53216

T30

33

T32

97

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52541364

1

T1

126843

T2

13216

T3

8

auto[1]

72268

1

T1

701

T4

520

T8

409

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6225790	1			T1	15477		T2	1652		T3	1
all_values[0]	auto[0]	auto[1]	40552	1			T1	466		T4	154		T8	256
all_values[0]	auto[1]	auto[0]	309390	1			T4	26479		T30	5		T32	6
all_values[0]	auto[1]	auto[1]	972	1			T4	104		T30	2		T32	10
all_values[1]	auto[0]	auto[0]	6057151	1			T1	15733		T2	1652		T3	1
all_values[1]	auto[0]	auto[1]	19817	1			T1	210		T4	152		T8	116
all_values[1]	auto[1]	auto[0]	498730	1			T4	2		T30	2		T32	7
all_values[1]	auto[1]	auto[1]	1006	1			T4	4		T30	2		T32	5
all_values[2]	auto[0]	auto[0]	6091458	1			T1	15918		T2	1652		T3	1
all_values[2]	auto[0]	auto[1]	7060	1			T1	25		T4	65		T8	37
all_values[2]	auto[1]	auto[0]	477593	1			T4	8		T30	3		T32	10
all_values[2]	auto[1]	auto[1]	593	1			T4	3		T32	3		T55	4
all_values[3]	auto[0]	auto[0]	6332653	1			T1	15943		T2	1652		T3	1
all_values[3]	auto[0]	auto[1]	221	1			T4	6		T119	1		T30	2
all_values[3]	auto[1]	auto[0]	243599	1			T4	4		T30	2		T32	1
all_values[3]	auto[1]	auto[1]	231	1			T4	1		T30	1		T32	6
all_values[4]	auto[0]	auto[0]	6115161	1			T1	15943		T2	1652		T3	1
all_values[4]	auto[0]	auto[1]	212	1			T4	2		T30	2		T32	4
all_values[4]	auto[1]	auto[0]	461134	1			T4	6		T30	2		T32	7
all_values[4]	auto[1]	auto[1]	197	1			T4	2		T30	2		T32	4
all_values[5]	auto[0]	auto[0]	6541814	1			T1	15943		T2	1652		T3	1
all_values[5]	auto[0]	auto[1]	368	1			T4	5		T158	5		T159	3
all_values[5]	auto[1]	auto[0]	34335	1			T4	26581		T30	3		T32	5
all_values[5]	auto[1]	auto[1]	187	1			T4	1		T30	1		T32	2
all_values[6]	auto[0]	auto[0]	6316864	1			T1	15943		T2	1652		T3	1
all_values[6]	auto[0]	auto[1]	217	1			T4	4		T30	3		T32	5
all_values[6]	auto[1]	auto[0]	259395	1			T4	10		T30	4		T32	5
all_values[6]	auto[1]	auto[1]	228	1			T4	4		T32	10		T55	3
all_values[7]	auto[0]	auto[0]	6315820	1			T1	15943		T2	1652		T3	1
all_values[7]	auto[0]	auto[1]	188	1			T4	8		T30	1		T32	2
all_values[7]	auto[1]	auto[0]	260477	1			T4	2		T30	4		T32	12
all_values[7]	auto[1]	auto[1]	219	1			T4	5		T32	4		T55	2