Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	39160	1			T1	300		T4	416		T5	6
auto[SpiFlashAddrCfg]	8705	1			T1	58		T4	119		T5	2
auto[SpiFlashAddr3b]	10589	1			T1	73		T4	95		T5	6
auto[SpiFlashAddr4b]	8815	1			T1	72		T4	83		T5	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38938

1

T1

317

T4

388

T5

16

auto[1]

28331

1

T1

186

T4

325

T8

277

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35987

1

T1

205

T4

362

T5

10

auto[1]

31282

1

T1

298

T4

351

T5

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44395	1			T1	353		T4	453		T5	6
values[1]	1163	1			T1	8		T4	15		T8	10
values[2]	1760	1			T1	19		T4	23		T8	10
values[3]	1789	1			T1	12		T4	29		T8	12
values[4]	1676	1			T1	11		T4	17		T8	14
values[5]	1719	1			T1	12		T4	16		T5	2
values[6]	1794	1			T1	8		T4	20		T8	10
values[7]	1671	1			T1	9		T4	21		T8	9
values[8]	11302	1			T1	71		T4	119		T5	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30094

1

T4

713

T5

16

T7

4

auto[1]

37175

1

T1

503

T14

9

T36

369

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

64820

1

T1

484

T4

686

T5

16

write

2449

1

T1

19

T4

27

T8

24

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

22845

1

T1

176

T4

231

T5

6

valids[0x1]

44424

1

T1

327

T4

482

T5

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1817	1			T1	10		T4	20		T5	2
internal_process_ops[0x5a]	1855	1			T1	11		T4	14		T5	4
internal_process_ops[0x05]	22738	1			T1	158		T4	252		T5	2
internal_process_ops[0x35]	1893	1			T1	16		T4	10		T5	2
internal_process_ops[0x15]	1894	1			T1	9		T4	21		T7	2
internal_process_ops[0x03]	1288	1			T1	7		T4	20		T8	7
internal_process_ops[0x0b]	1199	1			T1	6		T4	22		T8	8
internal_process_ops[0x3b]	1236	1			T1	5		T4	22		T8	12
internal_process_ops[0x6b]	1331	1			T1	4		T4	15		T8	10
internal_process_ops[0xbb]	1253	1			T1	8		T4	15		T8	8
internal_process_ops[0xeb]	1307	1			T1	3		T4	23		T8	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66071

1

T1

489

T4

697

T5

16

auto[1]

1198

1

T1

14

T4

16

T8

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65019

1

T1

477

T4

696

T5

16

auto[1]

2250

1

T1

26

T4

17

T8

24

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10416

1

T4

251

T5

6

T7

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5651

1

T4

161

T8

205

T11

88

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2235

1

T4

38

T5

2

T8

32

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1913

1

T4

73

T8

23

T11

30

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2625

1

T4

50

T5

6

T8

28

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2152

1

T4

43

T8

17

T11

29

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2222

1

T4

33

T5

2

T8

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1894

1

T4

37

T8

23

T11

26

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

84

1

T8

4

T25

1

T40

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

46

1

T4

4

T11

1

T13

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

45

1

T8

2

T11

1

T152

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

74

1

T26

1

T28

3

T29

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T4

3

T8

2

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T4

2

T8

4

T28

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

50

1

T4

3

T11

1

T13

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T8

1

T13

1

T28

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

51

1

T13

4

T25

2

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

60

1

T8

2

T11

1

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T11

2

T40

1

T26

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

50

1

T4

2

T8

1

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T8

2

T11

1

T12

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

56

1

T4

7

T8

1

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

52

1

T4

5

T8

2

T11

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

69

1

T4

1

T8

3

T13

8

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

13155

1

T1

199

T36

91

T37

101

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

9317

1

T1

95

T36

104

T37

237

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2096

1

T1

40

T36

24

T37

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1850

1

T1

13

T36

17

T37

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2788

1

T1

29

T14

9

T36

32

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2464

1

T1

37

T36

30

T37

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2130

1

T1

41

T36

23

T37

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1912

1

T1

30

T36

27

T37

13

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T36

3

T112

1

T153

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T1

2

T36

1

T112

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T36

2

T37

1

T111

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

87

1

T1

4

T30

1

T113

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

83

1

T1

4

T36

2

T112

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

99

1

T36

1

T111

1

T112

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T1

1

T36

1

T37

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

72

1

T154

1

T30

6

T155

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

68

1

T36

2

T156

1

T113

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T1

1

T111

1

T157

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

86

1

T36

2

T37

3

T112

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T1

6

T156

3

T30

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T36

1

T37

3

T111

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T1

1

T37

4

T153

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

105

1

T36

5

T157

1

T112

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T36

1

T111

1

T156

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4244	1			T4	81		T8	58		T9	22
auto[0]	values[0]	valids[0x1]	14389	1			T4	372		T5	6		T7	4
auto[0]	values[1]	valids[0x1]	534	1			T4	15		T8	10		T11	11
auto[0]	values[2]	valids[0x0]	564	1			T4	17		T8	9		T11	9
auto[0]	values[2]	valids[0x1]	287	1			T4	6		T8	1		T11	4
auto[0]	values[3]	valids[0x0]	576	1			T4	16		T8	6		T11	12
auto[0]	values[3]	valids[0x1]	315	1			T4	13		T8	6		T11	3
auto[0]	values[4]	valids[0x0]	566	1			T4	11		T8	14		T11	3
auto[0]	values[4]	valids[0x1]	302	1			T4	6		T11	4		T13	5
auto[0]	values[5]	valids[0x0]	588	1			T4	8		T5	2		T8	12
auto[0]	values[5]	valids[0x1]	283	1			T4	8		T11	4		T13	8
auto[0]	values[6]	valids[0x0]	654	1			T4	14		T8	4		T11	9
auto[0]	values[6]	valids[0x1]	312	1			T4	6		T8	6		T11	10
auto[0]	values[7]	valids[0x0]	532	1			T4	14		T8	5		T11	8
auto[0]	values[7]	valids[0x1]	347	1			T4	7		T8	4		T11	4
auto[0]	values[8]	valids[0x0]	3383	1			T4	70		T5	4		T8	27
auto[0]	values[8]	valids[0x1]	2218	1			T4	49		T5	4		T8	31
auto[1]	values[0]	valids[0x0]	5348	1			T1	97		T36	61		T37	26
auto[1]	values[0]	valids[0x1]	20414	1			T1	256		T36	169		T37	346
auto[1]	values[1]	valids[0x1]	629	1			T1	8		T14	2		T36	8
auto[1]	values[2]	valids[0x0]	553	1			T1	7		T36	5		T111	3
auto[1]	values[2]	valids[0x1]	356	1			T1	12		T36	4		T37	4
auto[1]	values[3]	valids[0x0]	548	1			T1	5		T36	5		T37	1
auto[1]	values[3]	valids[0x1]	350	1			T1	7		T36	1		T111	1
auto[1]	values[4]	valids[0x0]	468	1			T1	7		T36	5		T37	1
auto[1]	values[4]	valids[0x1]	340	1			T1	4		T36	6		T37	1
auto[1]	values[5]	valids[0x0]	504	1			T1	6		T36	9		T37	1
auto[1]	values[5]	valids[0x1]	344	1			T1	6		T37	1		T112	2
auto[1]	values[6]	valids[0x0]	496	1			T1	5		T36	5		T37	2
auto[1]	values[6]	valids[0x1]	332	1			T1	3		T36	5		T112	2
auto[1]	values[7]	valids[0x0]	450	1			T1	5		T36	5		T37	1
auto[1]	values[7]	valids[0x1]	342	1			T1	4		T36	4		T37	4
auto[1]	values[8]	valids[0x0]	3371	1			T1	44		T14	7		T36	52
auto[1]	values[8]	valids[0x1]	2330	1			T1	27		T36	25		T37	6