Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18839

1

T1

138

T4

171

T5

5

auto[1]

22831

1

T1

169

T4

249

T8

204

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15613

1

T1

124

T4

137

T5

1

auto[1]

26057

1

T1

183

T4

283

T5

4

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7113	1			T1	36		T4	61		T5	5
auto[524288:1048575]	4914	1			T1	3		T4	128		T7	1
auto[1048576:1572863]	4667	1			T1	110		T4	6		T7	3
auto[1572864:2097151]	5514	1			T1	65		T4	14		T8	38
auto[2097152:2621439]	5044	1			T1	33		T4	33		T7	2
auto[2621440:3145727]	5076	1			T1	6		T4	66		T7	2
auto[3145728:3670015]	4320	1			T1	27		T4	86		T8	31
auto[3670016:4194303]	5022	1			T1	27		T4	26		T8	50

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40826

1

T1

305

T4

406

T5

5

auto[1]

844

1

T1

2

T4

14

T8

26

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33423

1

T1

231

T4

377

T5

5

auto[1]

8247

1

T1

76

T4

43

T8

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1828	1			T1	13		T4	13		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	804	1			T1	8		T4	6		T5	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1278	1			T1	1		T4	14		T7	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	520	1			T4	5		T8	2		T11	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1321	1			T1	18		T4	2		T7	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	470	1			T1	4		T4	3		T8	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1278	1			T1	15		T4	10		T8	11
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	515	1			T1	8		T4	2		T8	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1393	1			T1	6		T4	18		T7	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	503	1			T1	3		T4	8		T8	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1317	1			T1	3		T4	10		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	508	1			T1	3		T4	3		T8	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1172	1			T1	13		T4	20		T8	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	475	1			T1	4		T4	9		T8	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1327	1			T1	5		T4	10		T8	12
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	511	1			T1	3		T4	4		T8	5
auto[0]	auto[1]	auto[0:524287]	auto[0]	342	1			T4	3		T11	3		T25	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	168	1			T25	1		T36	3		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	279	1			T1	1		T4	1		T11	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	142	1			T1	1		T4	1		T11	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	274	1			T1	8		T4	1		T40	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	143	1			T1	2		T40	3		T26	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	322	1			T1	5		T4	2		T8	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	141	1			T1	1		T11	1		T25	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	307	1			T1	4		T4	3		T11	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	157	1			T1	2		T4	4		T11	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	309	1			T4	2		T11	7		T13	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	132	1			T11	2		T25	1		T36	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	295	1			T4	6		T8	1		T11	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	148	1			T4	4		T8	1		T11	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	320	1			T1	6		T4	5		T11	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	140	1			T1	1		T4	2		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	287	1			T1	3		T4	1		T8	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2873	1			T1	12		T4	38		T8	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	214	1			T4	7		T8	4		T40	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1794	1			T4	100		T8	41		T40	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	226	1			T1	6		T8	2		T11	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1862	1			T1	70		T8	16		T11	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	221	1			T1	4		T8	1		T11	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2413	1			T1	6		T8	19		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	230	1			T1	3		T8	2		T11	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2076	1			T1	7		T8	10		T11	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	231	1			T4	2		T8	7		T13	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2006	1			T4	49		T8	42		T13	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	191	1			T1	2		T4	4		T8	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1357	1			T1	8		T4	39		T8	23
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	204	1			T1	1		T8	5		T40	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2018	1			T1	2		T8	28		T40	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	68	1			T11	1		T36	1		T152	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	743	1			T11	15		T36	1		T152	39
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	55	1			T11	1		T13	1		T153	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	632	1			T11	21		T13	2		T153	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	48	1			T1	1		T40	2		T153	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	323	1			T1	1		T40	9		T153	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	56	1			T1	2		T40	1		T112	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	568	1			T1	24		T40	3		T112	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	50	1			T1	2		T40	1		T36	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	328	1			T1	6		T40	2		T36	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T11	2		T36	1		T29	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	525	1			T11	52		T36	2		T29	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	65	1			T4	1		T28	1		T153	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	617	1			T4	3		T28	44		T153	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	57	1			T1	2		T4	2		T11	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	445	1			T1	7		T4	3		T11	45

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	14838	1			T1	106		T4	128		T5	5
auto[0]	auto[0]	auto[1]	382	1			T1	1		T4	9		T8	11
auto[0]	auto[1]	auto[0]	3556	1			T1	31		T4	34		T8	3
auto[0]	auto[1]	auto[1]	63	1			T11	4		T69	2		T147	1
auto[1]	auto[0]	auto[0]	17873	1			T1	123		T4	235		T8	189
auto[1]	auto[0]	auto[1]	330	1			T1	1		T4	5		T8	15
auto[1]	auto[1]	auto[0]	4559	1			T1	45		T4	9		T11	136
auto[1]	auto[1]	auto[1]	69	1			T11	2		T28	1		T152	1