Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18020

1

T4

388

T5

16

T7

4

auto[1]

12074

1

T4

325

T8

277

T11

178

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3256	1			T4	176		T8	61		T11	20
values[1]	4083	1			T4	28		T8	30		T9	22
values[2]	3901	1			T4	235		T7	4		T8	48
values[3]	3579	1			T4	44		T8	103		T11	186
values[4]	4045	1			T4	150		T8	56		T11	80
values[5]	4442	1			T4	60		T5	16		T8	42
values[6]	3398	1			T8	105		T11	34		T13	43
values[7]	3390	1			T4	20		T8	20		T11	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3544	1			T4	217		T8	136		T13	63
values[1]	3500	1			T4	20		T7	4		T8	72
values[2]	4203	1			T4	95		T5	16		T8	30
values[3]	3527	1			T4	72		T8	125		T11	61
values[4]	3653	1			T4	20		T8	20		T9	22
values[5]	3852	1			T4	103		T8	33		T11	223
values[6]	3675	1			T4	107		T11	20		T25	20
values[7]	4140	1			T4	79		T8	49		T11	113

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	335	1			T4	73		T29	17		T31	15
auto[0]	values[0]	values[1]	154	1			T4	5		T29	10		T192	30
auto[0]	values[0]	values[2]	283	1			T4	12		T13	8		T39	26
auto[0]	values[0]	values[3]	273	1			T8	9		T25	14		T40	13
auto[0]	values[0]	values[4]	136	1			T66	20		T69	8		T198	9
auto[0]	values[0]	values[5]	227	1			T11	9		T63	24		T36	10
auto[0]	values[0]	values[6]	366	1			T40	11		T211	2		T115	13
auto[0]	values[0]	values[7]	221	1			T4	13		T13	13		T25	9
auto[0]	values[1]	values[0]	293	1			T13	12		T26	12		T210	32
auto[0]	values[1]	values[1]	388	1			T8	14		T198	13		T187	12
auto[0]	values[1]	values[2]	213	1			T36	14		T152	7		T198	22
auto[0]	values[1]	values[3]	346	1			T4	11		T11	33		T13	18
auto[0]	values[1]	values[4]	211	1			T9	22		T13	14		T64	6
auto[0]	values[1]	values[5]	187	1			T114	14		T178	12		T173	12
auto[0]	values[1]	values[6]	286	1			T28	51		T69	12		T115	13
auto[0]	values[1]	values[7]	317	1			T11	41		T13	27		T65	20
auto[0]	values[2]	values[0]	310	1			T4	66		T8	9		T28	31
auto[0]	values[2]	values[1]	204	1			T7	4		T30	13		T206	20
auto[0]	values[2]	values[2]	349	1			T4	43		T11	11		T127	24
auto[0]	values[2]	values[3]	265	1			T114	15		T194	11		T201	13
auto[0]	values[2]	values[4]	360	1			T40	13		T29	13		T69	23
auto[0]	values[2]	values[5]	373	1			T4	11		T78	2		T208	8
auto[0]	values[2]	values[6]	287	1			T4	10		T25	15		T68	12
auto[0]	values[2]	values[7]	278	1			T13	30		T25	18		T36	13
auto[0]	values[3]	values[0]	359	1			T25	13		T33	12		T176	10
auto[0]	values[3]	values[1]	235	1			T11	14		T40	17		T212	16
auto[0]	values[3]	values[2]	268	1			T8	14		T26	13		T28	12
auto[0]	values[3]	values[3]	270	1			T4	7		T11	13		T69	6
auto[0]	values[3]	values[4]	371	1			T8	13		T11	19		T28	16
auto[0]	values[3]	values[5]	345	1			T4	7		T8	14		T11	97
auto[0]	values[3]	values[6]	296	1			T125	14		T29	20		T213	6
auto[0]	values[3]	values[7]	169	1			T8	11		T69	12		T187	13
auto[0]	values[4]	values[0]	128	1			T4	8		T8	12		T43	18
auto[0]	values[4]	values[1]	258	1			T26	28		T171	9		T214	18
auto[0]	values[4]	values[2]	567	1			T4	16		T26	13		T27	11
auto[0]	values[4]	values[3]	172	1			T40	8		T28	11		T193	24
auto[0]	values[4]	values[4]	237	1			T4	7		T25	30		T28	9
auto[0]	values[4]	values[5]	372	1			T4	14		T11	74		T38	16
auto[0]	values[4]	values[6]	401	1			T4	28		T40	17		T33	11
auto[0]	values[4]	values[7]	257	1			T4	11		T197	22		T28	8
auto[0]	values[5]	values[0]	321	1			T4	11		T40	31		T31	12
auto[0]	values[5]	values[1]	418	1			T8	15		T13	13		T40	14
auto[0]	values[5]	values[2]	553	1			T5	16		T40	9		T177	18
auto[0]	values[5]	values[3]	338	1			T4	10		T28	64		T29	15
auto[0]	values[5]	values[4]	199	1			T28	13		T115	8		T215	22
auto[0]	values[5]	values[5]	301	1			T171	56		T198	39		T216	13
auto[0]	values[5]	values[6]	187	1			T4	13		T28	14		T190	6
auto[0]	values[5]	values[7]	404	1			T40	15		T28	58		T209	32
auto[0]	values[6]	values[0]	248	1			T8	12		T13	23		T27	9
auto[0]	values[6]	values[1]	247	1			T191	20		T33	13		T69	63
auto[0]	values[6]	values[2]	306	1			T25	9		T26	9		T36	19
auto[0]	values[6]	values[3]	168	1			T8	31		T171	7		T29	27
auto[0]	values[6]	values[4]	265	1			T11	23		T29	11		T30	7
auto[0]	values[6]	values[5]	233	1			T28	11		T217	26		T216	12
auto[0]	values[6]	values[6]	146	1			T44	10		T200	12		T201	6
auto[0]	values[6]	values[7]	385	1			T8	19		T40	12		T28	128
auto[0]	values[7]	values[0]	149	1			T180	22		T33	12		T183	26
auto[0]	values[7]	values[1]	279	1			T45	22		T32	25		T115	12
auto[0]	values[7]	values[2]	158	1			T218	2		T29	7		T31	36
auto[0]	values[7]	values[3]	195	1			T8	15		T167	22		T114	16
auto[0]	values[7]	values[4]	252	1			T219	24		T152	14		T171	8
auto[0]	values[7]	values[5]	314	1			T11	13		T171	11		T29	16
auto[0]	values[7]	values[6]	276	1			T4	12		T11	9		T195	16
auto[0]	values[7]	values[7]	311	1			T12	22		T28	8		T29	12
auto[1]	values[0]	values[0]	74	1			T4	7		T29	7		T31	5
auto[1]	values[0]	values[1]	130	1			T4	15		T29	10		T201	9
auto[1]	values[0]	values[2]	230	1			T4	8		T13	16		T220	32
auto[1]	values[0]	values[3]	149	1			T8	52		T25	6		T40	7
auto[1]	values[0]	values[4]	65	1			T69	12		T198	11		T179	9
auto[1]	values[0]	values[5]	149	1			T11	11		T36	13		T198	37
auto[1]	values[0]	values[6]	230	1			T40	13		T115	7		T201	12
auto[1]	values[0]	values[7]	234	1			T4	43		T13	7		T25	11
auto[1]	values[1]	values[0]	247	1			T13	8		T26	9		T116	8
auto[1]	values[1]	values[1]	288	1			T8	16		T198	7		T187	8
auto[1]	values[1]	values[2]	200	1			T36	6		T152	62		T198	18
auto[1]	values[1]	values[3]	277	1			T4	17		T11	8		T13	6
auto[1]	values[1]	values[4]	130	1			T13	7		T194	6		T200	10
auto[1]	values[1]	values[5]	267	1			T114	21		T173	76		T188	9
auto[1]	values[1]	values[6]	186	1			T28	25		T69	12		T115	7
auto[1]	values[1]	values[7]	247	1			T11	72		T13	17		T36	6
auto[1]	values[2]	values[0]	193	1			T4	31		T8	39		T28	8
auto[1]	values[2]	values[1]	85	1			T30	7		T114	11		T187	8
auto[1]	values[2]	values[2]	186	1			T4	12		T11	9		T28	8
auto[1]	values[2]	values[3]	170	1			T114	8		T194	9		T201	7
auto[1]	values[2]	values[4]	261	1			T40	10		T29	7		T69	9
auto[1]	values[2]	values[5]	200	1			T4	52		T114	7		T115	19
auto[1]	values[2]	values[6]	124	1			T4	10		T25	5		T31	13
auto[1]	values[2]	values[7]	256	1			T13	10		T25	2		T36	7
auto[1]	values[3]	values[0]	140	1			T25	11		T33	14		T176	10
auto[1]	values[3]	values[1]	118	1			T11	6		T40	8		T30	23
auto[1]	values[3]	values[2]	117	1			T8	16		T26	7		T28	8
auto[1]	values[3]	values[3]	211	1			T4	17		T11	7		T69	19
auto[1]	values[3]	values[4]	214	1			T8	7		T11	24		T28	4
auto[1]	values[3]	values[5]	184	1			T4	13		T8	19		T11	6
auto[1]	values[3]	values[6]	167	1			T29	7		T175	18		T189	18
auto[1]	values[3]	values[7]	115	1			T8	9		T69	9		T187	8
auto[1]	values[4]	values[0]	212	1			T4	12		T8	44		T200	9
auto[1]	values[4]	values[1]	160	1			T26	6		T171	11		T198	8
auto[1]	values[4]	values[2]	274	1			T4	4		T26	7		T27	9
auto[1]	values[4]	values[3]	166	1			T40	13		T28	54		T33	16
auto[1]	values[4]	values[4]	228	1			T4	13		T25	14		T28	64
auto[1]	values[4]	values[5]	241	1			T4	6		T11	6		T27	39
auto[1]	values[4]	values[6]	224	1			T4	19		T40	3		T33	10
auto[1]	values[4]	values[7]	148	1			T4	12		T28	12		T29	8
auto[1]	values[5]	values[0]	220	1			T4	9		T40	19		T31	8
auto[1]	values[5]	values[1]	255	1			T8	27		T13	10		T40	6
auto[1]	values[5]	values[2]	114	1			T40	13		T221	10		T222	16
auto[1]	values[5]	values[3]	220	1			T4	10		T28	8		T29	5
auto[1]	values[5]	values[4]	321	1			T28	7		T115	12		T194	17
auto[1]	values[5]	values[5]	182	1			T171	5		T198	7		T216	12
auto[1]	values[5]	values[6]	173	1			T4	7		T28	6		T31	51
auto[1]	values[5]	values[7]	236	1			T40	13		T28	6		T29	5
auto[1]	values[6]	values[0]	223	1			T8	20		T13	20		T27	11
auto[1]	values[6]	values[1]	140	1			T33	7		T69	52		T114	7
auto[1]	values[6]	values[2]	176	1			T25	11		T26	13		T36	5
auto[1]	values[6]	values[3]	230	1			T8	13		T171	13		T29	4
auto[1]	values[6]	values[4]	137	1			T11	11		T29	17		T30	13
auto[1]	values[6]	values[5]	143	1			T28	9		T216	8		T114	12
auto[1]	values[6]	values[6]	126	1			T200	8		T201	14		T179	26
auto[1]	values[6]	values[7]	225	1			T8	10		T40	16		T28	7
auto[1]	values[7]	values[0]	92	1			T33	8		T179	7		T140	18
auto[1]	values[7]	values[1]	141	1			T32	19		T115	9		T223	8
auto[1]	values[7]	values[2]	209	1			T29	13		T31	7		T114	11
auto[1]	values[7]	values[3]	77	1			T8	5		T114	4		T186	9
auto[1]	values[7]	values[4]	266	1			T152	87		T171	12		T69	9
auto[1]	values[7]	values[5]	134	1			T11	7		T171	9		T29	14
auto[1]	values[7]	values[6]	200	1			T4	8		T11	11		T69	14
auto[1]	values[7]	values[7]	337	1			T28	16		T29	8		T32	7