Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	455	1			T4	5		T8	1		T11	2
auto[ReadAddrCrossIntoMailbox]	296	1			T4	8		T8	2		T11	4
auto[ReadAddrCrossOutOfMailbox]	296	1			T4	7		T8	5		T11	4
auto[ReadAddrCrossAllMailbox]	220	1			T4	6		T8	4		T11	4
auto[ReadAddrOutsideMailbox]	3795	1			T4	91		T8	44		T11	47

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2509

1

T4

46

T8

26

T11

31

auto[1]

2553

1

T4

71

T8

30

T11

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	839	1			T4	20		T8	7		T11	11
read_ops[0x0b]	822	1			T4	22		T8	8		T11	9
read_ops[0x3b]	805	1			T4	22		T8	12		T11	13
read_ops[0x6b]	916	1			T4	15		T8	10		T11	10
read_ops[0xbb]	837	1			T4	15		T8	8		T11	5
read_ops[0xeb]	843	1			T4	23		T8	11		T11	13

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T11	1		T127	2		T33	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T13	1		T127	2		T33	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T11	1		T25	1		T171	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T4	2		T13	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T4	1		T8	1		T11	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T4	1		T40	2		T26	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T4	1		T28	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T40	1		T30	1		T224	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T4	4		T8	2		T11	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T4	11		T8	4		T11	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T40	1		T127	1		T26	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T4	2		T127	1		T29	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T28	2		T33	1		T69	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T28	1		T33	1		T225	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T11	2		T13	2		T28	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T4	1		T8	1		T27	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T11	1		T26	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T4	1		T32	1		T69	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T4	6		T8	4		T11	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T4	12		T8	3		T11	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T13	1		T36	2		T28	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T4	2		T28	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T4	1		T40	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T4	2		T8	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T13	1		T28	1		T201	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T4	2		T40	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T11	1		T40	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T28	1		T29	1		T30	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T4	8		T8	2		T11	8
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T4	7		T8	9		T11	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T40	1		T127	1		T28	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T13	1		T25	1		T127	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T8	1		T13	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T4	1		T11	1		T69	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T8	2		T125	3		T28	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T11	1		T25	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T8	2		T40	1		T125	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T11	2		T25	1		T125	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	335	1			T4	10		T8	3		T11	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	352	1			T4	4		T8	2		T11	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T127	3		T177	2		T198	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T13	1		T127	3		T28	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T13	1		T40	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T11	2		T13	1		T27	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T4	1		T27	1		T28	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T13	2		T28	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	29	1			T4	1		T8	1		T13	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T4	1		T13	1		T40	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T4	4		T8	4		T11	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T4	8		T8	3		T11	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T8	1		T11	1		T177	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T4	1		T13	2		T40	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T4	1		T25	1		T28	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T4	1		T198	2		T114	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T4	1		T8	1		T171	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T13	1		T28	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T4	1		T125	2		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T4	1		T8	1		T40	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T4	6		T8	2		T11	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T4	11		T8	6		T11	6