Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[1]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[2]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[3]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[4]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[5]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[6]	6576704	1			T1	15943		T2	1652		T3	1
all_pins[7]	6576704	1			T1	15943		T2	1652		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52351052	1			T1	127544		T2	13216		T3	8
values[0x1]	262580	1			T4	956		T30	8		T32	44
transitions[0x0=>0x1]	260847	1			T4	952		T30	8		T32	32
transitions[0x1=>0x0]	260857	1			T4	952		T30	8		T32	32

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6575675	1			T1	15943		T2	1652		T3	1
all_pins[0]	values[0x1]	1029	1			T4	108		T30	2		T32	10
all_pins[0]	transitions[0x0=>0x1]	669	1			T4	108		T30	2		T32	5
all_pins[0]	transitions[0x1=>0x0]	690	1			T4	4		T30	2		T55	4
all_pins[1]	values[0x0]	6575654	1			T1	15943		T2	1652		T3	1
all_pins[1]	values[0x1]	1050	1			T4	4		T30	2		T32	5
all_pins[1]	transitions[0x0=>0x1]	620	1			T4	4		T30	2		T32	5
all_pins[1]	transitions[0x1=>0x0]	177	1			T4	3		T32	3		T55	4
all_pins[2]	values[0x0]	6576097	1			T1	15943		T2	1652		T3	1
all_pins[2]	values[0x1]	607	1			T4	3		T32	3		T55	4
all_pins[2]	transitions[0x0=>0x1]	560	1			T4	3		T32	2		T55	4
all_pins[2]	transitions[0x1=>0x0]	184	1			T4	1		T30	1		T32	5
all_pins[3]	values[0x0]	6576473	1			T1	15943		T2	1652		T3	1
all_pins[3]	values[0x1]	231	1			T4	1		T30	1		T32	6
all_pins[3]	transitions[0x0=>0x1]	181	1			T30	1		T32	4		T55	2
all_pins[3]	transitions[0x1=>0x0]	147	1			T4	1		T30	2		T32	2
all_pins[4]	values[0x0]	6576507	1			T1	15943		T2	1652		T3	1
all_pins[4]	values[0x1]	197	1			T4	2		T30	2		T32	4
all_pins[4]	transitions[0x0=>0x1]	153	1			T4	2		T30	2		T32	4
all_pins[4]	transitions[0x1=>0x0]	1622	1			T4	829		T30	1		T32	2
all_pins[5]	values[0x0]	6575038	1			T1	15943		T2	1652		T3	1
all_pins[5]	values[0x1]	1666	1			T4	829		T30	1		T32	2
all_pins[5]	transitions[0x0=>0x1]	962	1			T4	829		T30	1		T55	2
all_pins[5]	transitions[0x1=>0x0]	256877	1			T4	4		T32	8		T55	3
all_pins[6]	values[0x0]	6319123	1			T1	15943		T2	1652		T3	1
all_pins[6]	values[0x1]	257581	1			T4	4		T32	10		T55	3
all_pins[6]	transitions[0x0=>0x1]	257529	1			T4	2		T32	9		T55	2
all_pins[6]	transitions[0x1=>0x0]	167	1			T4	3		T32	3		T55	1
all_pins[7]	values[0x0]	6576485	1			T1	15943		T2	1652		T3	1
all_pins[7]	values[0x1]	219	1			T4	5		T32	4		T55	2
all_pins[7]	transitions[0x0=>0x1]	173	1			T4	4		T32	3		T55	2
all_pins[7]	transitions[0x1=>0x0]	993	1			T4	107		T30	2		T32	9