Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3962	1			T4	40		T8	113		T11	157
values[1]	2739	1			T5	16		T8	124		T25	20
values[2]	3233	1			T4	40		T11	58		T13	45
values[3]	4286	1			T4	147		T8	59		T11	100
values[4]	4178	1			T4	103		T8	33		T9	22
values[5]	3569	1			T4	103		T11	61		T25	20
values[6]	4140	1			T4	103		T7	4		T8	50
values[7]	3987	1			T4	177		T8	86		T11	78

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3810	1			T4	68		T11	80		T39	26
values[1]	4418	1			T4	24		T11	34		T13	63
values[2]	3044	1			T4	118		T5	16		T8	52
values[3]	3974	1			T4	123		T8	86		T11	40
values[4]	3718	1			T4	120		T8	115		T11	204
values[5]	3571	1			T4	87		T8	33		T11	55
values[6]	4303	1			T4	40		T7	4		T8	78
values[7]	3256	1			T4	133		T8	101		T9	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29618

1

T4

697

T5

16

T7

4

auto[1]

476

1

T4

16

T8

12

T11

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	418	1			T4	19		T125	14		T206	20
auto[0]	values[0]	values[1]	546	1			T11	34		T25	20		T152	101
auto[0]	values[0]	values[2]	500	1			T8	32		T27	18		T171	20
auto[0]	values[0]	values[3]	589	1			T4	17		T8	17		T11	20
auto[0]	values[0]	values[4]	476	1			T11	103		T30	20		T187	20
auto[0]	values[0]	values[5]	461	1			T127	24		T114	23		T226	38
auto[0]	values[0]	values[6]	530	1			T12	22		T13	22		T25	20
auto[0]	values[0]	values[7]	369	1			T8	59		T13	20		T30	25
auto[0]	values[1]	values[0]	487	1			T40	28		T195	16		T69	42
auto[0]	values[1]	values[1]	312	1			T25	20		T28	87		T227	12
auto[0]	values[1]	values[2]	418	1			T5	16		T36	20		T171	20
auto[0]	values[1]	values[3]	292	1			T28	18		T29	20		T114	33
auto[0]	values[1]	values[4]	301	1			T8	56		T27	20		T78	2
auto[0]	values[1]	values[5]	304	1			T28	23		T171	61		T29	26
auto[0]	values[1]	values[6]	230	1			T8	48		T29	29		T31	43
auto[0]	values[1]	values[7]	355	1			T8	16		T26	19		T152	20
auto[0]	values[2]	values[0]	359	1			T36	47		T29	24		T198	20
auto[0]	values[2]	values[1]	389	1			T171	20		T45	22		T186	20
auto[0]	values[2]	values[2]	287	1			T13	21		T26	34		T181	16
auto[0]	values[2]	values[3]	412	1			T4	40		T115	66		T186	20
auto[0]	values[2]	values[4]	381	1			T11	23		T212	16		T219	24
auto[0]	values[2]	values[5]	439	1			T11	35		T13	22		T40	20
auto[0]	values[2]	values[6]	663	1			T29	20		T30	23		T69	20
auto[0]	values[2]	values[7]	265	1			T63	24		T29	20		T228	2
auto[0]	values[3]	values[0]	375	1			T11	80		T28	63		T29	64
auto[0]	values[3]	values[1]	788	1			T4	24		T13	20		T40	23
auto[0]	values[3]	values[2]	493	1			T25	40		T30	20		T217	26
auto[0]	values[3]	values[3]	603	1			T4	21		T209	32		T152	68
auto[0]	values[3]	values[4]	530	1			T4	78		T8	57		T25	24
auto[0]	values[3]	values[5]	426	1			T4	20		T218	2		T229	2
auto[0]	values[3]	values[6]	582	1			T11	20		T40	24		T28	40
auto[0]	values[3]	values[7]	425	1			T180	22		T115	43		T186	20
auto[0]	values[4]	values[0]	590	1			T4	28		T27	49		T230	6
auto[0]	values[4]	values[1]	691	1			T40	26		T28	103		T194	31
auto[0]	values[4]	values[2]	377	1			T4	55		T26	20		T36	20
auto[0]	values[4]	values[3]	313	1			T11	20		T29	17		T44	10
auto[0]	values[4]	values[4]	479	1			T29	20		T31	59		T231	108
auto[0]	values[4]	values[5]	488	1			T8	33		T25	24		T28	72
auto[0]	values[4]	values[6]	733	1			T4	20		T114	20		T175	25
auto[0]	values[4]	values[7]	436	1			T9	22		T13	23		T40	25
auto[0]	values[5]	values[0]	499	1			T28	20		T29	20		T30	26
auto[0]	values[5]	values[1]	536	1			T198	64		T115	19		T194	24
auto[0]	values[5]	values[2]	244	1			T28	20		T232	2		T223	8
auto[0]	values[5]	values[3]	686	1			T4	20		T25	20		T208	8
auto[0]	values[5]	values[4]	332	1			T40	24		T29	20		T69	64
auto[0]	values[5]	values[5]	375	1			T4	26		T198	20		T179	47
auto[0]	values[5]	values[6]	401	1			T11	60		T26	20		T171	18
auto[0]	values[5]	values[7]	440	1			T4	56		T40	20		T233	18
auto[0]	values[6]	values[0]	561	1			T33	19		T69	24		T198	20
auto[0]	values[6]	values[1]	602	1			T40	21		T28	31		T200	22
auto[0]	values[6]	values[2]	394	1			T4	62		T13	19		T69	21
auto[0]	values[6]	values[3]	582	1			T28	92		T30	22		T193	24
auto[0]	values[6]	values[4]	582	1			T64	6		T234	66		T115	20
auto[0]	values[6]	values[5]	469	1			T4	20		T11	20		T65	20
auto[0]	values[6]	values[6]	570	1			T7	4		T8	29		T11	19
auto[0]	values[6]	values[7]	305	1			T4	19		T8	20		T11	20
auto[0]	values[7]	values[0]	462	1			T4	20		T39	26		T30	29
auto[0]	values[7]	values[1]	487	1			T13	40		T66	20		T30	20
auto[0]	values[7]	values[2]	284	1			T8	20		T40	28		T29	19
auto[0]	values[7]	values[3]	426	1			T4	20		T8	66		T175	20
auto[0]	values[7]	values[4]	584	1			T4	39		T11	78		T13	21
auto[0]	values[7]	values[5]	540	1			T4	20		T26	20		T214	18
auto[0]	values[7]	values[6]	529	1			T4	20		T13	20		T40	21
auto[0]	values[7]	values[7]	616	1			T4	53		T40	22		T68	12
auto[1]	values[0]	values[0]	5	1			T4	1		T235	2		T140	1
auto[1]	values[0]	values[1]	9	1			T69	1		T115	2		T188	5
auto[1]	values[0]	values[2]	7	1			T27	2		T188	1		T143	1
auto[1]	values[0]	values[3]	16	1			T4	3		T8	3		T28	1
auto[1]	values[0]	values[4]	8	1			T170	1		T236	1		T237	4
auto[1]	values[0]	values[5]	6	1			T238	4		T239	2		-	-
auto[1]	values[0]	values[6]	14	1			T13	1		T32	1		T220	2
auto[1]	values[0]	values[7]	8	1			T8	2		T30	1		T240	1
auto[1]	values[1]	values[0]	6	1			T69	2		T176	1		T241	3
auto[1]	values[1]	values[1]	3	1			T242	1		T243	2		-	-
auto[1]	values[1]	values[2]	5	1			T30	1		T244	2		T245	2
auto[1]	values[1]	values[3]	4	1			T28	2		T246	2		-	-
auto[1]	values[1]	values[4]	4	1			T221	4		-	-		-	-
auto[1]	values[1]	values[5]	9	1			T28	1		T29	1		T114	2
auto[1]	values[1]	values[6]	3	1			T29	1		T247	2		-	-
auto[1]	values[1]	values[7]	6	1			T8	4		T26	2		-	-
auto[1]	values[2]	values[0]	3	1			T187	1		T201	1		T20	1
auto[1]	values[2]	values[1]	7	1			T201	2		T240	2		T247	3
auto[1]	values[2]	values[2]	5	1			T69	1		T115	1		T201	3
auto[1]	values[2]	values[3]	2	1			T115	1		T248	1		-	-
auto[1]	values[2]	values[4]	3	1			T69	2		T249	1		-	-
auto[1]	values[2]	values[5]	7	1			T13	2		T250	3		T240	2
auto[1]	values[2]	values[6]	10	1			T69	1		T116	1		T176	1
auto[1]	values[2]	values[7]	1	1			T189	1		-	-		-	-
auto[1]	values[3]	values[0]	4	1			T28	1		T29	2		T251	1
auto[1]	values[3]	values[1]	9	1			T174	4		T252	2		T251	2
auto[1]	values[3]	values[2]	7	1			T198	4		T253	1		T242	2
auto[1]	values[3]	values[3]	12	1			T4	2		T152	1		T187	2
auto[1]	values[3]	values[4]	14	1			T4	2		T8	2		T116	2
auto[1]	values[3]	values[5]	11	1			T143	2		T251	5		T254	4
auto[1]	values[3]	values[6]	4	1			T251	1		T247	1		T254	1
auto[1]	values[3]	values[7]	3	1			T202	1		T226	1		T255	1
auto[1]	values[4]	values[0]	10	1			T27	1		T179	3		T253	1
auto[1]	values[4]	values[1]	21	1			T28	4		T194	1		T186	2
auto[1]	values[4]	values[2]	6	1			T26	2		T28	2		T207	2
auto[1]	values[4]	values[3]	6	1			T29	3		T187	1		T242	2
auto[1]	values[4]	values[4]	3	1			T256	2		T140	1		-	-
auto[1]	values[4]	values[5]	10	1			T33	1		T257	2		T240	2
auto[1]	values[4]	values[6]	7	1			T258	1		T20	1		T259	1
auto[1]	values[4]	values[7]	8	1			T13	1		T247	3		T239	1
auto[1]	values[5]	values[0]	10	1			T198	1		T189	1		T250	3
auto[1]	values[5]	values[1]	11	1			T115	1		T260	3		T240	2
auto[1]	values[5]	values[2]	1	1			T248	1		-	-		-	-
auto[1]	values[5]	values[3]	9	1			T33	2		T188	1		T241	4
auto[1]	values[5]	values[4]	5	1			T69	1		T222	2		T261	1
auto[1]	values[5]	values[5]	8	1			T4	1		T240	2		T262	3
auto[1]	values[5]	values[6]	11	1			T11	1		T171	2		T69	2
auto[1]	values[5]	values[7]	1	1			T243	1		-	-		-	-
auto[1]	values[6]	values[0]	11	1			T33	1		T186	1		T263	2
auto[1]	values[6]	values[1]	3	1			T28	1		T260	2		-	-
auto[1]	values[6]	values[2]	12	1			T4	1		T13	1		T69	1
auto[1]	values[6]	values[3]	15	1			T28	1		T198	1		T115	2
auto[1]	values[6]	values[4]	5	1			T194	3		T253	2		-	-
auto[1]	values[6]	values[5]	9	1			T31	3		T189	2		T247	4
auto[1]	values[6]	values[6]	12	1			T8	1		T11	1		T32	1
auto[1]	values[6]	values[7]	8	1			T4	1		T28	2		T201	1
auto[1]	values[7]	values[0]	10	1			T69	2		T189	1		T20	1
auto[1]	values[7]	values[1]	4	1			T13	3		T201	1		-	-
auto[1]	values[7]	values[2]	4	1			T29	1		T69	1		T250	1
auto[1]	values[7]	values[3]	7	1			T173	1		T140	2		T264	1
auto[1]	values[7]	values[4]	11	1			T4	1		T13	3		T194	1
auto[1]	values[7]	values[5]	9	1			T200	4		T143	1		T262	3
auto[1]	values[7]	values[6]	4	1			T253	4		-	-		-	-
auto[1]	values[7]	values[7]	10	1			T4	4		T194	3		T253	1