Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2640

1

T1

11

T2

11

T4

8

auto[1]

2637

1

T1

12

T2

12

T4

13

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2679

1

T1

17

T2

23

T4

21

auto[1]

2598

1

T1

6

T6

8

T15

46

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4288

1

T1

14

T2

16

T4

15

auto[1]

989

1

T1

9

T2

7

T4

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1006	1			T1	2		T2	6		T4	5
valid[1]	1079	1			T1	4		T2	4		T4	5
valid[2]	1057	1			T1	3		T2	2		T4	3
valid[3]	1092	1			T1	6		T2	7		T4	6
valid[4]	1043	1			T1	8		T2	4		T4	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	164	1			T2	3		T4	1		T6	1
auto[0]	auto[0]	valid[0]	auto[1]	220	1			T6	1		T15	4		T73	5
auto[0]	auto[0]	valid[1]	auto[0]	167	1			T1	1		T2	1		T24	1
auto[0]	auto[0]	valid[1]	auto[1]	266	1			T6	1		T15	6		T73	12
auto[0]	auto[0]	valid[2]	auto[0]	186	1			T2	1		T4	2		T6	1
auto[0]	auto[0]	valid[2]	auto[1]	264	1			T15	7		T73	3		T76	1
auto[0]	auto[0]	valid[3]	auto[0]	148	1			T1	3		T2	1		T4	2
auto[0]	auto[0]	valid[3]	auto[1]	278	1			T1	1		T15	2		T16	1
auto[0]	auto[0]	valid[4]	auto[0]	165	1			T1	1		T2	1		T4	1
auto[0]	auto[0]	valid[4]	auto[1]	271	1			T1	1		T15	4		T16	1
auto[0]	auto[1]	valid[0]	auto[0]	163	1			T1	1		T2	1		T4	1
auto[0]	auto[1]	valid[0]	auto[1]	261	1			T6	2		T15	8		T73	3
auto[0]	auto[1]	valid[1]	auto[0]	180	1			T2	1		T4	3		T6	1
auto[0]	auto[1]	valid[1]	auto[1]	268	1			T1	2		T6	1		T15	5
auto[0]	auto[1]	valid[2]	auto[0]	168	1			T1	1		T2	1		T4	1
auto[0]	auto[1]	valid[2]	auto[1]	264	1			T6	2		T15	2		T16	2
auto[0]	auto[1]	valid[3]	auto[0]	157	1			T2	4		T4	3		T13	1
auto[0]	auto[1]	valid[3]	auto[1]	277	1			T15	2		T16	3		T73	1
auto[0]	auto[1]	valid[4]	auto[0]	192	1			T1	1		T2	2		T4	1
auto[0]	auto[1]	valid[4]	auto[1]	229	1			T1	2		T6	1		T15	6
auto[1]	auto[0]	valid[0]	auto[0]	111	1			T1	1		T2	2		T4	1
auto[1]	auto[0]	valid[1]	auto[0]	104	1			T2	2		T4	1		T24	1
auto[1]	auto[0]	valid[2]	auto[0]	92	1			T1	2		T26	1		T36	2
auto[1]	auto[0]	valid[3]	auto[0]	107	1			T6	1		T13	1		T25	1
auto[1]	auto[0]	valid[4]	auto[0]	97	1			T1	1		T13	2		T25	1
auto[1]	auto[1]	valid[0]	auto[0]	87	1			T4	2		T17	1		T40	1
auto[1]	auto[1]	valid[1]	auto[0]	94	1			T1	1		T4	1		T24	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T6	2		T24	1		T26	1
auto[1]	auto[1]	valid[3]	auto[0]	125	1			T1	2		T2	2		T4	1
auto[1]	auto[1]	valid[4]	auto[0]	89	1			T1	2		T2	1		T40	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal