Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67550

1

T1

366

T2

305

T4

609

auto[1]

27178

1

T1

43

T4

28

T6

75

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70176

1

T1

277

T2

207

T4

432

auto[1]

24552

1

T1

132

T2

98

T4

205

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	48752	1			T1	206		T2	148		T4	304
others[1]	7787	1			T1	32		T2	26		T4	57
others[2]	8008	1			T1	34		T2	16		T4	67
others[3]	9159	1			T1	45		T2	36		T4	63
interest[1]	5301	1			T1	25		T2	21		T4	39
interest[4]	31978	1			T1	138		T2	93		T4	196
interest[64]	15721	1			T1	67		T2	58		T4	107

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	22006	1			T1	113		T2	103		T4	197
auto[0]	auto[0]	others[1]	3559	1			T1	22		T2	17		T4	37
auto[0]	auto[0]	others[2]	3732	1			T1	19		T2	11		T4	45
auto[0]	auto[0]	others[3]	4180	1			T1	23		T2	25		T4	39
auto[0]	auto[0]	interest[1]	2368	1			T1	16		T2	10		T4	21
auto[0]	auto[0]	interest[4]	14372	1			T1	80		T2	66		T4	130
auto[0]	auto[0]	interest[64]	7153	1			T1	41		T2	41		T4	65
auto[0]	auto[1]	others[0]	14176	1			T1	21		T4	11		T6	33
auto[0]	auto[1]	others[1]	2136	1			T1	3		T4	2		T6	6
auto[0]	auto[1]	others[2]	2208	1			T1	5		T4	2		T6	10
auto[0]	auto[1]	others[3]	2625	1			T1	4		T4	4		T6	8
auto[0]	auto[1]	interest[1]	1552	1			T1	3		T4	2		T6	6
auto[0]	auto[1]	interest[4]	9504	1			T1	13		T4	6		T6	21
auto[0]	auto[1]	interest[64]	4481	1			T1	7		T4	7		T6	12
auto[1]	auto[0]	others[0]	12570	1			T1	72		T2	45		T4	96
auto[1]	auto[0]	others[1]	2092	1			T1	7		T2	9		T4	18
auto[1]	auto[0]	others[2]	2068	1			T1	10		T2	5		T4	20
auto[1]	auto[0]	others[3]	2354	1			T1	18		T2	11		T4	20
auto[1]	auto[0]	interest[1]	1381	1			T1	6		T2	11		T4	16
auto[1]	auto[0]	interest[4]	8102	1			T1	45		T2	27		T4	60
auto[1]	auto[0]	interest[64]	4087	1			T1	19		T2	17		T4	35

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal