Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	895	1			T4	18		T30	7		T32	20
all_values[1]	895	1			T4	18		T30	7		T32	20
all_values[2]	895	1			T4	18		T30	7		T32	20
all_values[3]	895	1			T4	18		T30	7		T32	20
all_values[4]	895	1			T4	18		T30	7		T32	20
all_values[5]	895	1			T4	18		T30	7		T32	20
all_values[6]	895	1			T4	18		T30	7		T32	20
all_values[7]	895	1			T4	18		T30	7		T32	20

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3749

1

T4

84

T30

28

T32

85

auto[1]

3411

1

T4

60

T30

28

T32

75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2908

1

T4

63

T30

23

T32

62

auto[1]

4252

1

T4

81

T30

33

T32

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4093

1

T4

91

T30

30

T32

87

auto[1]

3067

1

T4

53

T30

26

T32

73

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	212	1			T4	7		T30	1		T32	1
all_values[0]	auto[0]	auto[0]	auto[1]	77	1			T4	3		T32	4		T55	1
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T4	1		T30	2		T32	1
all_values[0]	auto[0]	auto[1]	auto[1]	91	1			T4	1		T32	2		T55	2
all_values[0]	auto[1]	auto[0]	auto[1]	204	1			T4	4		T32	7		T55	4
all_values[0]	auto[1]	auto[1]	auto[1]	175	1			T4	2		T30	4		T32	5
all_values[1]	auto[0]	auto[0]	auto[0]	176	1			T4	4		T30	2		T32	5
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T4	4		T32	1		T55	2
all_values[1]	auto[0]	auto[1]	auto[0]	146	1			T4	1		T32	5		T55	4
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T4	3		T30	1		T32	1
all_values[1]	auto[1]	auto[0]	auto[1]	215	1			T4	3		T30	2		T32	5
all_values[1]	auto[1]	auto[1]	auto[1]	185	1			T4	3		T30	2		T32	3
all_values[2]	auto[0]	auto[0]	auto[0]	196	1			T4	3		T30	2		T32	6
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T4	1		T113	1		T137	1
all_values[2]	auto[0]	auto[1]	auto[0]	178	1			T4	5		T30	2		T32	5
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T4	1		T32	4		T55	1
all_values[2]	auto[1]	auto[0]	auto[1]	206	1			T4	3		T30	2		T32	3
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T4	5		T30	1		T32	2
all_values[3]	auto[0]	auto[0]	auto[0]	166	1			T4	7		T30	1		T32	2
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T4	1		T30	1		T32	5
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T4	2		T30	1		T55	4
all_values[3]	auto[0]	auto[1]	auto[1]	107	1			T30	1		T32	1		T55	4
all_values[3]	auto[1]	auto[0]	auto[1]	196	1			T4	5		T30	1		T32	5
all_values[3]	auto[1]	auto[1]	auto[1]	179	1			T4	3		T30	2		T32	7
all_values[4]	auto[0]	auto[0]	auto[0]	190	1			T4	6		T30	1		T32	8
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T4	1		T30	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T4	5		T32	3		T55	3
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T4	2		T30	1		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T4	3		T30	2		T32	2
all_values[4]	auto[1]	auto[1]	auto[1]	177	1			T4	1		T30	2		T32	5
all_values[5]	auto[0]	auto[0]	auto[0]	289	1			T4	8		T30	2		T32	7
all_values[5]	auto[0]	auto[1]	auto[0]	240	1			T4	4		T30	2		T32	4
all_values[5]	auto[1]	auto[0]	auto[1]	182	1			T4	5		T30	1		T32	4
all_values[5]	auto[1]	auto[1]	auto[1]	184	1			T4	1		T30	2		T32	5
all_values[6]	auto[0]	auto[0]	auto[0]	159	1			T32	4		T55	1		T137	3
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T4	3		T30	1		T32	2
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T4	6		T30	2		T55	6
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T4	2		T32	2		T55	2
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T30	3		T32	3		T55	3
all_values[6]	auto[1]	auto[1]	auto[1]	207	1			T4	7		T30	1		T32	9
all_values[7]	auto[0]	auto[0]	auto[0]	191	1			T4	4		T30	3		T32	5
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T4	4		T30	1		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	167	1			T30	2		T32	6		T55	10
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T4	2		T55	1		T113	1
all_values[7]	auto[1]	auto[0]	auto[1]	183	1			T4	5		T30	1		T32	4
all_values[7]	auto[1]	auto[1]	auto[1]	197	1			T4	3		T32	4		T55	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal