Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7674346	1			T1	14115		T2	4703		T3	1
all_values[1]	7674346	1			T1	14115		T2	4703		T3	1
all_values[2]	7674346	1			T1	14115		T2	4703		T3	1
all_values[3]	7674346	1			T1	14115		T2	4703		T3	1
all_values[4]	7674346	1			T1	14115		T2	4703		T3	1
all_values[5]	7674346	1			T1	14115		T2	4703		T3	1
all_values[6]	7674346	1			T1	14115		T2	4703		T3	1
all_values[7]	7674346	1			T1	14115		T2	4703		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60192110

1

T1

112920

T2

37624

T3

8

auto[1]

1202658

1

T6

43

T13

61

T52

48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61315097

1

T1

112233

T2

37624

T3

8

auto[1]

79671

1

T1

687

T5

639

T6

501

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	7394368	1			T1	13728		T2	4703		T3	1
all_values[0]	auto[0]	auto[1]	44321	1			T1	387		T5	375		T6	259
all_values[0]	auto[1]	auto[0]	233612	1			T6	7		T13	4		T52	3
all_values[0]	auto[1]	auto[1]	2045	1			T6	1		T13	3		T52	3
all_values[1]	auto[0]	auto[0]	7576901	1			T1	13883		T2	4703		T3	1
all_values[1]	auto[0]	auto[1]	22236	1			T1	232		T5	150		T6	141
all_values[1]	auto[1]	auto[0]	74196	1			T6	2		T13	3		T52	1
all_values[1]	auto[1]	auto[1]	1013	1			T6	1		T13	2		T52	4
all_values[2]	auto[0]	auto[0]	7535088	1			T1	14047		T2	4703		T3	1
all_values[2]	auto[0]	auto[1]	7502	1			T1	68		T5	114		T6	73
all_values[2]	auto[1]	auto[0]	131388	1			T6	2		T13	5		T52	5
all_values[2]	auto[1]	auto[1]	368	1			T6	2		T13	5		T52	3
all_values[3]	auto[0]	auto[0]	7651133	1			T1	14115		T2	4703		T3	1
all_values[3]	auto[0]	auto[1]	208	1			T6	4		T13	8		T52	4
all_values[3]	auto[1]	auto[0]	22803	1			T6	4		T13	3		T52	1
all_values[3]	auto[1]	auto[1]	202	1			T6	1		T13	3		T52	1
all_values[4]	auto[0]	auto[0]	7480163	1			T1	14115		T2	4703		T3	1
all_values[4]	auto[0]	auto[1]	224	1			T6	3		T13	2		T52	1
all_values[4]	auto[1]	auto[0]	193772	1			T6	1		T13	2		T52	4
all_values[4]	auto[1]	auto[1]	187	1			T6	3		T13	6		T52	1
all_values[5]	auto[0]	auto[0]	7541630	1			T1	14115		T2	4703		T3	1
all_values[5]	auto[0]	auto[1]	426	1			T6	3		T13	2		T140	6
all_values[5]	auto[1]	auto[0]	132114	1			T6	3		T13	9		T52	6
all_values[5]	auto[1]	auto[1]	176	1			T6	4		T13	2		T52	3
all_values[6]	auto[0]	auto[0]	7463945	1			T1	14115		T2	4703		T3	1
all_values[6]	auto[0]	auto[1]	175	1			T6	3		T13	4		T56	1
all_values[6]	auto[1]	auto[0]	210020	1			T6	4		T13	5		T52	2
all_values[6]	auto[1]	auto[1]	206	1			T13	5		T52	3		T56	3
all_values[7]	auto[0]	auto[0]	7473610	1			T1	14115		T2	4703		T3	1
all_values[7]	auto[0]	auto[1]	180	1			T6	1		T13	4		T127	8
all_values[7]	auto[1]	auto[0]	200354	1			T6	6		T13	4		T52	5
all_values[7]	auto[1]	auto[1]	202	1			T6	2		T52	3		T56	3