Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	38081	1			T1	139		T3	2		T4	10
auto[SpiFlashAddrCfg]	8988	1			T1	21		T4	3		T5	58
auto[SpiFlashAddr3b]	10981	1			T1	26		T3	4		T4	6
auto[SpiFlashAddr4b]	8930	1			T1	30		T4	1		T5	53

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38900

1

T1

130

T3

6

T4

12

auto[1]

28080

1

T1

86

T4

8

T5

199

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35842

1

T1

109

T3

6

T4

11

auto[1]

31138

1

T1

107

T4

9

T5

183

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	43367	1			T1	158		T3	2		T4	11
values[1]	1413	1			T1	7		T5	7		T6	7
values[2]	1681	1			T1	5		T5	9		T6	7
values[3]	1654	1			T1	7		T4	2		T5	15
values[4]	1698	1			T1	2		T4	2		T5	7
values[5]	1736	1			T1	5		T5	13		T6	11
values[6]	1757	1			T1	1		T5	21		T6	7
values[7]	1820	1			T5	14		T6	4		T11	4
values[8]	11854	1			T1	31		T3	4		T4	5

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32420

1

T3

6

T4

20

T6

270

auto[1]

34560

1

T1

216

T5

518

T13

326

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

64414

1

T1

204

T3

6

T4

20

write

2566

1

T1

12

T5

27

T6

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

23459

1

T1

85

T3

4

T4

10

valids[0x1]

43521

1

T1

131

T3

2

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1855	1			T1	9		T5	14		T6	7
internal_process_ops[0x5a]	1911	1			T1	5		T4	2		T5	12
internal_process_ops[0x05]	21460	1			T1	62		T3	2		T4	3
internal_process_ops[0x35]	1948	1			T1	9		T5	15		T6	11
internal_process_ops[0x15]	1909	1			T1	6		T4	1		T5	16
internal_process_ops[0x03]	1239	1			T1	1		T6	6		T7	4
internal_process_ops[0x0b]	1330	1			T1	1		T5	4		T6	6
internal_process_ops[0x3b]	1347	1			T1	1		T4	1		T5	4
internal_process_ops[0x6b]	1315	1			T1	1		T5	5		T6	10
internal_process_ops[0xbb]	1343	1			T1	1		T3	4		T5	3
internal_process_ops[0xeb]	1284	1			T1	1		T4	2		T5	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

65682

1

T1

205

T3

6

T4

20

auto[1]

1298

1

T1

11

T5

17

T6

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64565

1

T1

200

T3

6

T4

20

auto[1]

2415

1

T1

16

T5

17

T6

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11323

1

T3

2

T4

7

T6

76

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5546

1

T4

3

T6

72

T7

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2503

1

T6

20

T12

21

T24

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2048

1

T4

3

T6

17

T7

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2993

1

T3

4

T4

4

T6

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2359

1

T4

2

T6

14

T7

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2458

1

T4

1

T6

22

T12

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2070

1

T6

18

T7

2

T8

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

85

1

T134

2

T135

2

T28

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

59

1

T25

1

T28

1

T30

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

66

1

T12

1

T127

3

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T6

3

T11

2

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

82

1

T24

3

T136

3

T25

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

63

1

T6

3

T12

1

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

68

1

T12

2

T25

1

T127

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

73

1

T12

1

T27

2

T13

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

80

1

T26

1

T127

1

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

80

1

T12

2

T25

1

T28

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T12

1

T25

1

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T6

2

T7

4

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

64

1

T13

1

T25

2

T137

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T12

2

T25

1

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T12

1

T44

2

T138

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

78

1

T11

4

T12

2

T25

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11720

1

T1

86

T5

216

T13

108

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8858

1

T1

51

T5

101

T13

55

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1996

1

T1

9

T5

24

T13

28

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1758

1

T1

10

T5

24

T13

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2636

1

T1

13

T5

44

T13

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2337

1

T1

10

T5

35

T13

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2002

1

T1

15

T5

24

T13

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1807

1

T1

10

T5

23

T13

21

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

86

1

T5

1

T13

1

T31

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

65

1

T1

2

T5

1

T31

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T5

1

T16

2

T35

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

83

1

T5

1

T13

2

T16

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T5

2

T16

1

T31

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T5

3

T31

8

T35

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T5

1

T13

1

T16

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T1

2

T5

4

T35

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

85

1

T35

1

T70

2

T65

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

73

1

T1

1

T13

4

T35

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T1

1

T5

2

T13

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

111

1

T1

1

T5

5

T16

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T5

1

T70

2

T65

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

103

1

T1

4

T5

3

T31

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T5

2

T13

1

T70

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T1

1

T31

1

T35

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4640	1			T4	5		T6	48		T12	43
auto[0]	values[0]	valids[0x1]	15096	1			T3	2		T4	6		T6	123
auto[0]	values[1]	valids[0x1]	691	1			T6	7		T12	2		T13	5
auto[0]	values[2]	valids[0x0]	599	1			T6	7		T12	3		T24	1
auto[0]	values[2]	valids[0x1]	318	1			T12	3		T24	1		T13	1
auto[0]	values[3]	valids[0x0]	591	1			T4	2		T6	3		T12	5
auto[0]	values[3]	valids[0x1]	352	1			T6	2		T8	4		T11	2
auto[0]	values[4]	valids[0x0]	575	1			T6	3		T12	2		T24	1
auto[0]	values[4]	valids[0x1]	312	1			T4	2		T8	2		T12	9
auto[0]	values[5]	valids[0x0]	600	1			T6	8		T12	3		T24	2
auto[0]	values[5]	valids[0x1]	324	1			T6	3		T12	1		T24	1
auto[0]	values[6]	valids[0x0]	599	1			T6	5		T7	6		T8	2
auto[0]	values[6]	valids[0x1]	325	1			T6	2		T24	2		T13	1
auto[0]	values[7]	valids[0x0]	667	1			T6	1		T11	4		T12	5
auto[0]	values[7]	valids[0x1]	334	1			T6	3		T12	5		T139	8
auto[0]	values[8]	valids[0x0]	3942	1			T3	4		T4	3		T6	36
auto[0]	values[8]	valids[0x1]	2455	1			T4	2		T6	19		T7	8
auto[1]	values[0]	valids[0x0]	5067	1			T1	51		T5	57		T13	71
auto[1]	values[0]	valids[0x1]	18564	1			T1	107		T5	301		T13	128
auto[1]	values[1]	valids[0x1]	722	1			T1	7		T5	7		T13	10
auto[1]	values[2]	valids[0x0]	454	1			T1	3		T5	9		T13	8
auto[1]	values[2]	valids[0x1]	310	1			T1	2		T13	2		T16	5
auto[1]	values[3]	valids[0x0]	408	1			T1	3		T5	10		T13	3
auto[1]	values[3]	valids[0x1]	303	1			T1	4		T5	5		T13	4
auto[1]	values[4]	valids[0x0]	522	1			T1	2		T5	6		T13	10
auto[1]	values[4]	valids[0x1]	289	1			T5	1		T13	1		T31	1
auto[1]	values[5]	valids[0x0]	513	1			T1	3		T5	5		T13	8
auto[1]	values[5]	valids[0x1]	299	1			T1	2		T5	8		T13	4
auto[1]	values[6]	valids[0x0]	498	1			T5	11		T13	7		T16	3
auto[1]	values[6]	valids[0x1]	335	1			T1	1		T5	10		T13	9
auto[1]	values[7]	valids[0x0]	469	1			T5	6		T13	8		T31	8
auto[1]	values[7]	valids[0x1]	350	1			T5	8		T13	5		T31	5
auto[1]	values[8]	valids[0x0]	3315	1			T1	23		T5	37		T13	33
auto[1]	values[8]	valids[0x1]	2142	1			T1	8		T5	37		T13	15