Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19213

1

T1

80

T3

6

T4

7

auto[1]

21869

1

T1

72

T5

215

T6

81

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16037

1

T1

75

T3

4

T4

3

auto[1]

25045

1

T1

77

T3

2

T4

4

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7868	1			T1	33		T3	1		T4	3
auto[524288:1048575]	5053	1			T1	14		T5	58		T6	38
auto[1048576:1572863]	5010	1			T1	22		T4	4		T5	32
auto[1572864:2097151]	4738	1			T1	7		T3	1		T5	13
auto[2097152:2621439]	4427	1			T1	11		T5	62		T6	9
auto[2621440:3145727]	4685	1			T1	27		T5	49		T6	18
auto[3145728:3670015]	5068	1			T1	10		T3	3		T5	109
auto[3670016:4194303]	4233	1			T1	28		T3	1		T5	12

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40289

1

T1

151

T3

6

T4

7

auto[1]

793

1

T1

1

T5

1

T12

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32683

1

T1

104

T3

6

T4

6

auto[1]

8399

1

T1

48

T4

1

T5

148

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1998	1			T1	10		T3	1		T4	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	816	1			T1	4		T4	1		T5	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	1292	1			T1	3		T5	12		T6	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	454	1			T1	2		T5	7		T6	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	1375	1			T1	11		T4	1		T5	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	523	1			T1	1		T4	2		T5	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	1271	1			T1	3		T3	1		T5	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	510	1			T1	1		T5	1		T6	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	1267	1			T5	16		T6	2		T12	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	537	1			T1	7		T5	8		T12	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	1281	1			T1	2		T5	4		T6	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	544	1			T5	2		T6	2		T12	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	1388	1			T1	2		T3	2		T5	10
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	544	1			T3	1		T5	6		T6	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	1253	1			T1	2		T5	1		T6	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	486	1			T3	1		T5	4		T6	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	370	1			T1	4		T5	1		T12	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	167	1			T1	1		T12	1		T31	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	302	1			T5	2		T6	1		T35	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	156	1			T13	1		T31	1		T35	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	304	1			T12	1		T13	4		T31	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	123	1			T4	1		T5	1		T13	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	293	1			T1	1		T5	3		T6	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	119	1			T12	1		T31	1		T35	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	289	1			T1	3		T5	3		T6	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	145	1			T1	1		T5	1		T6	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	323	1			T1	8		T5	4		T6	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	164	1			T1	2		T12	1		T13	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	325	1			T1	1		T5	11		T6	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	163	1			T5	7		T6	1		T13	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	290	1			T1	9		T5	3		T6	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	141	1			T1	2		T6	1		T13	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	357	1			T1	2		T6	3		T12	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3373	1			T1	7		T6	15		T12	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	225	1			T1	2		T5	3		T6	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2025	1			T1	7		T5	34		T6	24
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	266	1			T1	2		T5	2		T6	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1806	1			T1	8		T5	21		T6	21
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	234	1			T1	1		T5	1		T12	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1769	1			T1	1		T5	2		T12	45
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	203	1			T5	5		T6	1		T12	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1489	1			T5	29		T6	2		T12	18
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	197	1			T1	1		T6	2		T12	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1529	1			T1	8		T6	8		T12	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	240	1			T1	2		T5	2		T12	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1823	1			T1	5		T5	4		T12	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	223	1			T1	1		T13	3		T16	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1385	1			T1	9		T13	6		T16	10
auto[1]	auto[1]	auto[0:524287]	auto[0]	67	1			T1	1		T12	1		T13	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	720	1			T1	4		T12	10		T13	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	48	1			T25	2		T70	1		T28	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	551	1			T25	42		T70	1		T28	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	60	1			T13	2		T31	2		T25	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	553	1			T13	2		T31	57		T25	45
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	55	1			T12	2		T16	1		T35	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	487	1			T12	27		T16	2		T35	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	59	1			T13	1		T31	1		T70	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	438	1			T13	3		T31	21		T70	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	67	1			T1	2		T5	1		T12	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	580	1			T1	4		T5	38		T12	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	65	1			T5	2		T13	2		T31	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	520	1			T5	67		T13	6		T31	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	50	1			T1	2		T5	1		T13	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	405	1			T1	3		T5	3		T13	12

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	15226	1			T1	47		T3	6		T4	6
auto[0]	auto[0]	auto[1]	313	1			T1	1		T12	1		T24	1
auto[0]	auto[1]	auto[0]	3577	1			T1	32		T4	1		T5	35
auto[0]	auto[1]	auto[1]	97	1			T5	1		T13	1		T31	4
auto[1]	auto[0]	auto[0]	16833	1			T1	56		T5	103		T6	81
auto[1]	auto[0]	auto[1]	311	1			T12	2		T24	1		T35	2
auto[1]	auto[1]	auto[0]	4653	1			T1	16		T5	112		T12	41
auto[1]	auto[1]	auto[1]	72	1			T12	1		T31	1		T35	1