Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19849

1

T3

6

T4

12

T6

144

auto[1]

12571

1

T4

8

T6

126

T7

26

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4199	1			T4	20		T6	26		T12	28
values[1]	3941	1			T7	26		T10	6		T12	141
values[2]	4480	1			T6	45		T12	46		T24	49
values[3]	3410	1			T6	28		T8	22		T82	6
values[4]	3975	1			T3	6		T6	80		T11	24
values[5]	4022	1			T6	49		T12	25		T24	20
values[6]	4167	1			T6	20		T24	81		T27	12
values[7]	4226	1			T6	22		T147	26		T192	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4727	1			T6	22		T8	22		T12	21
values[1]	3969	1			T7	26		T10	6		T12	67
values[2]	4159	1			T3	6		T6	20		T12	28
values[3]	3578	1			T24	81		T13	20		T25	111
values[4]	4517	1			T4	20		T6	26		T12	109
values[5]	4119	1			T6	73		T11	24		T12	20
values[6]	4043	1			T6	40		T12	48		T13	23
values[7]	3308	1			T6	89		T12	25		T24	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	318	1			T193	6		T28	11		T30	9
auto[0]	values[0]	values[1]	455	1			T173	14		T28	14		T50	16
auto[0]	values[0]	values[2]	332	1			T12	20		T26	17		T164	17
auto[0]	values[0]	values[3]	222	1			T194	22		T152	9		T170	15
auto[0]	values[0]	values[4]	350	1			T4	12		T6	21		T26	15
auto[0]	values[0]	values[5]	510	1			T28	13		T30	11		T128	25
auto[0]	values[0]	values[6]	364	1			T25	86		T159	9		T152	11
auto[0]	values[0]	values[7]	179	1			T136	15		T137	10		T150	10
auto[0]	values[1]	values[0]	248	1			T155	76		T18	5		T195	7
auto[0]	values[1]	values[1]	339	1			T10	6		T12	9		T30	14
auto[0]	values[1]	values[2]	282	1			T25	20		T68	13		T138	24
auto[0]	values[1]	values[3]	277	1			T44	11		T138	10		T157	10
auto[0]	values[1]	values[4]	419	1			T12	64		T26	10		T196	24
auto[0]	values[1]	values[5]	210	1			T12	12		T44	13		T171	38
auto[0]	values[1]	values[6]	417	1			T168	10		T30	10		T128	66
auto[0]	values[1]	values[7]	186	1			T25	17		T18	13		T197	7
auto[0]	values[2]	values[0]	385	1			T12	16		T198	10		T152	22
auto[0]	values[2]	values[1]	424	1			T13	5		T28	13		T44	8
auto[0]	values[2]	values[2]	410	1			T28	12		T44	13		T138	13
auto[0]	values[2]	values[3]	325	1			T25	22		T152	125		T199	22
auto[0]	values[2]	values[4]	378	1			T160	16		T30	14		T44	9
auto[0]	values[2]	values[5]	260	1			T6	17		T24	15		T30	7
auto[0]	values[2]	values[6]	285	1			T6	14		T28	9		T30	13
auto[0]	values[2]	values[7]	319	1			T12	19		T170	14		T197	13
auto[0]	values[3]	values[0]	353	1			T82	6		T152	4		T157	20
auto[0]	values[3]	values[1]	298	1			T25	40		T68	13		T30	6
auto[0]	values[3]	values[2]	136	1			T37	9		T157	13		T200	12
auto[0]	values[3]	values[3]	198	1			T152	13		T201	6		T202	10
auto[0]	values[3]	values[4]	404	1			T151	12		T67	14		T28	8
auto[0]	values[3]	values[5]	226	1			T6	23		T159	8		T128	12
auto[0]	values[3]	values[6]	191	1			T127	14		T138	14		T170	10
auto[0]	values[3]	values[7]	298	1			T25	72		T44	12		T170	8
auto[0]	values[4]	values[0]	382	1			T152	18		T203	4		T183	20
auto[0]	values[4]	values[1]	190	1			T12	24		T44	23		T159	12
auto[0]	values[4]	values[2]	277	1			T3	6		T25	9		T30	11
auto[0]	values[4]	values[3]	373	1			T25	43		T204	8		T134	40
auto[0]	values[4]	values[4]	350	1			T25	15		T30	29		T149	14
auto[0]	values[4]	values[5]	304	1			T152	13		T150	3		T205	16
auto[0]	values[4]	values[6]	247	1			T6	13		T12	9		T28	17
auto[0]	values[4]	values[7]	248	1			T6	10		T127	10		T159	8
auto[0]	values[5]	values[0]	250	1			T44	18		T152	13		T164	10
auto[0]	values[5]	values[1]	288	1			T153	23		T44	7		T182	12
auto[0]	values[5]	values[2]	210	1			T6	9		T206	4		T28	13
auto[0]	values[5]	values[3]	200	1			T13	15		T169	12		T172	32
auto[0]	values[5]	values[4]	240	1			T12	12		T166	4		T28	25
auto[0]	values[5]	values[5]	216	1			T25	11		T156	27		T200	12
auto[0]	values[5]	values[6]	483	1			T13	14		T25	14		T30	13
auto[0]	values[5]	values[7]	320	1			T6	15		T24	9		T128	7
auto[0]	values[6]	values[0]	475	1			T26	8		T189	28		T127	7
auto[0]	values[6]	values[1]	282	1			T25	9		T127	15		T153	10
auto[0]	values[6]	values[2]	297	1			T37	10		T128	10		T152	105
auto[0]	values[6]	values[3]	482	1			T24	9		T25	24		T68	7
auto[0]	values[6]	values[4]	227	1			T207	16		T208	16		T209	12
auto[0]	values[6]	values[5]	275	1			T6	13		T150	66		T157	32
auto[0]	values[6]	values[6]	255	1			T148	6		T28	13		T164	12
auto[0]	values[6]	values[7]	201	1			T25	18		T30	24		T210	6
auto[0]	values[7]	values[0]	474	1			T6	9		T139	28		T28	14
auto[0]	values[7]	values[1]	171	1			T30	9		T211	2		T150	19
auto[0]	values[7]	values[2]	477	1			T25	11		T26	14		T135	14
auto[0]	values[7]	values[3]	349	1			T63	2		T37	10		T156	34
auto[0]	values[7]	values[4]	434	1			T192	6		T212	4		T128	17
auto[0]	values[7]	values[5]	399	1			T170	36		T18	14		T213	15
auto[0]	values[7]	values[6]	263	1			T147	26		T26	19		T214	8
auto[0]	values[7]	values[7]	212	1			T26	12		T28	41		T30	26
auto[1]	values[0]	values[0]	229	1			T28	11		T30	11		T44	12
auto[1]	values[0]	values[1]	170	1			T28	6		T37	12		T128	6
auto[1]	values[0]	values[2]	231	1			T12	8		T26	3		T164	4
auto[1]	values[0]	values[3]	86	1			T152	11		T170	5		T175	8
auto[1]	values[0]	values[4]	196	1			T4	8		T6	5		T26	5
auto[1]	values[0]	values[5]	148	1			T28	7		T30	9		T128	6
auto[1]	values[0]	values[6]	203	1			T25	17		T159	19		T152	9
auto[1]	values[0]	values[7]	206	1			T136	5		T150	34		T157	33
auto[1]	values[1]	values[0]	215	1			T155	11		T18	15		T195	16
auto[1]	values[1]	values[1]	245	1			T7	26		T12	28		T30	6
auto[1]	values[1]	values[2]	157	1			T25	4		T68	7		T138	20
auto[1]	values[1]	values[3]	124	1			T44	10		T138	10		T157	10
auto[1]	values[1]	values[4]	317	1			T12	20		T26	10		T153	10
auto[1]	values[1]	values[5]	183	1			T12	8		T44	7		T171	4
auto[1]	values[1]	values[6]	215	1			T30	10		T128	8		T150	29
auto[1]	values[1]	values[7]	107	1			T25	3		T18	16		T197	13
auto[1]	values[2]	values[0]	158	1			T12	5		T152	12		T150	8
auto[1]	values[2]	values[1]	176	1			T13	15		T28	7		T44	22
auto[1]	values[2]	values[2]	291	1			T28	8		T44	7		T138	7
auto[1]	values[2]	values[3]	93	1			T25	9		T152	5		T171	3
auto[1]	values[2]	values[4]	366	1			T69	10		T30	16		T44	18
auto[1]	values[2]	values[5]	250	1			T6	8		T24	34		T30	13
auto[1]	values[2]	values[6]	193	1			T6	6		T28	13		T30	7
auto[1]	values[2]	values[7]	167	1			T12	6		T170	10		T197	7
auto[1]	values[3]	values[0]	228	1			T8	22		T152	18		T157	8
auto[1]	values[3]	values[1]	254	1			T25	11		T68	7		T30	15
auto[1]	values[3]	values[2]	116	1			T37	11		T157	7		T200	18
auto[1]	values[3]	values[3]	111	1			T152	7		T202	10		T19	9
auto[1]	values[3]	values[4]	138	1			T28	12		T37	12		T152	7
auto[1]	values[3]	values[5]	151	1			T6	5		T159	12		T128	11
auto[1]	values[3]	values[6]	102	1			T127	6		T138	6		T170	10
auto[1]	values[3]	values[7]	206	1			T25	20		T44	9		T170	12
auto[1]	values[4]	values[0]	212	1			T152	2		T164	18		T197	10
auto[1]	values[4]	values[1]	136	1			T12	6		T44	27		T159	8
auto[1]	values[4]	values[2]	238	1			T25	36		T30	12		T153	7
auto[1]	values[4]	values[3]	133	1			T25	10		T28	14		T153	8
auto[1]	values[4]	values[4]	205	1			T25	5		T30	4		T138	5
auto[1]	values[4]	values[5]	269	1			T11	24		T152	7		T150	69
auto[1]	values[4]	values[6]	193	1			T6	7		T12	39		T28	10
auto[1]	values[4]	values[7]	218	1			T6	50		T127	11		T159	12
auto[1]	values[5]	values[0]	352	1			T29	32		T44	12		T215	20
auto[1]	values[5]	values[1]	181	1			T153	20		T44	13		T157	10
auto[1]	values[5]	values[2]	156	1			T6	11		T28	7		T37	8
auto[1]	values[5]	values[3]	165	1			T13	5		T200	7		T171	14
auto[1]	values[5]	values[4]	282	1			T12	13		T188	6		T28	16
auto[1]	values[5]	values[5]	247	1			T25	45		T156	15		T200	12
auto[1]	values[5]	values[6]	311	1			T13	9		T25	22		T30	7
auto[1]	values[5]	values[7]	121	1			T6	14		T24	11		T128	13
auto[1]	values[6]	values[0]	303	1			T26	12		T127	26		T30	10
auto[1]	values[6]	values[1]	236	1			T25	11		T127	7		T153	10
auto[1]	values[6]	values[2]	190	1			T27	12		T37	10		T128	10
auto[1]	values[6]	values[3]	304	1			T24	72		T25	3		T68	29
auto[1]	values[6]	values[4]	69	1			T208	5		T216	9		T217	18
auto[1]	values[6]	values[5]	197	1			T6	7		T150	11		T157	32
auto[1]	values[6]	values[6]	200	1			T28	9		T164	9		T155	12
auto[1]	values[6]	values[7]	174	1			T25	8		T30	19		T150	11
auto[1]	values[7]	values[0]	145	1			T6	13		T28	6		T30	10
auto[1]	values[7]	values[1]	124	1			T30	11		T150	1		T18	7
auto[1]	values[7]	values[2]	359	1			T25	22		T26	6		T30	18
auto[1]	values[7]	values[3]	136	1			T37	14		T156	9		T195	20
auto[1]	values[7]	values[4]	142	1			T128	13		T170	10		T18	9
auto[1]	values[7]	values[5]	274	1			T170	17		T18	10		T213	5
auto[1]	values[7]	values[6]	121	1			T26	5		T37	13		T218	33
auto[1]	values[7]	values[7]	146	1			T26	12		T28	24		T30	6