Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16456

1

T3

3

T4

10

T6

144

auto[1]

50524

1

T1

216

T3

3

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1519	1			T1	1		T5	4		T6	7
auto[4:7]	25139	1			T1	78		T3	2		T4	4
auto[8:11]	1571	1			T1	2		T5	5		T6	6
auto[12:15]	419	1			T1	1		T5	6		T12	4
auto[16:19]	402	1			T1	2		T5	5		T6	1
auto[20:23]	2206	1			T1	6		T4	1		T5	17
auto[24:27]	337	1			T1	2		T5	3		T6	4
auto[28:31]	410	1			T5	7		T24	2		T13	5
auto[32:35]	430	1			T5	5		T6	2		T12	4
auto[36:39]	342	1			T12	3		T24	1		T13	2
auto[40:43]	340	1			T1	5		T5	4		T12	4
auto[44:47]	405	1			T1	2		T6	1		T27	2
auto[48:51]	363	1			T6	1		T13	4		T16	3
auto[52:55]	2213	1			T1	9		T4	1		T5	18
auto[56:59]	1629	1			T1	4		T4	1		T5	7
auto[60:63]	395	1			T1	1		T4	1		T5	2
auto[64:67]	333	1			T1	1		T4	3		T6	2
auto[68:71]	378	1			T1	2		T5	6		T6	3
auto[72:75]	336	1			T12	2		T13	1		T16	5
auto[76:79]	387	1			T1	1		T5	1		T24	2
auto[80:83]	376	1			T1	2		T24	2		T13	1
auto[84:87]	379	1			T1	2		T8	2		T12	1
auto[88:91]	2211	1			T1	6		T4	2		T5	15
auto[92:95]	361	1			T5	4		T6	1		T31	2
auto[96:99]	354	1			T1	4		T5	3		T11	2
auto[100:103]	348	1			T1	1		T5	5		T6	2
auto[104:107]	1575	1			T1	2		T5	5		T6	10
auto[108:111]	395	1			T5	5		T6	2		T13	5
auto[112:115]	420	1			T5	3		T13	2		T16	1
auto[116:119]	410	1			T1	1		T5	9		T6	2
auto[120:123]	443	1			T5	4		T7	2		T8	2
auto[124:127]	348	1			T5	8		T6	3		T7	2
auto[128:131]	341	1			T1	1		T5	1		T13	6
auto[132:135]	363	1			T1	7		T5	1		T6	1
auto[136:139]	367	1			T1	2		T5	2		T6	1
auto[140:143]	383	1			T5	5		T6	9		T13	6
auto[144:147]	387	1			T5	3		T6	2		T12	4
auto[148:151]	398	1			T1	1		T5	4		T6	3
auto[152:155]	367	1			T1	2		T5	6		T6	1
auto[156:159]	2174	1			T1	10		T5	17		T6	7
auto[160:163]	395	1			T5	2		T31	3		T35	3
auto[164:167]	372	1			T5	4		T6	5		T12	3
auto[168:171]	416	1			T6	1		T13	3		T16	1
auto[172:175]	361	1			T1	3		T5	2		T12	2
auto[176:179]	366	1			T1	2		T5	8		T12	2
auto[180:183]	2090	1			T1	12		T4	1		T5	13
auto[184:187]	1619	1			T1	1		T3	4		T5	8
auto[188:191]	361	1			T1	1		T5	4		T12	1
auto[192:195]	389	1			T1	5		T5	3		T6	4
auto[196:199]	374	1			T1	1		T5	6		T6	6
auto[200:203]	378	1			T1	2		T4	2		T5	3
auto[204:207]	415	1			T1	4		T5	2		T12	1
auto[208:211]	378	1			T1	2		T5	4		T12	3
auto[212:215]	388	1			T5	5		T6	2		T31	1
auto[216:219]	384	1			T5	1		T6	2		T13	1
auto[220:223]	370	1			T5	1		T6	1		T8	2
auto[224:227]	374	1			T1	2		T4	1		T5	7
auto[228:231]	394	1			T1	1		T5	5		T6	1
auto[232:235]	3254	1			T1	13		T4	2		T5	14
auto[236:239]	353	1			T1	2		T5	2		T6	7
auto[240:243]	381	1			T1	4		T12	1		T13	2
auto[244:247]	403	1			T1	1		T5	2		T24	1
auto[248:251]	426	1			T1	1		T4	1		T5	1
auto[252:255]	385	1			T1	1		T5	4		T12	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	512	1			T6	3		T7	2		T8	2
auto[0:3]	auto[1]	1007	1			T1	1		T5	4		T6	4
auto[4:7]	auto[0]	5560	1			T3	1		T4	1		T6	57
auto[4:7]	auto[1]	19579	1			T1	78		T3	1		T4	3
auto[8:11]	auto[0]	523	1			T6	3		T7	1		T11	2
auto[8:11]	auto[1]	1048	1			T1	2		T5	5		T6	3
auto[12:15]	auto[0]	80	1			T12	3		T26	3		T30	2
auto[12:15]	auto[1]	339	1			T1	1		T5	6		T12	1
auto[16:19]	auto[0]	92	1			T12	2		T24	1		T139	4
auto[16:19]	auto[1]	310	1			T1	2		T5	5		T6	1
auto[20:23]	auto[0]	525	1			T6	1		T8	2		T10	3
auto[20:23]	auto[1]	1681	1			T1	6		T4	1		T5	17
auto[24:27]	auto[0]	72	1			T25	1		T69	1		T28	3
auto[24:27]	auto[1]	265	1			T1	2		T5	3		T6	4
auto[28:31]	auto[0]	118	1			T147	3		T26	1		T134	1
auto[28:31]	auto[1]	292	1			T5	7		T24	2		T13	5
auto[32:35]	auto[0]	98	1			T6	1		T12	4		T25	2
auto[32:35]	auto[1]	332	1			T5	5		T6	1		T13	2
auto[36:39]	auto[0]	78	1			T12	2		T24	1		T28	2
auto[36:39]	auto[1]	264	1			T12	1		T13	2		T16	3
auto[40:43]	auto[0]	83	1			T12	4		T26	1		T153	1
auto[40:43]	auto[1]	257	1			T1	5		T5	4		T13	2
auto[44:47]	auto[0]	76	1			T6	1		T27	1		T68	1
auto[44:47]	auto[1]	329	1			T1	2		T27	1		T13	3
auto[48:51]	auto[0]	85	1			T6	1		T28	2		T153	2
auto[48:51]	auto[1]	278	1			T13	4		T16	3		T31	3
auto[52:55]	auto[0]	539	1			T4	1		T6	4		T7	3
auto[52:55]	auto[1]	1674	1			T1	9		T5	18		T6	8
auto[56:59]	auto[0]	517	1			T4	1		T6	2		T11	2
auto[56:59]	auto[1]	1112	1			T1	4		T5	7		T6	3
auto[60:63]	auto[0]	100	1			T4	1		T6	2		T12	1
auto[60:63]	auto[1]	295	1			T1	1		T5	2		T16	1
auto[64:67]	auto[0]	86	1			T6	1		T12	1		T24	1
auto[64:67]	auto[1]	247	1			T1	1		T4	3		T6	1
auto[68:71]	auto[0]	84	1			T6	3		T13	1		T26	2
auto[68:71]	auto[1]	294	1			T1	2		T5	6		T12	1
auto[72:75]	auto[0]	89	1			T12	2		T25	2		T127	1
auto[72:75]	auto[1]	247	1			T13	1		T16	5		T31	1
auto[76:79]	auto[0]	77	1			T25	2		T26	1		T69	1
auto[76:79]	auto[1]	310	1			T1	1		T5	1		T24	2
auto[80:83]	auto[0]	88	1			T136	3		T25	4		T28	2
auto[80:83]	auto[1]	288	1			T1	2		T24	2		T13	1
auto[84:87]	auto[0]	88	1			T8	1		T12	1		T13	1
auto[84:87]	auto[1]	291	1			T1	2		T8	1		T24	2
auto[88:91]	auto[0]	606	1			T4	2		T6	5		T7	2
auto[88:91]	auto[1]	1605	1			T1	6		T5	15		T6	3
auto[92:95]	auto[0]	69	1			T26	1		T30	2		T44	1
auto[92:95]	auto[1]	292	1			T5	4		T6	1		T31	2
auto[96:99]	auto[0]	72	1			T11	1		T68	1		T28	1
auto[96:99]	auto[1]	282	1			T1	4		T5	3		T11	1
auto[100:103]	auto[0]	78	1			T12	2		T25	1		T135	1
auto[100:103]	auto[1]	270	1			T1	1		T5	5		T6	2
auto[104:107]	auto[0]	534	1			T6	5		T12	6		T24	1
auto[104:107]	auto[1]	1041	1			T1	2		T5	5		T6	5
auto[108:111]	auto[0]	104	1			T6	1		T25	4		T127	2
auto[108:111]	auto[1]	291	1			T5	5		T6	1		T13	5
auto[112:115]	auto[0]	90	1			T147	1		T25	3		T26	2
auto[112:115]	auto[1]	330	1			T5	3		T13	2		T16	1
auto[116:119]	auto[0]	93	1			T6	2		T24	1		T189	2
auto[116:119]	auto[1]	317	1			T1	1		T5	9		T13	2
auto[120:123]	auto[0]	95	1			T7	1		T8	1		T24	2
auto[120:123]	auto[1]	348	1			T5	4		T7	1		T8	1
auto[124:127]	auto[0]	57	1			T6	3		T7	1		T26	1
auto[124:127]	auto[1]	291	1			T5	8		T7	1		T13	3
auto[128:131]	auto[0]	67	1			T25	1		T26	1		T134	1
auto[128:131]	auto[1]	274	1			T1	1		T5	1		T13	6
auto[132:135]	auto[0]	87	1			T6	1		T12	3		T24	1
auto[132:135]	auto[1]	276	1			T1	7		T5	1		T13	2
auto[136:139]	auto[0]	87	1			T12	2		T25	3		T127	3
auto[136:139]	auto[1]	280	1			T1	2		T5	2		T6	1
auto[140:143]	auto[0]	101	1			T6	3		T139	3		T25	2
auto[140:143]	auto[1]	282	1			T5	5		T6	6		T13	6
auto[144:147]	auto[0]	90	1			T6	1		T12	3		T25	1
auto[144:147]	auto[1]	297	1			T5	3		T6	1		T12	1
auto[148:151]	auto[0]	88	1			T6	1		T12	1		T27	2
auto[148:151]	auto[1]	310	1			T1	1		T5	4		T6	2
auto[152:155]	auto[0]	67	1			T6	1		T12	2		T13	2
auto[152:155]	auto[1]	300	1			T1	2		T5	6		T12	2
auto[156:159]	auto[0]	554	1			T6	6		T8	1		T12	3
auto[156:159]	auto[1]	1620	1			T1	10		T5	17		T6	1
auto[160:163]	auto[0]	95	1			T29	2		T30	2		T153	1
auto[160:163]	auto[1]	300	1			T5	2		T31	3		T35	3
auto[164:167]	auto[0]	98	1			T6	2		T127	2		T28	1
auto[164:167]	auto[1]	274	1			T5	4		T6	3		T12	3
auto[168:171]	auto[0]	108	1			T6	1		T139	1		T127	1
auto[168:171]	auto[1]	308	1			T13	3		T16	1		T31	2
auto[172:175]	auto[0]	91	1			T25	1		T26	1		T127	1
auto[172:175]	auto[1]	270	1			T1	3		T5	2		T12	2
auto[176:179]	auto[0]	94	1			T68	1		T44	3		T37	2
auto[176:179]	auto[1]	272	1			T1	2		T5	8		T12	2
auto[180:183]	auto[0]	517	1			T11	1		T12	9		T24	2
auto[180:183]	auto[1]	1573	1			T1	12		T4	1		T5	13
auto[184:187]	auto[0]	597	1			T3	2		T6	8		T8	2
auto[184:187]	auto[1]	1022	1			T1	1		T3	2		T5	8
auto[188:191]	auto[0]	74	1			T25	6		T137	1		T28	2
auto[188:191]	auto[1]	287	1			T1	1		T5	4		T12	1
auto[192:195]	auto[0]	97	1			T6	1		T12	3		T24	1
auto[192:195]	auto[1]	292	1			T1	5		T5	3		T6	3
auto[196:199]	auto[0]	87	1			T6	4		T12	1		T25	1
auto[196:199]	auto[1]	287	1			T1	1		T5	6		T6	2
auto[200:203]	auto[0]	81	1			T4	2		T12	1		T25	1
auto[200:203]	auto[1]	297	1			T1	2		T5	3		T12	1
auto[204:207]	auto[0]	91	1			T24	2		T26	1		T28	2
auto[204:207]	auto[1]	324	1			T1	4		T5	2		T12	1
auto[208:211]	auto[0]	79	1			T12	2		T24	1		T25	2
auto[208:211]	auto[1]	299	1			T1	2		T5	4		T12	1
auto[212:215]	auto[0]	103	1			T25	1		T189	1		T67	1
auto[212:215]	auto[1]	285	1			T5	5		T6	2		T31	1
auto[216:219]	auto[0]	77	1			T25	1		T44	1		T219	1
auto[216:219]	auto[1]	307	1			T5	1		T6	2		T13	1
auto[220:223]	auto[0]	85	1			T8	1		T25	1		T189	2
auto[220:223]	auto[1]	285	1			T5	1		T6	1		T8	1
auto[224:227]	auto[0]	82	1			T4	1		T6	1		T25	2
auto[224:227]	auto[1]	292	1			T1	2		T5	7		T13	3
auto[228:231]	auto[0]	93	1			T12	3		T26	2		T28	1
auto[228:231]	auto[1]	301	1			T1	1		T5	5		T6	1
auto[232:235]	auto[0]	958	1			T6	10		T12	3		T27	1
auto[232:235]	auto[1]	2296	1			T1	13		T4	2		T5	14
auto[236:239]	auto[0]	83	1			T6	5		T25	1		T28	1
auto[236:239]	auto[1]	270	1			T1	2		T5	2		T6	2
auto[240:243]	auto[0]	87	1			T26	4		T189	1		T30	3
auto[240:243]	auto[1]	294	1			T1	4		T12	1		T13	2
auto[244:247]	auto[0]	87	1			T24	1		T13	5		T28	1
auto[244:247]	auto[1]	316	1			T1	1		T5	2		T13	5
auto[248:251]	auto[0]	87	1			T4	1		T6	4		T11	1
auto[248:251]	auto[1]	339	1			T1	1		T5	1		T11	1
auto[252:255]	auto[0]	96	1			T24	2		T28	4		T44	1
auto[252:255]	auto[1]	289	1			T1	1		T5	4		T12	1