Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	497	1			T4	1		T6	4		T12	5
auto[ReadAddrCrossIntoMailbox]	338	1			T4	1		T6	4		T12	1
auto[ReadAddrCrossOutOfMailbox]	368	1			T6	2		T12	4		T24	2
auto[ReadAddrCrossAllMailbox]	274	1			T4	1		T6	2		T12	4
auto[ReadAddrOutsideMailbox]	3985	1			T3	4		T6	25		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2797

1

T3

2

T4

1

T6

18

auto[1]

2665

1

T3

2

T4

2

T6

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	856	1			T6	6		T8	4		T11	8
read_ops[0x0b]	941	1			T6	6		T7	2		T12	12
read_ops[0x3b]	919	1			T4	1		T6	3		T11	4
read_ops[0x6b]	910	1			T6	10		T12	7		T24	2
read_ops[0xbb]	955	1			T3	4		T6	6		T8	4
read_ops[0xeb]	881	1			T4	2		T6	6		T12	11

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T193	1		T44	1		T50	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T193	1		T44	2		T50	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T6	1		T12	1		T68	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T25	1		T26	2		T159	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T25	2		T26	1		T153	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T44	1		T50	1		T159	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T138	1		T150	1		T157	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T12	1		T28	1		T30	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T6	2		T8	2		T11	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T6	3		T8	2		T11	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T6	1		T12	1		T151	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T12	1		T151	1		T25	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T50	1		T170	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T24	1		T50	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T25	1		T138	1		T170	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T13	1		T25	1		T26	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	33	1			T12	1		T168	1		T68	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T168	1		T28	1		T152	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T6	2		T7	1		T12	7
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T6	3		T7	1		T12	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T4	1		T26	2		T168	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T6	1		T168	1		T28	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T6	1		T168	1		T153	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T168	1		T28	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T6	1		T24	1		T25	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T153	1		T170	2		T157	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T25	1		T168	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T25	1		T168	1		T30	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T11	2		T12	3		T24	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	352	1			T11	2		T12	2		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T12	2		T151	1		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T136	1		T151	1		T138	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	38	1			T6	1		T138	1		T152	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T6	1		T26	1		T150	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T12	1		T24	1		T25	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T6	1		T153	1		T138	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T25	1		T28	3		T159	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T220	1		T157	2		T197	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T6	4		T12	1		T13	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T6	3		T12	3		T24	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T12	1		T30	1		T50	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T6	2		T28	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T24	1		T28	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T127	1		T30	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T127	1		T37	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T25	1		T44	1		T128	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T24	1		T138	1		T152	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T6	2		T26	3		T153	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	374	1			T3	2		T6	2		T8	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T3	2		T8	2		T13	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T28	2		T164	1		T170	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T30	1		T153	1		T128	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T28	1		T30	2		T128	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T4	1		T136	1		T138	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T12	1		T127	1		T28	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T12	2		T13	1		T153	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T173	3		T127	1		T153	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	30	1			T4	1		T12	2		T173	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	319	1			T6	3		T12	1		T27	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T6	3		T12	5		T27	1