Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[1]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[2]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[3]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[4]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[5]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[6]	7674346	1			T1	14115		T2	4703		T3	1
all_pins[7]	7674346	1			T1	14115		T2	4703		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	61177423	1			T1	112920		T2	37624		T3	8
values[0x1]	217345	1			T6	14		T13	26		T52	21
transitions[0x0=>0x1]	213342	1			T6	12		T13	21		T52	11
transitions[0x1=>0x0]	213355	1			T6	12		T13	21		T52	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	7672232	1			T1	14115		T2	4703		T3	1
all_pins[0]	values[0x1]	2114	1			T6	1		T13	3		T52	3
all_pins[0]	transitions[0x0=>0x1]	1308	1			T6	1		T13	3		T52	1
all_pins[0]	transitions[0x1=>0x0]	236	1			T6	1		T13	2		T52	2
all_pins[1]	values[0x0]	7673304	1			T1	14115		T2	4703		T3	1
all_pins[1]	values[0x1]	1042	1			T6	1		T13	2		T52	4
all_pins[1]	transitions[0x0=>0x1]	879	1			T13	1		T52	1		T56	1
all_pins[1]	transitions[0x1=>0x0]	211	1			T6	1		T13	4		T56	3
all_pins[2]	values[0x0]	7673972	1			T1	14115		T2	4703		T3	1
all_pins[2]	values[0x1]	374	1			T6	2		T13	5		T52	3
all_pins[2]	transitions[0x0=>0x1]	328	1			T6	2		T13	4		T52	3
all_pins[2]	transitions[0x1=>0x0]	156	1			T6	1		T13	2		T52	1
all_pins[3]	values[0x0]	7674144	1			T1	14115		T2	4703		T3	1
all_pins[3]	values[0x1]	202	1			T6	1		T13	3		T52	1
all_pins[3]	transitions[0x0=>0x1]	152	1			T6	1		T52	1		T56	2
all_pins[3]	transitions[0x1=>0x0]	137	1			T6	3		T13	3		T52	1
all_pins[4]	values[0x0]	7674159	1			T1	14115		T2	4703		T3	1
all_pins[4]	values[0x1]	187	1			T6	3		T13	6		T52	1
all_pins[4]	transitions[0x0=>0x1]	147	1			T6	2		T13	6		T52	1
all_pins[4]	transitions[0x1=>0x0]	3539	1			T6	3		T13	2		T52	3
all_pins[5]	values[0x0]	7670767	1			T1	14115		T2	4703		T3	1
all_pins[5]	values[0x1]	3579	1			T6	4		T13	2		T52	3
all_pins[5]	transitions[0x0=>0x1]	807	1			T6	4		T13	2		T52	2
all_pins[5]	transitions[0x1=>0x0]	206873	1			T13	5		T52	2		T56	3
all_pins[6]	values[0x0]	7464701	1			T1	14115		T2	4703		T3	1
all_pins[6]	values[0x1]	209645	1			T13	5		T52	3		T56	3
all_pins[6]	transitions[0x0=>0x1]	209586	1			T13	5		T56	2		T127	2
all_pins[6]	transitions[0x1=>0x0]	143	1			T6	2		T56	2		T127	5
all_pins[7]	values[0x0]	7674144	1			T1	14115		T2	4703		T3	1
all_pins[7]	values[0x1]	202	1			T6	2		T52	3		T56	3
all_pins[7]	transitions[0x0=>0x1]	135	1			T6	2		T52	2		T56	1
all_pins[7]	transitions[0x1=>0x0]	2060	1			T6	1		T13	3		T52	2