Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4469	1			T6	49		T8	22		T12	95
values[1]	4351	1			T4	20		T10	6		T12	25
values[2]	3646	1			T12	21		T25	31		T26	20
values[3]	4048	1			T6	45		T12	25		T13	20
values[4]	3932	1			T6	48		T11	24		T12	48
values[5]	3754	1			T6	100		T12	64		T24	49
values[6]	3613	1			T3	6		T6	28		T12	20
values[7]	4607	1			T7	26		T12	20		T24	101

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4384	1			T12	65		T13	20		T25	76
values[1]	3587	1			T6	100		T24	20		T26	20
values[2]	3824	1			T6	82		T12	28		T27	12
values[3]	4084	1			T24	81		T206	4		T173	14
values[4]	4525	1			T6	68		T11	24		T12	101
values[5]	4066	1			T3	6		T6	20		T7	26
values[6]	3794	1			T12	46		T136	20		T82	6
values[7]	4156	1			T4	20		T10	6		T12	78

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31848

1

T3

6

T4

20

T6

262

auto[1]

572

1

T6

8

T7

4

T11

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	312	1			T25	20		T169	12		T138	40
auto[0]	values[0]	values[1]	441	1			T30	20		T44	18		T138	40
auto[0]	values[0]	values[2]	499	1			T6	27		T12	27		T25	20
auto[0]	values[0]	values[3]	422	1			T152	22		T150	20		T208	20
auto[0]	values[0]	values[4]	597	1			T6	18		T12	36		T44	51
auto[0]	values[0]	values[5]	833	1			T8	22		T147	26		T28	25
auto[0]	values[0]	values[6]	306	1			T134	40		T30	21		T162	20
auto[0]	values[0]	values[7]	989	1			T12	30		T25	70		T155	20
auto[0]	values[1]	values[0]	542	1			T12	24		T138	19		T128	94
auto[0]	values[1]	values[1]	357	1			T196	24		T44	19		T164	20
auto[0]	values[1]	values[2]	815	1			T148	6		T151	12		T189	28
auto[0]	values[1]	values[3]	499	1			T28	42		T138	21		T128	29
auto[0]	values[1]	values[4]	504	1			T192	6		T68	20		T30	18
auto[0]	values[1]	values[5]	533	1			T214	8		T170	20		T220	30
auto[0]	values[1]	values[6]	661	1			T68	20		T157	68		T213	26
auto[0]	values[1]	values[7]	360	1			T4	20		T10	6		T25	66
auto[0]	values[2]	values[0]	507	1			T44	20		T150	95		T221	2
auto[0]	values[2]	values[1]	283	1			T159	19		T138	20		T150	20
auto[0]	values[2]	values[2]	469	1			T26	19		T127	20		T30	24
auto[0]	values[2]	values[3]	305	1			T30	21		T44	20		T222	16
auto[0]	values[2]	values[4]	529	1			T30	44		T128	161		T207	16
auto[0]	values[2]	values[5]	532	1			T152	16		T167	14		T18	29
auto[0]	values[2]	values[6]	549	1			T12	21		T28	20		T30	20
auto[0]	values[2]	values[7]	413	1			T25	31		T219	14		T150	42
auto[0]	values[3]	values[0]	591	1			T193	6		T28	23		T164	22
auto[0]	values[3]	values[1]	344	1			T6	20		T223	26		T152	19
auto[0]	values[3]	values[2]	504	1			T6	24		T26	47		T30	20
auto[0]	values[3]	values[3]	487	1			T26	20		T28	20		T44	30
auto[0]	values[3]	values[4]	579	1			T25	58		T26	20		T69	10
auto[0]	values[3]	values[5]	439	1			T13	20		T25	20		T26	20
auto[0]	values[3]	values[6]	463	1			T12	22		T25	70		T30	20
auto[0]	values[3]	values[7]	563	1			T28	18		T44	29		T138	20
auto[0]	values[4]	values[0]	544	1			T25	55		T191	18		T153	20
auto[0]	values[4]	values[1]	613	1			T26	20		T204	8		T152	113
auto[0]	values[4]	values[2]	255	1			T27	10		T25	26		T63	2
auto[0]	values[4]	values[3]	582	1			T128	19		T170	20		T224	8
auto[0]	values[4]	values[4]	567	1			T6	48		T11	18		T28	19
auto[0]	values[4]	values[5]	369	1			T28	40		T37	22		T182	12
auto[0]	values[4]	values[6]	464	1			T82	6		T28	20		T37	40
auto[0]	values[4]	values[7]	465	1			T12	46		T150	20		T184	8
auto[0]	values[5]	values[0]	612	1			T183	20		T225	28		T157	28
auto[0]	values[5]	values[1]	399	1			T6	77		T28	20		T30	49
auto[0]	values[5]	values[2]	288	1			T226	16		T157	29		T227	23
auto[0]	values[5]	values[3]	608	1			T206	4		T25	54		T67	14
auto[0]	values[5]	values[4]	554	1			T12	64		T44	20		T128	19
auto[0]	values[5]	values[5]	406	1			T6	20		T127	20		T153	20
auto[0]	values[5]	values[6]	499	1			T136	20		T127	33		T28	22
auto[0]	values[5]	values[7]	325	1			T24	49		T152	20		T150	20
auto[0]	values[6]	values[0]	624	1			T12	20		T28	40		T30	22
auto[0]	values[6]	values[1]	393	1			T44	21		T164	20		T202	57
auto[0]	values[6]	values[2]	350	1			T6	28		T127	22		T170	19
auto[0]	values[6]	values[3]	421	1			T173	14		T137	10		T127	21
auto[0]	values[6]	values[4]	584	1			T25	88		T166	4		T157	24
auto[0]	values[6]	values[5]	280	1			T3	6		T153	23		T157	73
auto[0]	values[6]	values[6]	487	1			T25	48		T194	22		T152	129
auto[0]	values[6]	values[7]	411	1			T139	28		T44	62		T152	26
auto[0]	values[7]	values[0]	583	1			T12	20		T13	20		T188	6
auto[0]	values[7]	values[1]	682	1			T24	20		T30	20		T138	18
auto[0]	values[7]	values[2]	574	1			T127	20		T30	33		T159	52
auto[0]	values[7]	values[3]	705	1			T24	81		T68	36		T28	21
auto[0]	values[7]	values[4]	544	1			T28	42		T37	20		T152	20
auto[0]	values[7]	values[5]	603	1			T7	22		T160	16		T135	14
auto[0]	values[7]	values[6]	287	1			T170	24		T150	20		T18	20
auto[0]	values[7]	values[7]	543	1			T13	21		T30	23		T44	29
auto[1]	values[0]	values[0]	2	1			T138	1		T228	1		-	-
auto[1]	values[0]	values[1]	8	1			T44	2		T216	3		T229	1
auto[1]	values[0]	values[2]	12	1			T6	2		T12	1		T153	4
auto[1]	values[0]	values[3]	10	1			T208	1		T230	2		T19	1
auto[1]	values[0]	values[4]	6	1			T6	2		T12	1		T44	2
auto[1]	values[0]	values[5]	8	1			T28	2		T153	2		T231	4
auto[1]	values[0]	values[6]	8	1			T162	2		T217	1		T232	1
auto[1]	values[0]	values[7]	16	1			T18	2		T218	2		T19	3
auto[1]	values[1]	values[0]	10	1			T12	1		T138	2		T202	3
auto[1]	values[1]	values[1]	2	1			T44	1		T157	1		-	-
auto[1]	values[1]	values[2]	16	1			T157	2		T18	3		T156	1
auto[1]	values[1]	values[3]	4	1			T138	1		T128	1		T171	2
auto[1]	values[1]	values[4]	14	1			T30	2		T170	3		T233	4
auto[1]	values[1]	values[5]	12	1			T19	1		T234	2		T235	2
auto[1]	values[1]	values[6]	9	1			T213	1		T233	2		T236	3
auto[1]	values[1]	values[7]	13	1			T25	3		T30	2		T152	1
auto[1]	values[2]	values[0]	9	1			T150	2		T171	1		T237	1
auto[1]	values[2]	values[1]	6	1			T159	1		T228	1		T238	1
auto[1]	values[2]	values[2]	13	1			T26	1		T138	2		T239	1
auto[1]	values[2]	values[3]	3	1			T239	2		T240	1		-	-
auto[1]	values[2]	values[4]	5	1			T30	1		T128	1		T200	1
auto[1]	values[2]	values[5]	9	1			T152	4		T171	1		T241	2
auto[1]	values[2]	values[6]	8	1			T156	1		T242	2		T202	4
auto[1]	values[2]	values[7]	6	1			T150	2		T200	1		T175	1
auto[1]	values[3]	values[0]	6	1			T170	1		T150	2		T243	1
auto[1]	values[3]	values[1]	9	1			T152	1		T228	2		T240	2
auto[1]	values[3]	values[2]	8	1			T6	1		T26	1		T155	1
auto[1]	values[3]	values[3]	6	1			T242	2		T175	2		T228	1
auto[1]	values[3]	values[4]	9	1			T25	2		T44	1		T217	2
auto[1]	values[3]	values[5]	10	1			T159	3		T202	1		T216	1
auto[1]	values[3]	values[6]	16	1			T12	3		T25	1		T150	1
auto[1]	values[3]	values[7]	14	1			T28	2		T44	2		T152	1
auto[1]	values[4]	values[0]	9	1			T25	1		T138	1		T244	2
auto[1]	values[4]	values[1]	11	1			T170	1		T242	2		T234	2
auto[1]	values[4]	values[2]	4	1			T27	2		T216	1		T234	1
auto[1]	values[4]	values[3]	6	1			T128	1		T228	2		T239	1
auto[1]	values[4]	values[4]	10	1			T11	6		T28	1		T245	2
auto[1]	values[4]	values[5]	13	1			T37	1		T162	1		T246	2
auto[1]	values[4]	values[6]	10	1			T156	2		T244	2		T176	6
auto[1]	values[4]	values[7]	10	1			T12	2		T197	7		T247	1
auto[1]	values[5]	values[0]	11	1			T156	1		T200	1		T242	2
auto[1]	values[5]	values[1]	14	1			T6	3		T30	1		T19	3
auto[1]	values[5]	values[2]	1	1			T213	1		-	-		-	-
auto[1]	values[5]	values[3]	13	1			T156	1		T175	2		T216	1
auto[1]	values[5]	values[4]	6	1			T128	1		T152	1		T150	1
auto[1]	values[5]	values[5]	6	1			T195	2		T20	1		T248	1
auto[1]	values[5]	values[6]	5	1			T200	1		T234	4		-	-
auto[1]	values[5]	values[7]	7	1			T228	2		T249	2		T250	3
auto[1]	values[6]	values[0]	10	1			T28	3		T30	1		T238	3
auto[1]	values[6]	values[1]	12	1			T164	1		T228	1		T217	1
auto[1]	values[6]	values[2]	8	1			T170	1		T19	3		T246	1
auto[1]	values[6]	values[3]	2	1			T251	2		-	-		-	-
auto[1]	values[6]	values[4]	11	1			T25	1		T19	1		T232	2
auto[1]	values[6]	values[5]	2	1			T157	1		T238	1		-	-
auto[1]	values[6]	values[6]	16	1			T25	3		T152	1		T150	1
auto[1]	values[6]	values[7]	2	1			T44	2		-	-		-	-
auto[1]	values[7]	values[0]	12	1			T29	4		T246	5		T216	1
auto[1]	values[7]	values[1]	13	1			T138	2		T197	1		T19	5
auto[1]	values[7]	values[2]	8	1			T152	2		T216	2		T252	1
auto[1]	values[7]	values[3]	11	1			T28	1		T18	1		T228	1
auto[1]	values[7]	values[4]	6	1			T242	3		T253	3		-	-
auto[1]	values[7]	values[5]	11	1			T7	4		T157	2		T254	2
auto[1]	values[7]	values[6]	6	1			T200	1		T237	2		T176	1
auto[1]	values[7]	values[7]	19	1			T13	2		T44	1		T215	8