SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 159 | 1 | T32 | 1 | T118 | 2 | T120 | 5 | ||||
auto[1] | 133 | 1 | T32 | 1 | T118 | 1 | T120 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 34 | 1 | T121 | 4 | T124 | 1 | T255 | 1 | ||||
read_ops[0x0b] | 51 | 1 | T123 | 2 | T124 | 2 | T125 | 4 | ||||
read_ops[0x3b] | 35 | 1 | T118 | 3 | T256 | 1 | T257 | 2 | ||||
read_ops[0x6b] | 66 | 1 | T120 | 4 | T121 | 1 | T124 | 6 | ||||
read_ops[0xbb] | 47 | 1 | T120 | 5 | T124 | 2 | T257 | 2 | ||||
read_ops[0xeb] | 59 | 1 | T32 | 2 | T121 | 3 | T124 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |