Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2820

1

T1

12

T2

10

T4

11

auto[1]

2702

1

T1

7

T2

8

T4

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2859

1

T1

15

T2

18

T4

18

auto[1]

2663

1

T1

4

T4

3

T5

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4454

1

T1

13

T2

12

T4

14

auto[1]

1068

1

T1

6

T2

6

T4

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	1097	1			T1	3		T2	4		T4	4
valid[1]	1121	1			T1	5		T2	2		T4	5
valid[2]	1081	1			T1	2		T2	4		T4	5
valid[3]	1171	1			T1	4		T2	5		T4	3
valid[4]	1052	1			T1	5		T2	3		T4	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	174	1			T1	2		T2	2		T4	1
auto[0]	auto[0]	valid[0]	auto[1]	275	1			T4	1		T5	2		T14	2
auto[0]	auto[0]	valid[1]	auto[0]	166	1			T2	1		T4	1		T5	1
auto[0]	auto[0]	valid[1]	auto[1]	258	1			T1	1		T5	2		T13	2
auto[0]	auto[0]	valid[2]	auto[0]	204	1			T2	2		T4	3		T12	1
auto[0]	auto[0]	valid[2]	auto[1]	263	1			T1	1		T13	2		T14	1
auto[0]	auto[0]	valid[3]	auto[0]	189	1			T2	1		T4	1		T5	1
auto[0]	auto[0]	valid[3]	auto[1]	290	1			T13	1		T15	7		T80	2
auto[0]	auto[0]	valid[4]	auto[0]	162	1			T1	2		T4	1		T5	1
auto[0]	auto[0]	valid[4]	auto[1]	272	1			T1	1		T13	1		T15	11
auto[0]	auto[1]	valid[0]	auto[0]	168	1			T2	1		T4	1		T12	2
auto[0]	auto[1]	valid[0]	auto[1]	280	1			T1	1		T5	2		T13	3
auto[0]	auto[1]	valid[1]	auto[0]	176	1			T1	2		T4	1		T6	1
auto[0]	auto[1]	valid[1]	auto[1]	280	1			T13	2		T14	2		T15	6
auto[0]	auto[1]	valid[2]	auto[0]	174	1			T2	1		T6	1		T13	2
auto[0]	auto[1]	valid[2]	auto[1]	246	1			T4	1		T14	1		T15	4
auto[0]	auto[1]	valid[3]	auto[0]	203	1			T1	3		T2	2		T5	1
auto[0]	auto[1]	valid[3]	auto[1]	255	1			T4	1		T5	1		T15	7
auto[0]	auto[1]	valid[4]	auto[0]	175	1			T2	2		T4	2		T5	2
auto[0]	auto[1]	valid[4]	auto[1]	244	1			T5	2		T13	1		T15	5
auto[1]	auto[0]	valid[0]	auto[0]	115	1			T4	1		T5	1		T13	2
auto[1]	auto[0]	valid[1]	auto[0]	133	1			T1	2		T2	1		T4	1
auto[1]	auto[0]	valid[2]	auto[0]	104	1			T1	1		T2	1		T4	1
auto[1]	auto[0]	valid[3]	auto[0]	116	1			T1	1		T2	1		T5	1
auto[1]	auto[0]	valid[4]	auto[0]	99	1			T1	1		T2	1		T5	2
auto[1]	auto[1]	valid[0]	auto[0]	85	1			T2	1		T6	1		T14	1
auto[1]	auto[1]	valid[1]	auto[0]	108	1			T4	2		T5	1		T12	1
auto[1]	auto[1]	valid[2]	auto[0]	90	1			T6	1		T13	1		T66	2
auto[1]	auto[1]	valid[3]	auto[0]	118	1			T2	1		T4	1		T5	2
auto[1]	auto[1]	valid[4]	auto[0]	100	1			T1	1		T4	1		T5	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal