Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75850

1

T1

438

T2

624

T4

457

auto[1]

28978

1

T1

72

T4

43

T5

111

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76837

1

T1

330

T2

441

T4

332

auto[1]

27991

1

T1

180

T2

183

T4

168

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	54169	1			T1	285		T2	329		T4	256
others[1]	8833	1			T1	34		T2	51		T4	40
others[2]	8549	1			T1	38		T2	56		T4	44
others[3]	10003	1			T1	49		T2	58		T4	45
interest[1]	5776	1			T1	30		T2	30		T4	27
interest[4]	35326	1			T1	181		T2	218		T4	170
interest[64]	17498	1			T1	74		T2	100		T4	88

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	24616	1			T1	139		T2	237		T4	147
auto[0]	auto[0]	others[1]	4053	1			T1	19		T2	35		T4	25
auto[0]	auto[0]	others[2]	3908	1			T1	19		T2	39		T4	28
auto[0]	auto[0]	others[3]	4511	1			T1	29		T2	37		T4	20
auto[0]	auto[0]	interest[1]	2686	1			T1	13		T2	22		T4	16
auto[0]	auto[0]	interest[4]	15983	1			T1	89		T2	157		T4	100
auto[0]	auto[0]	interest[64]	8085	1			T1	39		T2	71		T4	53
auto[0]	auto[1]	others[0]	15140	1			T1	43		T4	22		T5	61
auto[0]	auto[1]	others[1]	2373	1			T1	1		T4	3		T5	4
auto[0]	auto[1]	others[2]	2372	1			T1	4		T4	2		T5	8
auto[0]	auto[1]	others[3]	2850	1			T1	6		T4	7		T5	12
auto[0]	auto[1]	interest[1]	1517	1			T1	5		T4	3		T5	6
auto[0]	auto[1]	interest[4]	10039	1			T1	34		T4	13		T5	36
auto[0]	auto[1]	interest[64]	4726	1			T1	13		T4	6		T5	20
auto[1]	auto[0]	others[0]	14413	1			T1	103		T2	92		T4	87
auto[1]	auto[0]	others[1]	2407	1			T1	14		T2	16		T4	12
auto[1]	auto[0]	others[2]	2269	1			T1	15		T2	17		T4	14
auto[1]	auto[0]	others[3]	2642	1			T1	14		T2	21		T4	18
auto[1]	auto[0]	interest[1]	1573	1			T1	12		T2	8		T4	8
auto[1]	auto[0]	interest[4]	9304	1			T1	58		T2	61		T4	57
auto[1]	auto[0]	interest[64]	4687	1			T1	22		T2	29		T4	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal