Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	855	1			T6	10		T13	14		T52	8
all_values[1]	855	1			T6	10		T13	14		T52	8
all_values[2]	855	1			T6	10		T13	14		T52	8
all_values[3]	855	1			T6	10		T13	14		T52	8
all_values[4]	855	1			T6	10		T13	14		T52	8
all_values[5]	855	1			T6	10		T13	14		T52	8
all_values[6]	855	1			T6	10		T13	14		T52	8
all_values[7]	855	1			T6	10		T13	14		T52	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3620

1

T6

50

T13

65

T52

27

auto[1]

3220

1

T6

30

T13

47

T52

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2836

1

T6

29

T13

44

T52

23

auto[1]

4004

1

T6

51

T13

68

T52

41

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3980

1

T6

41

T13

67

T52

37

auto[1]

2860

1

T6

39

T13

45

T52

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T13	5		T56	6		T127	5
all_values[0]	auto[0]	auto[0]	auto[1]	91	1			T6	1		T13	1		T52	1
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T6	4		T13	1		T52	2
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T6	1		T13	1		T52	2
all_values[0]	auto[1]	auto[0]	auto[1]	181	1			T6	1		T13	5		T52	2
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T6	3		T13	1		T52	1
all_values[1]	auto[0]	auto[0]	auto[0]	186	1			T6	3		T13	4		T52	1
all_values[1]	auto[0]	auto[0]	auto[1]	89	1			T6	1		T13	2		T52	1
all_values[1]	auto[0]	auto[1]	auto[0]	147	1			T13	1		T127	4		T133	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T52	2		T56	1		T127	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T6	4		T13	2		T52	2
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T6	2		T13	5		T52	2
all_values[2]	auto[0]	auto[0]	auto[0]	209	1			T6	5		T13	3		T52	1
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T13	1		T28	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T13	2		T52	2		T56	4
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T13	2		T52	1
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T6	2		T13	3		T52	1
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T6	1		T13	3		T52	3
all_values[3]	auto[0]	auto[0]	auto[0]	184	1			T6	2		T13	1		T52	2
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T6	1		T13	3		T52	2
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T6	1		T13	2		T127	6
all_values[3]	auto[0]	auto[1]	auto[1]	94	1			T13	2		T52	1		T56	1
all_values[3]	auto[1]	auto[0]	auto[1]	188	1			T6	4		T13	4		T52	3
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T6	2		T13	2		T56	2
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T6	1		T13	2		T52	3
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T6	1		T13	1		T56	2
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T6	1		T13	2		T52	2
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T6	1		T13	3		T127	2
all_values[4]	auto[1]	auto[0]	auto[1]	211	1			T6	6		T13	5		T56	4
all_values[4]	auto[1]	auto[1]	auto[1]	153	1			T13	1		T52	3		T56	1
all_values[5]	auto[0]	auto[0]	auto[0]	236	1			T6	1		T13	2		T52	1
all_values[5]	auto[0]	auto[1]	auto[0]	261	1			T6	2		T13	8		T52	4
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T6	2		T13	4		T56	2
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T6	5		T52	3		T127	3
all_values[6]	auto[0]	auto[0]	auto[0]	199	1			T6	3		T13	2		T52	3
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T6	3		T13	3		T56	1
all_values[6]	auto[0]	auto[1]	auto[0]	150	1			T6	2		T13	1		T56	3
all_values[6]	auto[0]	auto[1]	auto[1]	89	1			T13	2		T52	2		T56	1
all_values[6]	auto[1]	auto[0]	auto[1]	188	1			T6	2		T13	3		T52	1
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T13	3		T52	2		T56	3
all_values[7]	auto[0]	auto[0]	auto[0]	158	1			T6	3		T13	5		T56	3
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T13	2		T52	1		T127	1
all_values[7]	auto[0]	auto[1]	auto[0]	171	1			T6	1		T13	3		T52	2
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T6	1		T52	1		T56	1
all_values[7]	auto[1]	auto[0]	auto[1]	189	1			T6	3		T13	2		T52	2
all_values[7]	auto[1]	auto[1]	auto[1]	193	1			T6	2		T13	2		T52	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal