Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1412135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1533225

1

T1

6551

T2

1017

T3

4694

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2257359	1			T1	7055		T2	238		T3	7720
values[0x0]	342359	1			T1	3210		T2	444		T3	432
values[0x1]	345642	1			T1	3134		T2	449		T3	461

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1063454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1881906

1

T1

8541

T2

1035

T3

5454

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8224	1			T1	1		T2	9		T4	4
valid_sources[0x01]	14918	1			T2	3		T4	4		T6	10
valid_sources[0x02]	14410	1			T2	10		T6	9		T7	18
valid_sources[0x03]	16990	1			T1	6		T2	4		T4	4
valid_sources[0x04]	9180	1			T2	1		T4	3		T6	3
valid_sources[0x05]	7720	1			T1	3		T2	4		T4	1
valid_sources[0x06]	9135	1			T2	1		T6	5		T7	14
valid_sources[0x07]	9671	1			T2	7		T4	7		T6	11
valid_sources[0x08]	22743	1			T2	4		T4	6		T6	2
valid_sources[0x09]	11341	1			T1	73		T2	1		T4	3
valid_sources[0x0a]	11044	1			T1	79		T2	2		T4	8
valid_sources[0x0b]	9523	1			T2	7		T4	1		T6	2
valid_sources[0x0c]	8957	1			T1	11		T2	6		T4	1
valid_sources[0x0d]	9402	1			T4	12		T14	1		T7	20
valid_sources[0x0e]	10658	1			T2	9		T4	5		T7	9
valid_sources[0x0f]	8870	1			T1	288		T2	2		T4	3
valid_sources[0x10]	12325	1			T1	4		T2	6		T4	3
valid_sources[0x11]	13352	1			T2	6		T4	2		T7	13
valid_sources[0x12]	13287	1			T2	1		T4	4		T14	1
valid_sources[0x13]	9337	1			T2	5		T4	5		T6	3
valid_sources[0x14]	8380	1			T1	60		T2	5		T4	5
valid_sources[0x15]	9305	1			T1	3		T2	5		T4	16
valid_sources[0x16]	9121	1			T1	54		T2	7		T4	1
valid_sources[0x17]	13260	1			T4	6		T6	3		T7	14
valid_sources[0x18]	9305	1			T2	7		T4	3		T6	7
valid_sources[0x19]	13791	1			T1	1		T2	10		T4	4
valid_sources[0x1a]	12981	1			T2	2		T4	5		T6	1
valid_sources[0x1b]	12938	1			T2	2		T4	3		T6	1
valid_sources[0x1c]	7990	1			T1	150		T2	2		T4	4
valid_sources[0x1d]	26402	1			T1	1		T2	3		T3	8613
valid_sources[0x1e]	9549	1			T1	5		T2	2		T4	6
valid_sources[0x1f]	10997	1			T2	6		T4	6		T14	2
valid_sources[0x20]	9775	1			T2	6		T4	2		T6	5
valid_sources[0x21]	9342	1			T1	1		T2	3		T4	2
valid_sources[0x22]	10416	1			T4	2		T6	1		T7	11
valid_sources[0x23]	10162	1			T1	13		T2	2		T4	7
valid_sources[0x24]	10820	1			T1	4		T2	5		T4	3
valid_sources[0x25]	9849	1			T2	6		T4	4		T6	10
valid_sources[0x26]	9067	1			T1	4		T2	5		T4	4
valid_sources[0x27]	10684	1			T1	2		T2	4		T4	3
valid_sources[0x28]	8875	1			T2	1		T4	4		T6	1
valid_sources[0x29]	11252	1			T2	4		T4	6		T6	5
valid_sources[0x2a]	10225	1			T1	142		T2	2		T4	4
valid_sources[0x2b]	9452	1			T1	2		T2	4		T4	5
valid_sources[0x2c]	13751	1			T2	4		T4	5		T14	1
valid_sources[0x2d]	9127	1			T1	40		T2	8		T4	2
valid_sources[0x2e]	8494	1			T1	101		T2	1		T4	2
valid_sources[0x2f]	10588	1			T1	201		T2	2		T4	2
valid_sources[0x30]	15333	1			T1	3		T2	4		T4	1
valid_sources[0x31]	8865	1			T1	2		T2	3		T4	2
valid_sources[0x32]	8874	1			T2	4		T4	3		T7	8
valid_sources[0x33]	11036	1			T1	8		T2	5		T4	3
valid_sources[0x34]	10221	1			T1	1		T2	3		T4	2
valid_sources[0x35]	25192	1			T1	356		T4	3		T6	3
valid_sources[0x36]	9492	1			T2	8		T4	2		T6	2
valid_sources[0x37]	8041	1			T2	7		T4	7		T6	8
valid_sources[0x38]	9723	1			T2	3		T4	2		T6	2
valid_sources[0x39]	15890	1			T1	1		T4	3		T6	9
valid_sources[0x3a]	9198	1			T2	6		T4	4		T14	4
valid_sources[0x3b]	10726	1			T2	8		T4	8		T14	1
valid_sources[0x3c]	8464	1			T2	2		T4	2		T14	1
valid_sources[0x3d]	9985	1			T1	4		T2	5		T4	3
valid_sources[0x3e]	29313	1			T2	2		T4	2		T7	9
valid_sources[0x3f]	14891	1			T1	5		T2	8		T6	6
valid_sources[0x40]	8328	1			T2	4		T4	1		T7	13
valid_sources[0x41]	8027	1			T1	10		T2	8		T4	1
valid_sources[0x42]	9042	1			T2	5		T4	1		T6	8
valid_sources[0x43]	8386	1			T1	38		T2	1		T4	2
valid_sources[0x44]	8623	1			T2	7		T4	4		T6	12
valid_sources[0x45]	8193	1			T1	13		T2	1		T4	2
valid_sources[0x46]	61338	1			T1	8		T2	4		T4	5
valid_sources[0x47]	11255	1			T2	6		T4	1		T6	5
valid_sources[0x48]	9740	1			T1	119		T2	3		T4	5
valid_sources[0x49]	9089	1			T1	6		T2	16		T4	2
valid_sources[0x4a]	10708	1			T1	1		T2	4		T4	1
valid_sources[0x4b]	8887	1			T2	10		T4	3		T6	1
valid_sources[0x4c]	9207	1			T1	3		T2	1		T4	3
valid_sources[0x4d]	35746	1			T1	4		T2	10		T4	8
valid_sources[0x4e]	10731	1			T2	3		T4	3		T6	2
valid_sources[0x4f]	11797	1			T2	4		T4	3		T6	5
valid_sources[0x50]	10177	1			T1	150		T2	2		T4	4
valid_sources[0x51]	9423	1			T1	8		T4	8		T6	8
valid_sources[0x52]	8174	1			T2	5		T4	1		T14	2
valid_sources[0x53]	9272	1			T1	1		T2	3		T4	6
valid_sources[0x54]	10003	1			T2	8		T4	2		T15	4
valid_sources[0x55]	13091	1			T1	53		T2	10		T4	2
valid_sources[0x56]	9404	1			T1	7		T2	3		T4	5
valid_sources[0x57]	11226	1			T1	99		T2	3		T4	4
valid_sources[0x58]	9279	1			T2	9		T4	6		T7	15
valid_sources[0x59]	10259	1			T2	4		T4	1		T6	2
valid_sources[0x5a]	10954	1			T1	20		T2	4		T4	1
valid_sources[0x5b]	8258	1			T2	4		T4	6		T7	12
valid_sources[0x5c]	9850	1			T1	2		T2	2		T4	5
valid_sources[0x5d]	9464	1			T1	652		T2	3		T4	3
valid_sources[0x5e]	9193	1			T1	1		T4	2		T7	11
valid_sources[0x5f]	9232	1			T1	596		T2	2		T4	2
valid_sources[0x60]	9448	1			T2	4		T4	4		T14	4
valid_sources[0x61]	13190	1			T1	3		T2	6		T4	3
valid_sources[0x62]	9633	1			T1	232		T4	6		T6	5
valid_sources[0x63]	8963	1			T1	197		T2	8		T4	3
valid_sources[0x64]	9129	1			T1	346		T2	4		T4	1
valid_sources[0x65]	8886	1			T2	3		T4	1		T7	11
valid_sources[0x66]	9175	1			T2	4		T4	2		T6	5
valid_sources[0x67]	8735	1			T1	3		T2	2		T4	4
valid_sources[0x68]	9903	1			T2	6		T4	4		T6	12
valid_sources[0x69]	10921	1			T1	275		T2	1		T4	6
valid_sources[0x6a]	9582	1			T1	44		T2	3		T4	8
valid_sources[0x6b]	10337	1			T2	4		T4	2		T6	4
valid_sources[0x6c]	11571	1			T2	2		T4	1		T6	2
valid_sources[0x6d]	8915	1			T2	1		T4	3		T6	15
valid_sources[0x6e]	9952	1			T1	2		T2	5		T4	11
valid_sources[0x6f]	10946	1			T1	3		T2	4		T4	2
valid_sources[0x70]	9301	1			T1	201		T2	11		T4	2
valid_sources[0x71]	7984	1			T1	2		T4	8		T6	6
valid_sources[0x72]	11427	1			T2	2		T4	4		T6	2
valid_sources[0x73]	9685	1			T2	10		T4	2		T14	2
valid_sources[0x74]	8077	1			T2	1		T6	2		T7	9
valid_sources[0x75]	9413	1			T1	529		T2	2		T7	17
valid_sources[0x76]	8909	1			T2	3		T4	2		T6	6
valid_sources[0x77]	8848	1			T1	3		T2	2		T4	2
valid_sources[0x78]	9350	1			T1	20		T2	5		T4	3
valid_sources[0x79]	9176	1			T1	3		T2	1		T4	4
valid_sources[0x7a]	11293	1			T1	277		T2	7		T4	2
valid_sources[0x7b]	16293	1			T2	2		T4	6		T6	6
valid_sources[0x7c]	8859	1			T1	4		T2	2		T4	3
valid_sources[0x7d]	21976	1			T2	7		T4	4		T14	1
valid_sources[0x7e]	8702	1			T1	1		T2	1		T4	3
valid_sources[0x7f]	10166	1			T1	570		T2	5		T4	6
valid_sources[0x80]	9056	1			T1	1		T2	9		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

912713

1

T1

1843

T2

128

T3

3816

values[0x0]

all_enables

biggest_size

312552

1

T1

2414

T2

443

T3

430

values[0x1]

all_enables

biggest_size

307960

1

T1

2294

T2

446

T3

448