Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1429264

1

T1

6848

T2

114

T3

3919

full_word

1532090

1

T1

6551

T2

1017

T3

4694

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2960934	1			T1	13399		T2	1131		T3	8613
auto[TlIntgErrCmd]	141	1			T36	13		T131	12		T132	11
auto[TlIntgErrData]	134	1			T36	8		T131	9		T132	9
auto[TlIntgErrBoth]	145	1			T36	9		T131	9		T132	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2258476

1

T1

7055

T2

238

T3

7720

auto[1]

702878

1

T1

6344

T2

893

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1345495	1			T1	5212		T2	110		T3	3904
auto[TlIntgErrNone]	partial	auto[1]	83377	1			T1	1636		T2	4		T3	15
auto[TlIntgErrNone]	full_word	auto[0]	912787	1			T1	1843		T2	128		T3	3816
auto[TlIntgErrNone]	full_word	auto[1]	619275	1			T1	4708		T2	889		T3	878
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T36	4		T131	4		T132	4
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T36	7		T131	7		T132	7
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T174	1		T378	1		T381	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T36	2		T131	1		T174	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T36	4		T131	3		T132	4
auto[TlIntgErrData]	partial	auto[1]	59	1			T36	4		T131	6		T132	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T132	1		T146	1		T382	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T146	1		T383	1		T382	2
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T36	6		T131	3		T132	3
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T36	3		T131	6		T132	7
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T380	1		T384	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T146	1		T385	1		T386	1