Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	100.00	70.37			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	55.51	86.36	44.44			60.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
55.51	86.36

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T1,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T13
1	0	Unreachable
1	1	Covered	T1,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
55.51	44.44

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	192269881	151316721	0	0
CheckNGreaterZero_A	2121	2121	0	0
GntImpliesReady_A	192269881	731485	0	0
GntImpliesValid_A	192269881	731485	0	0
GrantKnown_A	192269881	151316721	0	0
IdxKnown_A	192269881	151316721	0	0
IndexIsCorrect_A	192269881	731485	0	0
LockArbDecision_A	192269881	0	0	0
NoReadyValidNoGrant_A	192269881	0	0	0
ReadyAndValidImplyGrant_A	192269881	731485	0	0
ReqAndReadyImplyGrant_A	192269881	731485	0	0
ReqImpliesValid_A	192269881	731485	0	0
ReqStaysHighUntilGranted0_M	192269881	0	0	0
RoundRobin_A	192269881	0	0	707
ValidKnown_A	192269881	151316721	0	0
gen_data_port_assertion.DataFlow_A	192269881	731485	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	151316721	0	0
T1	833723	823902	0	0
T2	222441	187120	0	0
T3	225163	203173	0	0
T4	408126	246288	0	0
T5	100887	86680	0	0
T6	337160	189826	0	0
T7	90601	75977	0	0
T8	376250	186896	0	0
T9	8224	4112	0	0
T10	0	142536	0	0
T12	34204	29789	0	0
T13	435169	428608	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2121	2121	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T12	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	151316721	0	0
T1	833723	823902	0	0
T2	222441	187120	0	0
T3	225163	203173	0	0
T4	408126	246288	0	0
T5	100887	86680	0	0
T6	337160	189826	0	0
T7	90601	75977	0	0
T8	376250	186896	0	0
T9	8224	4112	0	0
T10	0	142536	0	0
T12	34204	29789	0	0
T13	435169	428608	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	151316721	0	0
T1	833723	823902	0	0
T2	222441	187120	0	0
T3	225163	203173	0	0
T4	408126	246288	0	0
T5	100887	86680	0	0
T6	337160	189826	0	0
T7	90601	75977	0	0
T8	376250	186896	0	0
T9	8224	4112	0	0
T10	0	142536	0	0
T12	34204	29789	0	0
T13	435169	428608	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	0	0	707

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	151316721	0	0
T1	833723	823902	0	0
T2	222441	187120	0	0
T3	225163	203173	0	0
T4	408126	246288	0	0
T5	100887	86680	0	0
T6	337160	189826	0	0
T7	90601	75977	0	0
T8	376250	186896	0	0
T9	8224	4112	0	0
T10	0	142536	0	0
T12	34204	29789	0	0
T13	435169	428608	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192269881	731485	0	0
T1	833723	12869	0	0
T2	187358	832	0	0
T3	203477	832	0	0
T4	246421	832	0	0
T5	86948	832	0	0
T6	190283	832	0	0
T7	76059	832	0	0
T8	188125	832	0	0
T9	4112	0	0	0
T12	30002	379	0	0
T13	0	6179	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	19	86.36
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	3	75.00
ALWAYS	124	4	3	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	0	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	1	50.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	40297255	25278180	0	0
CheckNGreaterZero_A	707	707	0	0
GntImpliesReady_A	40297255	0	0	0
GntImpliesValid_A	40297255	0	0	0
GrantKnown_A	40297255	25278180	0	0
IdxKnown_A	40297255	25278180	0	0
IndexIsCorrect_A	40297255	0	0	0
LockArbDecision_A	40297255	0	0	0
NoReadyValidNoGrant_A	40297255	0	0	0
ReadyAndValidImplyGrant_A	40297255	0	0	0
ReqAndReadyImplyGrant_A	40297255	0	0	0
ReqImpliesValid_A	40297255	0	0	0
ReqStaysHighUntilGranted0_M	40297255	0	0	0
RoundRobin_A	40297255	0	0	0
ValidKnown_A	40297255	25278180	0	0
gen_data_port_assertion.DataFlow_A	40297255	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	25278180	0	0
T2	35083	34936	0	0
T3	21686	21454	0	0
T4	161705	161632	0	0
T5	13939	13728	0	0
T6	146877	146500	0	0
T7	14542	14542	0	0
T8	188125	186896	0	0
T9	4112	4112	0	0
T10	0	142536	0	0
T11	0	26238	0	0
T12	4202	0	0	0
T13	435169	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707	707	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	25278180	0	0
T2	35083	34936	0	0
T3	21686	21454	0	0
T4	161705	161632	0	0
T5	13939	13728	0	0
T6	146877	146500	0	0
T7	14542	14542	0	0
T8	188125	186896	0	0
T9	4112	4112	0	0
T10	0	142536	0	0
T11	0	26238	0	0
T12	4202	0	0	0
T13	435169	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	25278180	0	0
T2	35083	34936	0	0
T3	21686	21454	0	0
T4	161705	161632	0	0
T5	13939	13728	0	0
T6	146877	146500	0	0
T7	14542	14542	0	0
T8	188125	186896	0	0
T9	4112	4112	0	0
T10	0	142536	0	0
T11	0	26238	0	0
T12	4202	0	0	0
T13	435169	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	25278180	0	0
T2	35083	34936	0	0
T3	21686	21454	0	0
T4	161705	161632	0	0
T5	13939	13728	0	0
T6	146877	146500	0	0
T7	14542	14542	0	0
T8	188125	186896	0	0
T9	4112	4112	0	0
T10	0	142536	0	0
T11	0	26238	0	0
T12	4202	0	0	0
T13	435169	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T13
1	0	Covered	T1,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T13
1	0	Unreachable
1	1	Covered	T1,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T12,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	40297255	14428059	0	0
CheckNGreaterZero_A	707	707	0	0
GntImpliesReady_A	40297255	249597	0	0
GntImpliesValid_A	40297255	249597	0	0
GrantKnown_A	40297255	14428059	0	0
IdxKnown_A	40297255	14428059	0	0
IndexIsCorrect_A	40297255	249597	0	0
LockArbDecision_A	40297255	0	0	0
NoReadyValidNoGrant_A	40297255	0	0	0
ReadyAndValidImplyGrant_A	40297255	249597	0	0
ReqAndReadyImplyGrant_A	40297255	249597	0	0
ReqImpliesValid_A	40297255	249597	0	0
ReqStaysHighUntilGranted0_M	40297255	0	0	0
RoundRobin_A	40297255	0	0	0
ValidKnown_A	40297255	14428059	0	0
gen_data_port_assertion.DataFlow_A	40297255	249597	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	14428059	0	0
T1	369349	359600	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	4040	0	0
T13	0	428608	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707	707	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	14428059	0	0
T1	369349	359600	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	4040	0	0
T13	0	428608	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	14428059	0	0
T1	369349	359600	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	4040	0	0
T13	0	428608	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	14428059	0	0
T1	369349	359600	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	4040	0	0
T13	0	428608	0	0
T19	0	288	0	0
T20	0	66648	0	0
T21	0	5544	0	0
T60	0	136552	0	0
T61	0	128776	0	0
T62	0	54296	0	0
T63	0	202072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40297255	249597	0	0
T1	369349	8746	0	0
T2	35083	0	0	0
T3	21686	0	0	0
T4	161705	0	0	0
T5	13939	0	0	0
T6	146877	0	0	0
T7	14542	0	0	0
T8	188125	0	0	0
T9	4112	0	0	0
T12	4202	273	0	0
T13	0	6179	0	0
T20	0	2511	0	0
T63	0	9162	0	0
T65	0	96	0	0
T66	0	4991	0	0
T67	0	43	0	0
T68	0	5971	0	0
T69	0	7243	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T12,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	111675371	111610482	0	0
CheckNGreaterZero_A	707	707	0	0
GntImpliesReady_A	111675371	481888	0	0
GntImpliesValid_A	111675371	481888	0	0
GrantKnown_A	111675371	111610482	0	0
IdxKnown_A	111675371	111610482	0	0
IndexIsCorrect_A	111675371	481888	0	0
LockArbDecision_A	111675371	0	0	0
NoReadyValidNoGrant_A	111675371	0	0	0
ReadyAndValidImplyGrant_A	111675371	481888	0	0
ReqAndReadyImplyGrant_A	111675371	481888	0	0
ReqImpliesValid_A	111675371	481888	0	0
ReqStaysHighUntilGranted0_M	111675371	0	0	0
RoundRobin_A	111675371	0	0	707
ValidKnown_A	111675371	111610482	0	0
gen_data_port_assertion.DataFlow_A	111675371	481888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	111610482	0	0
T1	464374	464302	0	0
T2	152275	152184	0	0
T3	181791	181719	0	0
T4	84716	84656	0	0
T5	73009	72952	0	0
T6	43406	43326	0	0
T7	61517	61435	0	0
T12	25800	25749	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707	707	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	111610482	0	0
T1	464374	464302	0	0
T2	152275	152184	0	0
T3	181791	181719	0	0
T4	84716	84656	0	0
T5	73009	72952	0	0
T6	43406	43326	0	0
T7	61517	61435	0	0
T12	25800	25749	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	111610482	0	0
T1	464374	464302	0	0
T2	152275	152184	0	0
T3	181791	181719	0	0
T4	84716	84656	0	0
T5	73009	72952	0	0
T6	43406	43326	0	0
T7	61517	61435	0	0
T12	25800	25749	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	0	0	707

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	111610482	0	0
T1	464374	464302	0	0
T2	152275	152184	0	0
T3	181791	181719	0	0
T4	84716	84656	0	0
T5	73009	72952	0	0
T6	43406	43326	0	0
T7	61517	61435	0	0
T12	25800	25749	0	0
T14	1278	1214	0	0
T15	1494	1443	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111675371	481888	0	0
T1	464374	4123	0	0
T2	152275	832	0	0
T3	181791	832	0	0
T4	84716	832	0	0
T5	73009	832	0	0
T6	43406	832	0	0
T7	61517	832	0	0
T8	0	832	0	0
T12	25800	106	0	0
T14	1278	0	0	0
T15	1494	0	0	0
T16	0	200	0	0