Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
3019 |
0 |
0 |
T36 |
96830 |
3 |
0 |
0 |
T125 |
3862 |
50 |
0 |
0 |
T126 |
2899 |
168 |
0 |
0 |
T127 |
2219 |
73 |
0 |
0 |
T131 |
108610 |
5 |
0 |
0 |
T132 |
29388 |
3 |
0 |
0 |
T133 |
6301 |
55 |
0 |
0 |
T134 |
6455 |
238 |
0 |
0 |
T139 |
8584 |
6 |
0 |
0 |
T145 |
4763 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2053 |
0 |
0 |
T36 |
96830 |
49 |
0 |
0 |
T131 |
108610 |
102 |
0 |
0 |
T154 |
119997 |
753 |
0 |
0 |
T155 |
180890 |
442 |
0 |
0 |
T171 |
34748 |
156 |
0 |
0 |
T172 |
10210 |
20 |
0 |
0 |
T173 |
5872 |
7 |
0 |
0 |
T174 |
33029 |
38 |
0 |
0 |
T175 |
13475 |
86 |
0 |
0 |
T176 |
8743 |
6 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2011 |
0 |
0 |
T36 |
96830 |
61 |
0 |
0 |
T131 |
108610 |
135 |
0 |
0 |
T154 |
119997 |
717 |
0 |
0 |
T155 |
180890 |
435 |
0 |
0 |
T171 |
34748 |
189 |
0 |
0 |
T172 |
10210 |
7 |
0 |
0 |
T173 |
5872 |
5 |
0 |
0 |
T174 |
33029 |
44 |
0 |
0 |
T175 |
13475 |
39 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2544 |
0 |
0 |
T36 |
96830 |
163 |
0 |
0 |
T131 |
108610 |
261 |
0 |
0 |
T154 |
119997 |
715 |
0 |
0 |
T155 |
180890 |
452 |
0 |
0 |
T171 |
34748 |
157 |
0 |
0 |
T172 |
10210 |
36 |
0 |
0 |
T173 |
5872 |
15 |
0 |
0 |
T174 |
33029 |
65 |
0 |
0 |
T175 |
13475 |
62 |
0 |
0 |
T176 |
8743 |
14 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
9646 |
0 |
0 |
T36 |
96830 |
1195 |
0 |
0 |
T131 |
108610 |
1916 |
0 |
0 |
T154 |
119997 |
699 |
0 |
0 |
T155 |
180890 |
418 |
0 |
0 |
T171 |
34748 |
151 |
0 |
0 |
T172 |
10210 |
122 |
0 |
0 |
T173 |
5872 |
158 |
0 |
0 |
T174 |
33029 |
666 |
0 |
0 |
T175 |
13475 |
26 |
0 |
0 |
T176 |
8743 |
118 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
9868 |
0 |
0 |
T36 |
96830 |
1206 |
0 |
0 |
T131 |
108610 |
1845 |
0 |
0 |
T154 |
119997 |
783 |
0 |
0 |
T155 |
180890 |
474 |
0 |
0 |
T171 |
34748 |
120 |
0 |
0 |
T172 |
10210 |
206 |
0 |
0 |
T173 |
5872 |
152 |
0 |
0 |
T174 |
33029 |
718 |
0 |
0 |
T175 |
13475 |
14 |
0 |
0 |
T176 |
8743 |
48 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
10240 |
0 |
0 |
T36 |
96830 |
1156 |
0 |
0 |
T131 |
108610 |
1458 |
0 |
0 |
T154 |
119997 |
760 |
0 |
0 |
T155 |
180890 |
472 |
0 |
0 |
T171 |
34748 |
150 |
0 |
0 |
T172 |
10210 |
245 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
802 |
0 |
0 |
T175 |
13475 |
40 |
0 |
0 |
T176 |
8743 |
86 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
9033 |
0 |
0 |
T36 |
96830 |
935 |
0 |
0 |
T131 |
108610 |
2302 |
0 |
0 |
T154 |
119997 |
761 |
0 |
0 |
T155 |
180890 |
428 |
0 |
0 |
T171 |
34748 |
129 |
0 |
0 |
T172 |
10210 |
14 |
0 |
0 |
T173 |
5872 |
110 |
0 |
0 |
T174 |
33029 |
527 |
0 |
0 |
T175 |
13475 |
60 |
0 |
0 |
T176 |
8743 |
42 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
10266 |
0 |
0 |
T36 |
96830 |
1365 |
0 |
0 |
T131 |
108610 |
1793 |
0 |
0 |
T154 |
119997 |
764 |
0 |
0 |
T155 |
180890 |
428 |
0 |
0 |
T171 |
34748 |
97 |
0 |
0 |
T172 |
10210 |
137 |
0 |
0 |
T173 |
5872 |
4 |
0 |
0 |
T174 |
33029 |
873 |
0 |
0 |
T175 |
13475 |
20 |
0 |
0 |
T176 |
8743 |
78 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
8221 |
0 |
0 |
T36 |
96830 |
666 |
0 |
0 |
T131 |
108610 |
1338 |
0 |
0 |
T154 |
119997 |
823 |
0 |
0 |
T155 |
180890 |
428 |
0 |
0 |
T171 |
34748 |
166 |
0 |
0 |
T172 |
10210 |
18 |
0 |
0 |
T173 |
5872 |
6 |
0 |
0 |
T174 |
33029 |
584 |
0 |
0 |
T175 |
13475 |
79 |
0 |
0 |
T176 |
8743 |
10 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
9126 |
0 |
0 |
T36 |
96830 |
735 |
0 |
0 |
T131 |
108610 |
1808 |
0 |
0 |
T154 |
119997 |
750 |
0 |
0 |
T155 |
180890 |
478 |
0 |
0 |
T171 |
34748 |
120 |
0 |
0 |
T172 |
10210 |
95 |
0 |
0 |
T173 |
5872 |
116 |
0 |
0 |
T174 |
33029 |
387 |
0 |
0 |
T175 |
13475 |
75 |
0 |
0 |
T176 |
8743 |
61 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
9931 |
0 |
0 |
T36 |
96830 |
820 |
0 |
0 |
T131 |
108610 |
2059 |
0 |
0 |
T154 |
119997 |
776 |
0 |
0 |
T155 |
180890 |
398 |
0 |
0 |
T171 |
34748 |
152 |
0 |
0 |
T172 |
10210 |
196 |
0 |
0 |
T173 |
5872 |
9 |
0 |
0 |
T174 |
33029 |
535 |
0 |
0 |
T175 |
13475 |
41 |
0 |
0 |
T176 |
8743 |
14 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5175 |
0 |
0 |
T36 |
96830 |
420 |
0 |
0 |
T131 |
108610 |
921 |
0 |
0 |
T154 |
119997 |
751 |
0 |
0 |
T155 |
180890 |
472 |
0 |
0 |
T171 |
34748 |
167 |
0 |
0 |
T172 |
10210 |
50 |
0 |
0 |
T173 |
5872 |
3 |
0 |
0 |
T174 |
33029 |
235 |
0 |
0 |
T175 |
13475 |
36 |
0 |
0 |
T176 |
8743 |
26 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5070 |
0 |
0 |
T36 |
96830 |
337 |
0 |
0 |
T131 |
108610 |
962 |
0 |
0 |
T154 |
119997 |
732 |
0 |
0 |
T155 |
180890 |
452 |
0 |
0 |
T171 |
34748 |
127 |
0 |
0 |
T172 |
10210 |
16 |
0 |
0 |
T173 |
5872 |
49 |
0 |
0 |
T174 |
33029 |
172 |
0 |
0 |
T175 |
13475 |
36 |
0 |
0 |
T176 |
8743 |
3 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4546 |
0 |
0 |
T36 |
96830 |
410 |
0 |
0 |
T131 |
108610 |
810 |
0 |
0 |
T154 |
119997 |
764 |
0 |
0 |
T155 |
180890 |
475 |
0 |
0 |
T171 |
34748 |
163 |
0 |
0 |
T172 |
10210 |
18 |
0 |
0 |
T173 |
5872 |
11 |
0 |
0 |
T174 |
33029 |
186 |
0 |
0 |
T175 |
13475 |
20 |
0 |
0 |
T176 |
8743 |
18 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4795 |
0 |
0 |
T36 |
96830 |
482 |
0 |
0 |
T131 |
108610 |
504 |
0 |
0 |
T154 |
119997 |
724 |
0 |
0 |
T155 |
180890 |
400 |
0 |
0 |
T171 |
34748 |
127 |
0 |
0 |
T172 |
10210 |
71 |
0 |
0 |
T173 |
5872 |
72 |
0 |
0 |
T174 |
33029 |
208 |
0 |
0 |
T175 |
13475 |
48 |
0 |
0 |
T176 |
8743 |
57 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4971 |
0 |
0 |
T36 |
96830 |
314 |
0 |
0 |
T131 |
108610 |
1125 |
0 |
0 |
T154 |
119997 |
794 |
0 |
0 |
T155 |
180890 |
406 |
0 |
0 |
T171 |
34748 |
152 |
0 |
0 |
T172 |
10210 |
52 |
0 |
0 |
T173 |
5872 |
66 |
0 |
0 |
T174 |
33029 |
445 |
0 |
0 |
T175 |
13475 |
44 |
0 |
0 |
T176 |
8743 |
13 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4554 |
0 |
0 |
T36 |
96830 |
531 |
0 |
0 |
T131 |
108610 |
721 |
0 |
0 |
T154 |
119997 |
761 |
0 |
0 |
T155 |
180890 |
368 |
0 |
0 |
T171 |
34748 |
117 |
0 |
0 |
T172 |
10210 |
13 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
315 |
0 |
0 |
T175 |
13475 |
68 |
0 |
0 |
T176 |
8743 |
40 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5205 |
0 |
0 |
T36 |
96830 |
478 |
0 |
0 |
T131 |
108610 |
799 |
0 |
0 |
T154 |
119997 |
791 |
0 |
0 |
T155 |
180890 |
471 |
0 |
0 |
T171 |
34748 |
131 |
0 |
0 |
T172 |
10210 |
60 |
0 |
0 |
T173 |
5872 |
47 |
0 |
0 |
T174 |
33029 |
348 |
0 |
0 |
T175 |
13475 |
34 |
0 |
0 |
T176 |
8743 |
32 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5195 |
0 |
0 |
T36 |
96830 |
499 |
0 |
0 |
T131 |
108610 |
836 |
0 |
0 |
T154 |
119997 |
806 |
0 |
0 |
T155 |
180890 |
404 |
0 |
0 |
T171 |
34748 |
125 |
0 |
0 |
T172 |
10210 |
42 |
0 |
0 |
T173 |
5872 |
16 |
0 |
0 |
T174 |
33029 |
292 |
0 |
0 |
T175 |
13475 |
35 |
0 |
0 |
T176 |
8743 |
73 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4569 |
0 |
0 |
T36 |
96830 |
422 |
0 |
0 |
T131 |
108610 |
845 |
0 |
0 |
T154 |
119997 |
750 |
0 |
0 |
T155 |
180890 |
372 |
0 |
0 |
T171 |
34748 |
143 |
0 |
0 |
T172 |
10210 |
68 |
0 |
0 |
T173 |
5872 |
1 |
0 |
0 |
T174 |
33029 |
139 |
0 |
0 |
T175 |
13475 |
67 |
0 |
0 |
T176 |
8743 |
27 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5036 |
0 |
0 |
T36 |
96830 |
385 |
0 |
0 |
T131 |
108610 |
930 |
0 |
0 |
T136 |
17778 |
3 |
0 |
0 |
T154 |
119997 |
681 |
0 |
0 |
T155 |
180890 |
429 |
0 |
0 |
T171 |
34748 |
200 |
0 |
0 |
T172 |
10210 |
88 |
0 |
0 |
T173 |
5872 |
57 |
0 |
0 |
T174 |
33029 |
232 |
0 |
0 |
T175 |
13475 |
28 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4898 |
0 |
0 |
T36 |
96830 |
463 |
0 |
0 |
T131 |
108610 |
769 |
0 |
0 |
T154 |
119997 |
724 |
0 |
0 |
T155 |
180890 |
401 |
0 |
0 |
T171 |
34748 |
116 |
0 |
0 |
T172 |
10210 |
47 |
0 |
0 |
T173 |
5872 |
71 |
0 |
0 |
T174 |
33029 |
155 |
0 |
0 |
T175 |
13475 |
35 |
0 |
0 |
T176 |
8743 |
40 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4999 |
0 |
0 |
T36 |
96830 |
393 |
0 |
0 |
T131 |
108610 |
888 |
0 |
0 |
T154 |
119997 |
803 |
0 |
0 |
T155 |
180890 |
427 |
0 |
0 |
T171 |
34748 |
161 |
0 |
0 |
T172 |
10210 |
55 |
0 |
0 |
T173 |
5872 |
9 |
0 |
0 |
T174 |
33029 |
174 |
0 |
0 |
T175 |
13475 |
54 |
0 |
0 |
T176 |
8743 |
18 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4596 |
0 |
0 |
T36 |
96830 |
312 |
0 |
0 |
T131 |
108610 |
855 |
0 |
0 |
T154 |
119997 |
732 |
0 |
0 |
T155 |
180890 |
400 |
0 |
0 |
T171 |
34748 |
120 |
0 |
0 |
T172 |
10210 |
92 |
0 |
0 |
T173 |
5872 |
62 |
0 |
0 |
T174 |
33029 |
204 |
0 |
0 |
T175 |
13475 |
64 |
0 |
0 |
T176 |
8743 |
45 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5231 |
0 |
0 |
T36 |
96830 |
447 |
0 |
0 |
T131 |
108610 |
806 |
0 |
0 |
T154 |
119997 |
750 |
0 |
0 |
T155 |
180890 |
489 |
0 |
0 |
T171 |
34748 |
153 |
0 |
0 |
T172 |
10210 |
104 |
0 |
0 |
T173 |
5872 |
70 |
0 |
0 |
T174 |
33029 |
290 |
0 |
0 |
T175 |
13475 |
32 |
0 |
0 |
T176 |
8743 |
7 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5568 |
0 |
0 |
T36 |
96830 |
530 |
0 |
0 |
T131 |
108610 |
1012 |
0 |
0 |
T154 |
119997 |
776 |
0 |
0 |
T155 |
180890 |
428 |
0 |
0 |
T171 |
34748 |
105 |
0 |
0 |
T172 |
10210 |
78 |
0 |
0 |
T173 |
5872 |
6 |
0 |
0 |
T174 |
33029 |
412 |
0 |
0 |
T175 |
13475 |
25 |
0 |
0 |
T176 |
8743 |
1 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4853 |
0 |
0 |
T36 |
96830 |
345 |
0 |
0 |
T131 |
108610 |
768 |
0 |
0 |
T154 |
119997 |
704 |
0 |
0 |
T155 |
180890 |
460 |
0 |
0 |
T171 |
34748 |
144 |
0 |
0 |
T172 |
10210 |
46 |
0 |
0 |
T173 |
5872 |
39 |
0 |
0 |
T174 |
33029 |
368 |
0 |
0 |
T175 |
13475 |
54 |
0 |
0 |
T176 |
8743 |
4 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5106 |
0 |
0 |
T36 |
96830 |
480 |
0 |
0 |
T131 |
108610 |
1000 |
0 |
0 |
T154 |
119997 |
796 |
0 |
0 |
T155 |
180890 |
403 |
0 |
0 |
T171 |
34748 |
168 |
0 |
0 |
T172 |
10210 |
12 |
0 |
0 |
T173 |
5872 |
17 |
0 |
0 |
T174 |
33029 |
232 |
0 |
0 |
T175 |
13475 |
47 |
0 |
0 |
T176 |
8743 |
34 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5340 |
0 |
0 |
T36 |
96830 |
589 |
0 |
0 |
T131 |
108610 |
831 |
0 |
0 |
T154 |
119997 |
740 |
0 |
0 |
T155 |
180890 |
457 |
0 |
0 |
T171 |
34748 |
159 |
0 |
0 |
T172 |
10210 |
66 |
0 |
0 |
T173 |
5872 |
4 |
0 |
0 |
T174 |
33029 |
353 |
0 |
0 |
T175 |
13475 |
57 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4886 |
0 |
0 |
T36 |
96830 |
419 |
0 |
0 |
T131 |
108610 |
789 |
0 |
0 |
T154 |
119997 |
742 |
0 |
0 |
T155 |
180890 |
451 |
0 |
0 |
T171 |
34748 |
120 |
0 |
0 |
T172 |
10210 |
52 |
0 |
0 |
T173 |
5872 |
10 |
0 |
0 |
T174 |
33029 |
206 |
0 |
0 |
T175 |
13475 |
20 |
0 |
0 |
T176 |
8743 |
72 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4755 |
0 |
0 |
T36 |
96830 |
438 |
0 |
0 |
T131 |
108610 |
715 |
0 |
0 |
T154 |
119997 |
754 |
0 |
0 |
T155 |
180890 |
479 |
0 |
0 |
T171 |
34748 |
178 |
0 |
0 |
T172 |
10210 |
70 |
0 |
0 |
T173 |
5872 |
14 |
0 |
0 |
T174 |
33029 |
235 |
0 |
0 |
T175 |
13475 |
42 |
0 |
0 |
T176 |
8743 |
3 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4992 |
0 |
0 |
T36 |
96830 |
477 |
0 |
0 |
T131 |
108610 |
1017 |
0 |
0 |
T154 |
119997 |
831 |
0 |
0 |
T155 |
180890 |
420 |
0 |
0 |
T171 |
34748 |
149 |
0 |
0 |
T172 |
10210 |
18 |
0 |
0 |
T173 |
5872 |
12 |
0 |
0 |
T174 |
33029 |
171 |
0 |
0 |
T175 |
13475 |
20 |
0 |
0 |
T176 |
8743 |
69 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4954 |
0 |
0 |
T36 |
96830 |
426 |
0 |
0 |
T131 |
108610 |
1029 |
0 |
0 |
T154 |
119997 |
770 |
0 |
0 |
T155 |
180890 |
436 |
0 |
0 |
T171 |
34748 |
174 |
0 |
0 |
T172 |
10210 |
73 |
0 |
0 |
T173 |
5872 |
53 |
0 |
0 |
T174 |
33029 |
174 |
0 |
0 |
T175 |
13475 |
67 |
0 |
0 |
T176 |
8743 |
42 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
5200 |
0 |
0 |
T36 |
96830 |
459 |
0 |
0 |
T131 |
108610 |
891 |
0 |
0 |
T154 |
119997 |
733 |
0 |
0 |
T155 |
180890 |
425 |
0 |
0 |
T171 |
34748 |
167 |
0 |
0 |
T172 |
10210 |
115 |
0 |
0 |
T173 |
5872 |
6 |
0 |
0 |
T174 |
33029 |
314 |
0 |
0 |
T175 |
13475 |
47 |
0 |
0 |
T176 |
8743 |
7 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
4663 |
0 |
0 |
T36 |
96830 |
479 |
0 |
0 |
T131 |
108610 |
641 |
0 |
0 |
T154 |
119997 |
717 |
0 |
0 |
T155 |
180890 |
473 |
0 |
0 |
T171 |
34748 |
125 |
0 |
0 |
T172 |
10210 |
14 |
0 |
0 |
T173 |
5872 |
64 |
0 |
0 |
T174 |
33029 |
140 |
0 |
0 |
T175 |
13475 |
27 |
0 |
0 |
T176 |
8743 |
5 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2229 |
0 |
0 |
T36 |
96830 |
73 |
0 |
0 |
T131 |
108610 |
144 |
0 |
0 |
T154 |
119997 |
768 |
0 |
0 |
T155 |
180890 |
485 |
0 |
0 |
T171 |
34748 |
97 |
0 |
0 |
T172 |
10210 |
15 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
69 |
0 |
0 |
T175 |
13475 |
59 |
0 |
0 |
T176 |
8743 |
18 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2246 |
0 |
0 |
T36 |
96830 |
111 |
0 |
0 |
T131 |
108610 |
171 |
0 |
0 |
T154 |
119997 |
744 |
0 |
0 |
T155 |
180890 |
443 |
0 |
0 |
T171 |
34748 |
110 |
0 |
0 |
T172 |
10210 |
16 |
0 |
0 |
T173 |
5872 |
17 |
0 |
0 |
T174 |
33029 |
64 |
0 |
0 |
T175 |
13475 |
47 |
0 |
0 |
T176 |
8743 |
7 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2216 |
0 |
0 |
T36 |
96830 |
77 |
0 |
0 |
T131 |
108610 |
158 |
0 |
0 |
T154 |
119997 |
741 |
0 |
0 |
T155 |
180890 |
461 |
0 |
0 |
T171 |
34748 |
101 |
0 |
0 |
T172 |
10210 |
39 |
0 |
0 |
T173 |
5872 |
12 |
0 |
0 |
T174 |
33029 |
59 |
0 |
0 |
T175 |
13475 |
40 |
0 |
0 |
T176 |
8743 |
15 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2198 |
0 |
0 |
T36 |
96830 |
91 |
0 |
0 |
T131 |
108610 |
176 |
0 |
0 |
T154 |
119997 |
691 |
0 |
0 |
T155 |
180890 |
449 |
0 |
0 |
T171 |
34748 |
151 |
0 |
0 |
T172 |
10210 |
15 |
0 |
0 |
T173 |
5872 |
2 |
0 |
0 |
T174 |
33029 |
67 |
0 |
0 |
T175 |
13475 |
47 |
0 |
0 |
T176 |
8743 |
9 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2692 |
0 |
0 |
T36 |
96830 |
146 |
0 |
0 |
T131 |
108610 |
295 |
0 |
0 |
T154 |
119997 |
759 |
0 |
0 |
T155 |
180890 |
470 |
0 |
0 |
T171 |
34748 |
155 |
0 |
0 |
T172 |
10210 |
7 |
0 |
0 |
T173 |
5872 |
12 |
0 |
0 |
T174 |
33029 |
102 |
0 |
0 |
T175 |
13475 |
25 |
0 |
0 |
T176 |
8743 |
25 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
3592 |
0 |
0 |
T36 |
0 |
251 |
0 |
0 |
T87 |
570472 |
0 |
0 |
0 |
T131 |
0 |
455 |
0 |
0 |
T154 |
0 |
694 |
0 |
0 |
T171 |
0 |
142 |
0 |
0 |
T172 |
0 |
31 |
0 |
0 |
T173 |
0 |
51 |
0 |
0 |
T177 |
5959 |
24 |
0 |
0 |
T178 |
0 |
9 |
0 |
0 |
T179 |
0 |
18 |
0 |
0 |
T180 |
0 |
26 |
0 |
0 |
T181 |
60269 |
0 |
0 |
0 |
T182 |
5743 |
0 |
0 |
0 |
T183 |
180010 |
0 |
0 |
0 |
T184 |
70093 |
0 |
0 |
0 |
T185 |
75879 |
0 |
0 |
0 |
T186 |
1679 |
0 |
0 |
0 |
T187 |
3188 |
0 |
0 |
0 |
T188 |
80292 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2304 |
0 |
0 |
T36 |
96830 |
75 |
0 |
0 |
T131 |
108610 |
171 |
0 |
0 |
T154 |
119997 |
753 |
0 |
0 |
T155 |
180890 |
464 |
0 |
0 |
T171 |
34748 |
141 |
0 |
0 |
T172 |
10210 |
16 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
57 |
0 |
0 |
T175 |
13475 |
75 |
0 |
0 |
T176 |
8743 |
4 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2314 |
0 |
0 |
T36 |
96830 |
106 |
0 |
0 |
T131 |
108610 |
159 |
0 |
0 |
T154 |
119997 |
807 |
0 |
0 |
T155 |
180890 |
466 |
0 |
0 |
T171 |
34748 |
126 |
0 |
0 |
T172 |
10210 |
10 |
0 |
0 |
T173 |
5872 |
12 |
0 |
0 |
T174 |
33029 |
66 |
0 |
0 |
T175 |
13475 |
55 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2162 |
0 |
0 |
T36 |
96830 |
65 |
0 |
0 |
T131 |
108610 |
126 |
0 |
0 |
T154 |
119997 |
789 |
0 |
0 |
T155 |
180890 |
477 |
0 |
0 |
T171 |
34748 |
191 |
0 |
0 |
T172 |
10210 |
13 |
0 |
0 |
T173 |
5872 |
10 |
0 |
0 |
T174 |
33029 |
23 |
0 |
0 |
T175 |
13475 |
40 |
0 |
0 |
T176 |
8743 |
17 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
1947 |
0 |
0 |
T36 |
96830 |
55 |
0 |
0 |
T131 |
108610 |
105 |
0 |
0 |
T154 |
119997 |
698 |
0 |
0 |
T155 |
180890 |
427 |
0 |
0 |
T171 |
34748 |
132 |
0 |
0 |
T172 |
10210 |
10 |
0 |
0 |
T173 |
5872 |
4 |
0 |
0 |
T174 |
33029 |
38 |
0 |
0 |
T175 |
13475 |
74 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2036 |
0 |
0 |
T36 |
96830 |
56 |
0 |
0 |
T131 |
108610 |
106 |
0 |
0 |
T154 |
119997 |
749 |
0 |
0 |
T155 |
180890 |
452 |
0 |
0 |
T171 |
34748 |
177 |
0 |
0 |
T172 |
10210 |
16 |
0 |
0 |
T173 |
5872 |
11 |
0 |
0 |
T174 |
33029 |
34 |
0 |
0 |
T175 |
13475 |
32 |
0 |
0 |
T176 |
8743 |
4 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2135 |
0 |
0 |
T36 |
96830 |
91 |
0 |
0 |
T131 |
108610 |
132 |
0 |
0 |
T154 |
119997 |
772 |
0 |
0 |
T155 |
180890 |
468 |
0 |
0 |
T171 |
34748 |
155 |
0 |
0 |
T172 |
10210 |
11 |
0 |
0 |
T173 |
5872 |
5 |
0 |
0 |
T174 |
33029 |
33 |
0 |
0 |
T175 |
13475 |
61 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2848 |
0 |
0 |
T36 |
96830 |
156 |
0 |
0 |
T131 |
108610 |
333 |
0 |
0 |
T154 |
119997 |
744 |
0 |
0 |
T155 |
180890 |
446 |
0 |
0 |
T171 |
34748 |
166 |
0 |
0 |
T172 |
10210 |
39 |
0 |
0 |
T173 |
5872 |
22 |
0 |
0 |
T174 |
33029 |
102 |
0 |
0 |
T175 |
13475 |
60 |
0 |
0 |
T176 |
8743 |
34 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2069 |
0 |
0 |
T36 |
96830 |
26 |
0 |
0 |
T131 |
108610 |
111 |
0 |
0 |
T154 |
119997 |
775 |
0 |
0 |
T155 |
180890 |
528 |
0 |
0 |
T171 |
34748 |
128 |
0 |
0 |
T172 |
10210 |
13 |
0 |
0 |
T173 |
5872 |
5 |
0 |
0 |
T174 |
33029 |
47 |
0 |
0 |
T175 |
13475 |
68 |
0 |
0 |
T176 |
8743 |
8 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
3126 |
0 |
0 |
T36 |
96830 |
213 |
0 |
0 |
T131 |
108610 |
285 |
0 |
0 |
T154 |
119997 |
781 |
0 |
0 |
T155 |
180890 |
432 |
0 |
0 |
T171 |
34748 |
137 |
0 |
0 |
T172 |
10210 |
33 |
0 |
0 |
T173 |
5872 |
5 |
0 |
0 |
T174 |
33029 |
131 |
0 |
0 |
T175 |
13475 |
49 |
0 |
0 |
T176 |
8743 |
12 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2223 |
0 |
0 |
T36 |
96830 |
77 |
0 |
0 |
T131 |
108610 |
173 |
0 |
0 |
T154 |
119997 |
754 |
0 |
0 |
T155 |
180890 |
428 |
0 |
0 |
T171 |
34748 |
167 |
0 |
0 |
T172 |
10210 |
21 |
0 |
0 |
T173 |
5872 |
4 |
0 |
0 |
T174 |
33029 |
50 |
0 |
0 |
T175 |
13475 |
59 |
0 |
0 |
T176 |
8743 |
9 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2030 |
0 |
0 |
T36 |
96830 |
46 |
0 |
0 |
T131 |
108610 |
129 |
0 |
0 |
T154 |
119997 |
779 |
0 |
0 |
T155 |
180890 |
457 |
0 |
0 |
T171 |
34748 |
180 |
0 |
0 |
T172 |
10210 |
13 |
0 |
0 |
T173 |
5872 |
6 |
0 |
0 |
T174 |
33029 |
33 |
0 |
0 |
T175 |
13475 |
22 |
0 |
0 |
T176 |
8743 |
6 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
1985 |
0 |
0 |
T36 |
96830 |
55 |
0 |
0 |
T131 |
108610 |
111 |
0 |
0 |
T154 |
119997 |
779 |
0 |
0 |
T155 |
180890 |
435 |
0 |
0 |
T171 |
34748 |
174 |
0 |
0 |
T172 |
10210 |
19 |
0 |
0 |
T173 |
5872 |
12 |
0 |
0 |
T174 |
33029 |
35 |
0 |
0 |
T175 |
13475 |
31 |
0 |
0 |
T176 |
8743 |
4 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
1987 |
0 |
0 |
T36 |
96830 |
87 |
0 |
0 |
T131 |
108610 |
111 |
0 |
0 |
T154 |
119997 |
729 |
0 |
0 |
T155 |
180890 |
453 |
0 |
0 |
T159 |
9895 |
12 |
0 |
0 |
T171 |
34748 |
137 |
0 |
0 |
T172 |
10210 |
29 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
46 |
0 |
0 |
T175 |
13475 |
38 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2043 |
0 |
0 |
T36 |
96830 |
45 |
0 |
0 |
T131 |
108610 |
125 |
0 |
0 |
T154 |
119997 |
756 |
0 |
0 |
T155 |
180890 |
479 |
0 |
0 |
T171 |
34748 |
121 |
0 |
0 |
T172 |
10210 |
15 |
0 |
0 |
T173 |
5872 |
8 |
0 |
0 |
T174 |
33029 |
44 |
0 |
0 |
T175 |
13475 |
65 |
0 |
0 |
T176 |
8743 |
11 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2074 |
0 |
0 |
T36 |
96830 |
104 |
0 |
0 |
T131 |
108610 |
126 |
0 |
0 |
T154 |
119997 |
829 |
0 |
0 |
T155 |
180890 |
408 |
0 |
0 |
T171 |
34748 |
122 |
0 |
0 |
T172 |
10210 |
22 |
0 |
0 |
T173 |
5872 |
3 |
0 |
0 |
T174 |
33029 |
35 |
0 |
0 |
T175 |
13475 |
44 |
0 |
0 |
T176 |
8743 |
3 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113963792 |
2011 |
0 |
0 |
T36 |
96830 |
85 |
0 |
0 |
T131 |
108610 |
115 |
0 |
0 |
T154 |
119997 |
792 |
0 |
0 |
T155 |
180890 |
412 |
0 |
0 |
T171 |
34748 |
164 |
0 |
0 |
T172 |
10210 |
9 |
0 |
0 |
T173 |
5872 |
14 |
0 |
0 |
T174 |
33029 |
45 |
0 |
0 |
T175 |
13475 |
18 |
0 |
0 |
T176 |
8743 |
22 |
0 |
0 |