| T639 |
/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1653109337 |
|
|
Mar 31 02:46:16 PM PDT 24 |
Mar 31 02:46:19 PM PDT 24 |
316998812 ps |
| T248 |
/workspace/coverage/default/35.spi_device_intercept.164110669 |
|
|
Mar 31 02:46:32 PM PDT 24 |
Mar 31 02:46:36 PM PDT 24 |
435395320 ps |
| T640 |
/workspace/coverage/default/15.spi_device_tpm_rw.1444680914 |
|
|
Mar 31 02:45:00 PM PDT 24 |
Mar 31 02:45:01 PM PDT 24 |
55683190 ps |
| T341 |
/workspace/coverage/default/12.spi_device_pass_cmd_filtering.2615693860 |
|
|
Mar 31 02:44:47 PM PDT 24 |
Mar 31 02:44:50 PM PDT 24 |
564298776 ps |
| T641 |
/workspace/coverage/default/18.spi_device_tpm_rw.2603684115 |
|
|
Mar 31 02:45:11 PM PDT 24 |
Mar 31 02:45:23 PM PDT 24 |
3233265305 ps |
| T226 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3220707677 |
|
|
Mar 31 02:47:43 PM PDT 24 |
Mar 31 02:47:51 PM PDT 24 |
4470110547 ps |
| T105 |
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2490908689 |
|
|
Mar 31 02:44:31 PM PDT 24 |
Mar 31 02:45:16 PM PDT 24 |
3292076384 ps |
| T642 |
/workspace/coverage/default/31.spi_device_alert_test.1976415902 |
|
|
Mar 31 02:46:18 PM PDT 24 |
Mar 31 02:46:19 PM PDT 24 |
13314559 ps |
| T643 |
/workspace/coverage/default/25.spi_device_tpm_sts_read.2083107260 |
|
|
Mar 31 02:45:47 PM PDT 24 |
Mar 31 02:45:48 PM PDT 24 |
193992212 ps |
| T644 |
/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2966756070 |
|
|
Mar 31 02:45:18 PM PDT 24 |
Mar 31 02:45:22 PM PDT 24 |
602355556 ps |
| T645 |
/workspace/coverage/default/20.spi_device_tpm_rw.3944290626 |
|
|
Mar 31 02:45:16 PM PDT 24 |
Mar 31 02:45:20 PM PDT 24 |
529612338 ps |
| T646 |
/workspace/coverage/default/47.spi_device_alert_test.469160215 |
|
|
Mar 31 02:47:37 PM PDT 24 |
Mar 31 02:47:37 PM PDT 24 |
36881895 ps |
| T647 |
/workspace/coverage/default/35.spi_device_tpm_rw.64343456 |
|
|
Mar 31 02:46:28 PM PDT 24 |
Mar 31 02:46:31 PM PDT 24 |
58512130 ps |
| T648 |
/workspace/coverage/default/8.spi_device_ram_cfg.1162653779 |
|
|
Mar 31 02:44:22 PM PDT 24 |
Mar 31 02:44:23 PM PDT 24 |
18429222 ps |
| T649 |
/workspace/coverage/default/46.spi_device_alert_test.145388612 |
|
|
Mar 31 02:47:24 PM PDT 24 |
Mar 31 02:47:25 PM PDT 24 |
13096665 ps |
| T650 |
/workspace/coverage/default/23.spi_device_csb_read.1339699260 |
|
|
Mar 31 02:45:45 PM PDT 24 |
Mar 31 02:45:46 PM PDT 24 |
15770548 ps |
| T651 |
/workspace/coverage/default/12.spi_device_alert_test.2065387306 |
|
|
Mar 31 02:44:51 PM PDT 24 |
Mar 31 02:44:52 PM PDT 24 |
12687100 ps |
| T366 |
/workspace/coverage/default/14.spi_device_flash_mode.1713222824 |
|
|
Mar 31 02:44:53 PM PDT 24 |
Mar 31 02:45:34 PM PDT 24 |
6046464828 ps |
| T652 |
/workspace/coverage/default/2.spi_device_tpm_sts_read.2615363472 |
|
|
Mar 31 02:43:50 PM PDT 24 |
Mar 31 02:43:52 PM PDT 24 |
123493979 ps |
| T653 |
/workspace/coverage/default/39.spi_device_intercept.1945032273 |
|
|
Mar 31 02:46:49 PM PDT 24 |
Mar 31 02:46:55 PM PDT 24 |
847580909 ps |
| T654 |
/workspace/coverage/default/49.spi_device_tpm_all.2664458063 |
|
|
Mar 31 02:47:42 PM PDT 24 |
Mar 31 02:48:00 PM PDT 24 |
8366984028 ps |
| T655 |
/workspace/coverage/default/20.spi_device_alert_test.975500782 |
|
|
Mar 31 02:45:24 PM PDT 24 |
Mar 31 02:45:24 PM PDT 24 |
128009503 ps |
| T253 |
/workspace/coverage/default/32.spi_device_intercept.2312862787 |
|
|
Mar 31 02:46:18 PM PDT 24 |
Mar 31 02:46:22 PM PDT 24 |
353221266 ps |
| T202 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.1504489450 |
|
|
Mar 31 02:45:01 PM PDT 24 |
Mar 31 02:45:12 PM PDT 24 |
57371078079 ps |
| T656 |
/workspace/coverage/default/31.spi_device_csb_read.382643752 |
|
|
Mar 31 02:46:10 PM PDT 24 |
Mar 31 02:46:11 PM PDT 24 |
64404191 ps |
| T657 |
/workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1369323065 |
|
|
Mar 31 02:45:50 PM PDT 24 |
Mar 31 02:45:56 PM PDT 24 |
2417841747 ps |
| T345 |
/workspace/coverage/default/0.spi_device_upload.2425723869 |
|
|
Mar 31 02:43:40 PM PDT 24 |
Mar 31 02:44:32 PM PDT 24 |
41901346455 ps |
| T237 |
/workspace/coverage/default/40.spi_device_upload.1537585143 |
|
|
Mar 31 02:46:52 PM PDT 24 |
Mar 31 02:46:59 PM PDT 24 |
825004595 ps |
| T297 |
/workspace/coverage/default/11.spi_device_mailbox.820709381 |
|
|
Mar 31 02:44:43 PM PDT 24 |
Mar 31 02:46:15 PM PDT 24 |
53836450241 ps |
| T658 |
/workspace/coverage/default/28.spi_device_tpm_sts_read.1782042084 |
|
|
Mar 31 02:46:04 PM PDT 24 |
Mar 31 02:46:05 PM PDT 24 |
80751783 ps |
| T659 |
/workspace/coverage/default/21.spi_device_alert_test.1288236450 |
|
|
Mar 31 02:45:31 PM PDT 24 |
Mar 31 02:45:32 PM PDT 24 |
38764319 ps |
| T660 |
/workspace/coverage/default/19.spi_device_csb_read.2163296463 |
|
|
Mar 31 02:45:13 PM PDT 24 |
Mar 31 02:45:14 PM PDT 24 |
35862986 ps |
| T114 |
/workspace/coverage/default/13.spi_device_intercept.1883714018 |
|
|
Mar 31 02:44:51 PM PDT 24 |
Mar 31 02:44:57 PM PDT 24 |
1430560666 ps |
| T316 |
/workspace/coverage/default/34.spi_device_flash_mode.2131263054 |
|
|
Mar 31 02:46:26 PM PDT 24 |
Mar 31 02:47:21 PM PDT 24 |
3776638773 ps |
| T192 |
/workspace/coverage/default/1.spi_device_intercept.1210398111 |
|
|
Mar 31 02:43:43 PM PDT 24 |
Mar 31 02:44:01 PM PDT 24 |
7791672504 ps |
| T661 |
/workspace/coverage/default/18.spi_device_csb_read.2451080902 |
|
|
Mar 31 02:45:09 PM PDT 24 |
Mar 31 02:45:10 PM PDT 24 |
26134100 ps |
| T662 |
/workspace/coverage/default/12.spi_device_intercept.1324750168 |
|
|
Mar 31 02:44:51 PM PDT 24 |
Mar 31 02:45:04 PM PDT 24 |
15904349104 ps |
| T663 |
/workspace/coverage/default/38.spi_device_alert_test.1484612431 |
|
|
Mar 31 02:46:47 PM PDT 24 |
Mar 31 02:46:47 PM PDT 24 |
21378803 ps |
| T664 |
/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2841750424 |
|
|
Mar 31 02:47:12 PM PDT 24 |
Mar 31 02:47:33 PM PDT 24 |
6431593164 ps |
| T665 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.1403059724 |
|
|
Mar 31 02:43:55 PM PDT 24 |
Mar 31 02:44:00 PM PDT 24 |
311735547 ps |
| T666 |
/workspace/coverage/default/39.spi_device_alert_test.1941612859 |
|
|
Mar 31 02:46:57 PM PDT 24 |
Mar 31 02:46:57 PM PDT 24 |
46543487 ps |
| T667 |
/workspace/coverage/default/42.spi_device_tpm_sts_read.3315849225 |
|
|
Mar 31 02:47:00 PM PDT 24 |
Mar 31 02:47:01 PM PDT 24 |
89398758 ps |
| T668 |
/workspace/coverage/default/48.spi_device_tpm_sts_read.2382772256 |
|
|
Mar 31 02:47:34 PM PDT 24 |
Mar 31 02:47:34 PM PDT 24 |
48183284 ps |
| T669 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.671869587 |
|
|
Mar 31 02:44:58 PM PDT 24 |
Mar 31 02:45:25 PM PDT 24 |
30950424882 ps |
| T670 |
/workspace/coverage/default/31.spi_device_tpm_all.4014935748 |
|
|
Mar 31 02:46:14 PM PDT 24 |
Mar 31 02:46:42 PM PDT 24 |
3465366399 ps |
| T355 |
/workspace/coverage/default/22.spi_device_upload.1137595434 |
|
|
Mar 31 02:45:31 PM PDT 24 |
Mar 31 02:45:46 PM PDT 24 |
1972247773 ps |
| T671 |
/workspace/coverage/default/45.spi_device_mailbox.2276569647 |
|
|
Mar 31 02:47:21 PM PDT 24 |
Mar 31 02:47:46 PM PDT 24 |
2938452982 ps |
| T672 |
/workspace/coverage/default/38.spi_device_tpm_all.3067388940 |
|
|
Mar 31 02:46:39 PM PDT 24 |
Mar 31 02:47:38 PM PDT 24 |
45450109705 ps |
| T673 |
/workspace/coverage/default/10.spi_device_ram_cfg.3265913369 |
|
|
Mar 31 02:44:39 PM PDT 24 |
Mar 31 02:44:40 PM PDT 24 |
42920777 ps |
| T674 |
/workspace/coverage/default/34.spi_device_read_buffer_direct.1492517275 |
|
|
Mar 31 02:46:28 PM PDT 24 |
Mar 31 02:46:38 PM PDT 24 |
521506307 ps |
| T675 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.3993552796 |
|
|
Mar 31 02:46:28 PM PDT 24 |
Mar 31 02:46:29 PM PDT 24 |
514898119 ps |
| T676 |
/workspace/coverage/default/25.spi_device_read_buffer_direct.1196134553 |
|
|
Mar 31 02:45:48 PM PDT 24 |
Mar 31 02:45:52 PM PDT 24 |
334113048 ps |
| T677 |
/workspace/coverage/default/3.spi_device_csb_read.204040863 |
|
|
Mar 31 02:43:55 PM PDT 24 |
Mar 31 02:43:56 PM PDT 24 |
33020183 ps |
| T678 |
/workspace/coverage/default/27.spi_device_csb_read.3246677777 |
|
|
Mar 31 02:45:53 PM PDT 24 |
Mar 31 02:45:54 PM PDT 24 |
22204518 ps |
| T679 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.2966079031 |
|
|
Mar 31 02:47:20 PM PDT 24 |
Mar 31 02:47:24 PM PDT 24 |
195744869 ps |
| T680 |
/workspace/coverage/default/11.spi_device_tpm_rw.4252788092 |
|
|
Mar 31 02:44:43 PM PDT 24 |
Mar 31 02:44:45 PM PDT 24 |
175016662 ps |
| T681 |
/workspace/coverage/default/8.spi_device_csb_read.41398317 |
|
|
Mar 31 02:44:24 PM PDT 24 |
Mar 31 02:44:25 PM PDT 24 |
38696698 ps |
| T276 |
/workspace/coverage/default/44.spi_device_pass_cmd_filtering.2234742487 |
|
|
Mar 31 02:47:15 PM PDT 24 |
Mar 31 02:47:27 PM PDT 24 |
51617983541 ps |
| T326 |
/workspace/coverage/default/13.spi_device_upload.1011694714 |
|
|
Mar 31 02:44:46 PM PDT 24 |
Mar 31 02:45:01 PM PDT 24 |
4789737867 ps |
| T682 |
/workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2115247985 |
|
|
Mar 31 02:46:10 PM PDT 24 |
Mar 31 02:46:15 PM PDT 24 |
727385239 ps |
| T683 |
/workspace/coverage/default/12.spi_device_read_buffer_direct.3565624487 |
|
|
Mar 31 02:44:51 PM PDT 24 |
Mar 31 02:44:55 PM PDT 24 |
100417855 ps |
| T370 |
/workspace/coverage/default/4.spi_device_flash_mode.2843146670 |
|
|
Mar 31 02:44:06 PM PDT 24 |
Mar 31 02:44:19 PM PDT 24 |
1617540613 ps |
| T86 |
/workspace/coverage/default/23.spi_device_pass_addr_payload_swap.74017185 |
|
|
Mar 31 02:45:40 PM PDT 24 |
Mar 31 02:45:50 PM PDT 24 |
1668847111 ps |
| T684 |
/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2216855863 |
|
|
Mar 31 02:46:41 PM PDT 24 |
Mar 31 02:46:49 PM PDT 24 |
10046661137 ps |
| T359 |
/workspace/coverage/default/45.spi_device_pass_addr_payload_swap.500539945 |
|
|
Mar 31 02:47:22 PM PDT 24 |
Mar 31 02:47:38 PM PDT 24 |
6824225964 ps |
| T685 |
/workspace/coverage/default/4.spi_device_ram_cfg.1527638832 |
|
|
Mar 31 02:44:01 PM PDT 24 |
Mar 31 02:44:02 PM PDT 24 |
17596365 ps |
| T686 |
/workspace/coverage/default/10.spi_device_stress_all.2453963530 |
|
|
Mar 31 02:44:34 PM PDT 24 |
Mar 31 02:44:36 PM PDT 24 |
124992569 ps |
| T368 |
/workspace/coverage/default/30.spi_device_flash_mode.2249289217 |
|
|
Mar 31 02:46:03 PM PDT 24 |
Mar 31 02:46:15 PM PDT 24 |
424052382 ps |
| T687 |
/workspace/coverage/default/22.spi_device_alert_test.1695691294 |
|
|
Mar 31 02:45:39 PM PDT 24 |
Mar 31 02:45:42 PM PDT 24 |
13108653 ps |
| T688 |
/workspace/coverage/default/17.spi_device_flash_mode.2835266451 |
|
|
Mar 31 02:45:08 PM PDT 24 |
Mar 31 02:46:02 PM PDT 24 |
4029103170 ps |
| T689 |
/workspace/coverage/default/18.spi_device_flash_mode.2744891517 |
|
|
Mar 31 02:45:14 PM PDT 24 |
Mar 31 02:46:38 PM PDT 24 |
98987383500 ps |
| T690 |
/workspace/coverage/default/10.spi_device_tpm_sts_read.3252350311 |
|
|
Mar 31 02:44:35 PM PDT 24 |
Mar 31 02:44:36 PM PDT 24 |
137229589 ps |
| T691 |
/workspace/coverage/default/6.spi_device_flash_mode.1592079835 |
|
|
Mar 31 02:44:15 PM PDT 24 |
Mar 31 02:45:32 PM PDT 24 |
5541793937 ps |
| T177 |
/workspace/coverage/default/32.spi_device_stress_all.1018484196 |
|
|
Mar 31 02:46:26 PM PDT 24 |
Mar 31 02:46:28 PM PDT 24 |
248357807 ps |
| T181 |
/workspace/coverage/default/3.spi_device_intercept.2321930347 |
|
|
Mar 31 02:43:55 PM PDT 24 |
Mar 31 02:44:03 PM PDT 24 |
627855152 ps |
| T182 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3732975894 |
|
|
Mar 31 02:44:56 PM PDT 24 |
Mar 31 02:45:00 PM PDT 24 |
212752659 ps |
| T87 |
/workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1364892491 |
|
|
Mar 31 02:46:27 PM PDT 24 |
Mar 31 02:46:46 PM PDT 24 |
47539234794 ps |
| T183 |
/workspace/coverage/default/29.spi_device_flash_mode.2289039605 |
|
|
Mar 31 02:46:00 PM PDT 24 |
Mar 31 02:46:42 PM PDT 24 |
7200447953 ps |
| T184 |
/workspace/coverage/default/19.spi_device_intercept.1908295880 |
|
|
Mar 31 02:45:22 PM PDT 24 |
Mar 31 02:45:30 PM PDT 24 |
3186175032 ps |
| T185 |
/workspace/coverage/default/18.spi_device_tpm_all.298736955 |
|
|
Mar 31 02:45:15 PM PDT 24 |
Mar 31 02:45:24 PM PDT 24 |
5058713588 ps |
| T186 |
/workspace/coverage/default/7.spi_device_mem_parity.176254708 |
|
|
Mar 31 02:44:18 PM PDT 24 |
Mar 31 02:44:19 PM PDT 24 |
17149777 ps |
| T187 |
/workspace/coverage/default/18.spi_device_cfg_cmd.1745773142 |
|
|
Mar 31 02:45:12 PM PDT 24 |
Mar 31 02:45:15 PM PDT 24 |
354240039 ps |
| T188 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.2334868250 |
|
|
Mar 31 02:44:47 PM PDT 24 |
Mar 31 02:44:56 PM PDT 24 |
1638621984 ps |
| T346 |
/workspace/coverage/default/6.spi_device_upload.3163038927 |
|
|
Mar 31 02:44:17 PM PDT 24 |
Mar 31 02:45:06 PM PDT 24 |
16041853615 ps |
| T692 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.2007651149 |
|
|
Mar 31 02:46:40 PM PDT 24 |
Mar 31 02:46:42 PM PDT 24 |
69760539 ps |
| T373 |
/workspace/coverage/default/37.spi_device_pass_cmd_filtering.790122277 |
|
|
Mar 31 02:46:39 PM PDT 24 |
Mar 31 02:47:05 PM PDT 24 |
42020576703 ps |
| T693 |
/workspace/coverage/default/5.spi_device_csb_read.3358832349 |
|
|
Mar 31 02:44:07 PM PDT 24 |
Mar 31 02:44:09 PM PDT 24 |
49092651 ps |
| T694 |
/workspace/coverage/default/48.spi_device_flash_mode.2508796043 |
|
|
Mar 31 02:47:34 PM PDT 24 |
Mar 31 02:48:18 PM PDT 24 |
11964162572 ps |
| T695 |
/workspace/coverage/default/6.spi_device_ram_cfg.3031882480 |
|
|
Mar 31 02:44:12 PM PDT 24 |
Mar 31 02:44:13 PM PDT 24 |
41323653 ps |
| T696 |
/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2747910035 |
|
|
Mar 31 02:46:52 PM PDT 24 |
Mar 31 02:47:08 PM PDT 24 |
24354180582 ps |
| T697 |
/workspace/coverage/default/7.spi_device_tpm_all.2575251157 |
|
|
Mar 31 02:44:17 PM PDT 24 |
Mar 31 02:44:40 PM PDT 24 |
4690991065 ps |
| T217 |
/workspace/coverage/default/0.spi_device_pass_cmd_filtering.1640926649 |
|
|
Mar 31 02:43:38 PM PDT 24 |
Mar 31 02:43:41 PM PDT 24 |
134095975 ps |
| T256 |
/workspace/coverage/default/34.spi_device_mailbox.3731009071 |
|
|
Mar 31 02:46:26 PM PDT 24 |
Mar 31 02:46:31 PM PDT 24 |
930606612 ps |
| T698 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1346587251 |
|
|
Mar 31 02:44:21 PM PDT 24 |
Mar 31 02:44:27 PM PDT 24 |
2469686307 ps |
| T699 |
/workspace/coverage/default/4.spi_device_read_buffer_direct.1063473062 |
|
|
Mar 31 02:44:05 PM PDT 24 |
Mar 31 02:44:21 PM PDT 24 |
1701542558 ps |
| T700 |
/workspace/coverage/default/2.spi_device_mailbox.4185425173 |
|
|
Mar 31 02:43:48 PM PDT 24 |
Mar 31 02:44:32 PM PDT 24 |
5431737765 ps |
| T701 |
/workspace/coverage/default/25.spi_device_intercept.1421442205 |
|
|
Mar 31 02:45:46 PM PDT 24 |
Mar 31 02:45:55 PM PDT 24 |
3405751058 ps |
| T360 |
/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1250210784 |
|
|
Mar 31 02:45:31 PM PDT 24 |
Mar 31 02:45:49 PM PDT 24 |
3609770747 ps |
| T350 |
/workspace/coverage/default/29.spi_device_intercept.3885837303 |
|
|
Mar 31 02:46:01 PM PDT 24 |
Mar 31 02:46:31 PM PDT 24 |
14288315149 ps |
| T327 |
/workspace/coverage/default/27.spi_device_upload.1716590271 |
|
|
Mar 31 02:45:53 PM PDT 24 |
Mar 31 02:46:15 PM PDT 24 |
6419585452 ps |
| T702 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2223595088 |
|
|
Mar 31 02:43:43 PM PDT 24 |
Mar 31 02:44:06 PM PDT 24 |
14146553290 ps |
| T703 |
/workspace/coverage/default/15.spi_device_csb_read.584186675 |
|
|
Mar 31 02:45:06 PM PDT 24 |
Mar 31 02:45:09 PM PDT 24 |
69658393 ps |
| T704 |
/workspace/coverage/default/35.spi_device_csb_read.3652678585 |
|
|
Mar 31 02:46:31 PM PDT 24 |
Mar 31 02:46:32 PM PDT 24 |
17446546 ps |
| T705 |
/workspace/coverage/default/17.spi_device_tpm_sts_read.4140603307 |
|
|
Mar 31 02:45:08 PM PDT 24 |
Mar 31 02:45:10 PM PDT 24 |
120436479 ps |
| T336 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.1891977424 |
|
|
Mar 31 02:46:04 PM PDT 24 |
Mar 31 02:46:32 PM PDT 24 |
6145861432 ps |
| T706 |
/workspace/coverage/default/21.spi_device_tpm_all.3465352539 |
|
|
Mar 31 02:45:25 PM PDT 24 |
Mar 31 02:46:02 PM PDT 24 |
23326654928 ps |
| T707 |
/workspace/coverage/default/49.spi_device_csb_read.3872325255 |
|
|
Mar 31 02:47:39 PM PDT 24 |
Mar 31 02:47:40 PM PDT 24 |
190104594 ps |
| T708 |
/workspace/coverage/default/40.spi_device_alert_test.2856873680 |
|
|
Mar 31 02:46:59 PM PDT 24 |
Mar 31 02:47:00 PM PDT 24 |
39467537 ps |
| T348 |
/workspace/coverage/default/15.spi_device_intercept.819822420 |
|
|
Mar 31 02:45:00 PM PDT 24 |
Mar 31 02:45:03 PM PDT 24 |
1604040972 ps |
| T709 |
/workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3121775574 |
|
|
Mar 31 02:46:27 PM PDT 24 |
Mar 31 02:46:50 PM PDT 24 |
38389326478 ps |
| T710 |
/workspace/coverage/default/46.spi_device_read_buffer_direct.1636104443 |
|
|
Mar 31 02:47:21 PM PDT 24 |
Mar 31 02:47:32 PM PDT 24 |
868372255 ps |
| T711 |
/workspace/coverage/default/12.spi_device_csb_read.2613759705 |
|
|
Mar 31 02:44:41 PM PDT 24 |
Mar 31 02:44:41 PM PDT 24 |
22165028 ps |
| T233 |
/workspace/coverage/default/36.spi_device_upload.1891939369 |
|
|
Mar 31 02:46:37 PM PDT 24 |
Mar 31 02:46:42 PM PDT 24 |
360751659 ps |
| T712 |
/workspace/coverage/default/44.spi_device_tpm_all.2795557065 |
|
|
Mar 31 02:47:11 PM PDT 24 |
Mar 31 02:47:32 PM PDT 24 |
3559440473 ps |
| T240 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.671793671 |
|
|
Mar 31 02:43:49 PM PDT 24 |
Mar 31 02:44:00 PM PDT 24 |
2506708471 ps |
| T130 |
/workspace/coverage/default/43.spi_device_intercept.793846842 |
|
|
Mar 31 02:47:12 PM PDT 24 |
Mar 31 02:47:19 PM PDT 24 |
2441097857 ps |
| T713 |
/workspace/coverage/default/48.spi_device_alert_test.2041619826 |
|
|
Mar 31 02:47:43 PM PDT 24 |
Mar 31 02:47:44 PM PDT 24 |
65911439 ps |
| T340 |
/workspace/coverage/default/39.spi_device_mailbox.2867693721 |
|
|
Mar 31 02:46:47 PM PDT 24 |
Mar 31 02:48:13 PM PDT 24 |
99961025132 ps |
| T714 |
/workspace/coverage/default/25.spi_device_csb_read.415335577 |
|
|
Mar 31 02:45:45 PM PDT 24 |
Mar 31 02:45:46 PM PDT 24 |
14211020 ps |
| T361 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2347495155 |
|
|
Mar 31 02:45:44 PM PDT 24 |
Mar 31 02:45:50 PM PDT 24 |
1474094133 ps |
| T715 |
/workspace/coverage/default/29.spi_device_csb_read.918046984 |
|
|
Mar 31 02:45:58 PM PDT 24 |
Mar 31 02:45:59 PM PDT 24 |
70551292 ps |
| T716 |
/workspace/coverage/default/45.spi_device_tpm_rw.3053627700 |
|
|
Mar 31 02:47:21 PM PDT 24 |
Mar 31 02:47:22 PM PDT 24 |
48645430 ps |
| T717 |
/workspace/coverage/default/2.spi_device_csb_read.2582705173 |
|
|
Mar 31 02:43:51 PM PDT 24 |
Mar 31 02:43:52 PM PDT 24 |
24718371 ps |
| T718 |
/workspace/coverage/default/18.spi_device_tpm_read_hw_reg.413268330 |
|
|
Mar 31 02:45:13 PM PDT 24 |
Mar 31 02:45:31 PM PDT 24 |
14431500056 ps |
| T719 |
/workspace/coverage/default/18.spi_device_tpm_sts_read.1075434822 |
|
|
Mar 31 02:45:12 PM PDT 24 |
Mar 31 02:45:13 PM PDT 24 |
193724855 ps |
| T285 |
/workspace/coverage/default/28.spi_device_mailbox.896896249 |
|
|
Mar 31 02:46:04 PM PDT 24 |
Mar 31 02:46:10 PM PDT 24 |
245059821 ps |
| T330 |
/workspace/coverage/default/6.spi_device_mailbox.4037300772 |
|
|
Mar 31 02:44:12 PM PDT 24 |
Mar 31 02:45:26 PM PDT 24 |
36483480479 ps |
| T720 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.852732789 |
|
|
Mar 31 02:45:32 PM PDT 24 |
Mar 31 02:45:34 PM PDT 24 |
112048918 ps |
| T721 |
/workspace/coverage/default/44.spi_device_cfg_cmd.1779266152 |
|
|
Mar 31 02:47:12 PM PDT 24 |
Mar 31 02:47:27 PM PDT 24 |
1439751352 ps |
| T722 |
/workspace/coverage/default/11.spi_device_read_buffer_direct.3934180654 |
|
|
Mar 31 02:44:42 PM PDT 24 |
Mar 31 02:44:52 PM PDT 24 |
894500962 ps |
| T723 |
/workspace/coverage/default/46.spi_device_tpm_all.3384131346 |
|
|
Mar 31 02:47:18 PM PDT 24 |
Mar 31 02:47:32 PM PDT 24 |
2668198678 ps |
| T724 |
/workspace/coverage/default/24.spi_device_stress_all.3716539040 |
|
|
Mar 31 02:45:50 PM PDT 24 |
Mar 31 02:45:51 PM PDT 24 |
65772243 ps |
| T725 |
/workspace/coverage/default/28.spi_device_tpm_rw.3327916544 |
|
|
Mar 31 02:46:02 PM PDT 24 |
Mar 31 02:46:04 PM PDT 24 |
742901263 ps |
| T726 |
/workspace/coverage/default/30.spi_device_csb_read.2214577131 |
|
|
Mar 31 02:46:07 PM PDT 24 |
Mar 31 02:46:08 PM PDT 24 |
35642001 ps |
| T727 |
/workspace/coverage/default/15.spi_device_ram_cfg.2501240301 |
|
|
Mar 31 02:44:59 PM PDT 24 |
Mar 31 02:45:00 PM PDT 24 |
16924148 ps |
| T728 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.2406257960 |
|
|
Mar 31 02:47:26 PM PDT 24 |
Mar 31 02:47:27 PM PDT 24 |
42639484 ps |
| T729 |
/workspace/coverage/default/9.spi_device_tpm_sts_read.2926414349 |
|
|
Mar 31 02:44:30 PM PDT 24 |
Mar 31 02:44:31 PM PDT 24 |
108206721 ps |
| T730 |
/workspace/coverage/default/8.spi_device_mailbox.1279947097 |
|
|
Mar 31 02:44:22 PM PDT 24 |
Mar 31 02:44:56 PM PDT 24 |
2920774616 ps |
| T731 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.1952777550 |
|
|
Mar 31 02:45:51 PM PDT 24 |
Mar 31 02:46:02 PM PDT 24 |
1787750418 ps |
| T732 |
/workspace/coverage/default/34.spi_device_csb_read.344091295 |
|
|
Mar 31 02:46:21 PM PDT 24 |
Mar 31 02:46:22 PM PDT 24 |
19346447 ps |
| T733 |
/workspace/coverage/default/32.spi_device_tpm_rw.3065673343 |
|
|
Mar 31 02:46:17 PM PDT 24 |
Mar 31 02:46:22 PM PDT 24 |
327572701 ps |
| T734 |
/workspace/coverage/default/24.spi_device_flash_mode.107207496 |
|
|
Mar 31 02:45:40 PM PDT 24 |
Mar 31 02:46:00 PM PDT 24 |
1778215980 ps |
| T279 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.3059501368 |
|
|
Mar 31 02:45:30 PM PDT 24 |
Mar 31 02:45:39 PM PDT 24 |
858327516 ps |
| T344 |
/workspace/coverage/default/16.spi_device_intercept.2503903772 |
|
|
Mar 31 02:45:05 PM PDT 24 |
Mar 31 02:45:15 PM PDT 24 |
959340728 ps |
| T735 |
/workspace/coverage/default/37.spi_device_tpm_rw.1914218963 |
|
|
Mar 31 02:46:34 PM PDT 24 |
Mar 31 02:46:36 PM PDT 24 |
250138042 ps |
| T736 |
/workspace/coverage/default/19.spi_device_alert_test.3673834446 |
|
|
Mar 31 02:45:17 PM PDT 24 |
Mar 31 02:45:18 PM PDT 24 |
33767696 ps |
| T328 |
/workspace/coverage/default/24.spi_device_cfg_cmd.3823480301 |
|
|
Mar 31 02:45:37 PM PDT 24 |
Mar 31 02:45:40 PM PDT 24 |
108286863 ps |
| T303 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3728525174 |
|
|
Mar 31 02:46:24 PM PDT 24 |
Mar 31 02:46:53 PM PDT 24 |
39448353227 ps |
| T49 |
/workspace/coverage/default/1.spi_device_sec_cm.4070512202 |
|
|
Mar 31 02:43:51 PM PDT 24 |
Mar 31 02:43:52 PM PDT 24 |
134322300 ps |
| T737 |
/workspace/coverage/default/20.spi_device_tpm_all.660523254 |
|
|
Mar 31 02:45:17 PM PDT 24 |
Mar 31 02:45:33 PM PDT 24 |
2101004233 ps |
| T738 |
/workspace/coverage/default/46.spi_device_intercept.1676203921 |
|
|
Mar 31 02:47:20 PM PDT 24 |
Mar 31 02:47:34 PM PDT 24 |
4333741980 ps |
| T739 |
/workspace/coverage/default/24.spi_device_pass_cmd_filtering.3515157910 |
|
|
Mar 31 02:45:39 PM PDT 24 |
Mar 31 02:45:44 PM PDT 24 |
2972979647 ps |
| T740 |
/workspace/coverage/default/28.spi_device_flash_mode.1787431100 |
|
|
Mar 31 02:45:57 PM PDT 24 |
Mar 31 02:46:35 PM PDT 24 |
1751950107 ps |
| T741 |
/workspace/coverage/default/19.spi_device_flash_mode.3724617653 |
|
|
Mar 31 02:45:18 PM PDT 24 |
Mar 31 02:45:44 PM PDT 24 |
788994004 ps |
| T742 |
/workspace/coverage/default/10.spi_device_read_buffer_direct.979830330 |
|
|
Mar 31 02:44:37 PM PDT 24 |
Mar 31 02:44:41 PM PDT 24 |
69435122 ps |
| T743 |
/workspace/coverage/default/45.spi_device_cfg_cmd.2133933290 |
|
|
Mar 31 02:47:20 PM PDT 24 |
Mar 31 02:47:25 PM PDT 24 |
1494383074 ps |
| T304 |
/workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3197486050 |
|
|
Mar 31 02:44:41 PM PDT 24 |
Mar 31 02:44:52 PM PDT 24 |
9714458800 ps |
| T352 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.4098413549 |
|
|
Mar 31 02:47:37 PM PDT 24 |
Mar 31 02:47:40 PM PDT 24 |
1152121403 ps |
| T357 |
/workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2218286186 |
|
|
Mar 31 02:44:00 PM PDT 24 |
Mar 31 02:44:10 PM PDT 24 |
1576271342 ps |
| T744 |
/workspace/coverage/default/6.spi_device_tpm_rw.749565221 |
|
|
Mar 31 02:44:14 PM PDT 24 |
Mar 31 02:44:17 PM PDT 24 |
171258258 ps |
| T404 |
/workspace/coverage/default/2.spi_device_tpm_all.1329833612 |
|
|
Mar 31 02:43:48 PM PDT 24 |
Mar 31 02:44:46 PM PDT 24 |
40356466753 ps |
| T745 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.1746798247 |
|
|
Mar 31 02:44:12 PM PDT 24 |
Mar 31 02:44:13 PM PDT 24 |
29330595 ps |
| T746 |
/workspace/coverage/default/20.spi_device_mailbox.1646626161 |
|
|
Mar 31 02:45:19 PM PDT 24 |
Mar 31 02:45:27 PM PDT 24 |
748172437 ps |
| T747 |
/workspace/coverage/default/35.spi_device_alert_test.3165709073 |
|
|
Mar 31 02:46:34 PM PDT 24 |
Mar 31 02:46:35 PM PDT 24 |
26105823 ps |
| T291 |
/workspace/coverage/default/46.spi_device_pass_cmd_filtering.3888010153 |
|
|
Mar 31 02:47:18 PM PDT 24 |
Mar 31 02:47:27 PM PDT 24 |
2244704115 ps |
| T748 |
/workspace/coverage/default/33.spi_device_tpm_read_hw_reg.934131489 |
|
|
Mar 31 02:46:22 PM PDT 24 |
Mar 31 02:46:26 PM PDT 24 |
1755264759 ps |
| T749 |
/workspace/coverage/default/45.spi_device_csb_read.1153789368 |
|
|
Mar 31 02:47:19 PM PDT 24 |
Mar 31 02:47:19 PM PDT 24 |
19621675 ps |
| T358 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3371902155 |
|
|
Mar 31 02:47:28 PM PDT 24 |
Mar 31 02:47:45 PM PDT 24 |
5316729262 ps |
| T750 |
/workspace/coverage/default/14.spi_device_ram_cfg.4156023961 |
|
|
Mar 31 02:44:57 PM PDT 24 |
Mar 31 02:44:58 PM PDT 24 |
44367476 ps |
| T751 |
/workspace/coverage/default/46.spi_device_flash_mode.3771187639 |
|
|
Mar 31 02:47:21 PM PDT 24 |
Mar 31 02:48:24 PM PDT 24 |
31768334849 ps |
| T351 |
/workspace/coverage/default/13.spi_device_mailbox.4060916250 |
|
|
Mar 31 02:44:50 PM PDT 24 |
Mar 31 02:45:04 PM PDT 24 |
3939512762 ps |
| T284 |
/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.579715136 |
|
|
Mar 31 02:43:53 PM PDT 24 |
Mar 31 02:44:05 PM PDT 24 |
3294114708 ps |
| T752 |
/workspace/coverage/default/22.spi_device_tpm_all.1996530143 |
|
|
Mar 31 02:45:34 PM PDT 24 |
Mar 31 02:45:37 PM PDT 24 |
1498156688 ps |
| T753 |
/workspace/coverage/default/34.spi_device_tpm_rw.3925979978 |
|
|
Mar 31 02:46:27 PM PDT 24 |
Mar 31 02:46:29 PM PDT 24 |
339742842 ps |
| T754 |
/workspace/coverage/default/13.spi_device_flash_mode.3822459941 |
|
|
Mar 31 02:44:49 PM PDT 24 |
Mar 31 02:46:14 PM PDT 24 |
5623632144 ps |
| T339 |
/workspace/coverage/default/33.spi_device_pass_cmd_filtering.774556768 |
|
|
Mar 31 02:46:30 PM PDT 24 |
Mar 31 02:46:36 PM PDT 24 |
2856076599 ps |
| T270 |
/workspace/coverage/default/29.spi_device_mailbox.2532812258 |
|
|
Mar 31 02:45:58 PM PDT 24 |
Mar 31 02:48:52 PM PDT 24 |
21388437114 ps |
| T755 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.579763989 |
|
|
Mar 31 02:46:53 PM PDT 24 |
Mar 31 02:46:54 PM PDT 24 |
23075813 ps |
| T305 |
/workspace/coverage/default/38.spi_device_pass_cmd_filtering.2073493485 |
|
|
Mar 31 02:46:42 PM PDT 24 |
Mar 31 02:46:48 PM PDT 24 |
298029804 ps |
| T756 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.3217423384 |
|
|
Mar 31 02:45:19 PM PDT 24 |
Mar 31 02:45:19 PM PDT 24 |
57184582 ps |
| T338 |
/workspace/coverage/default/10.spi_device_pass_cmd_filtering.2729894254 |
|
|
Mar 31 02:44:34 PM PDT 24 |
Mar 31 02:44:42 PM PDT 24 |
6327636190 ps |
| T234 |
/workspace/coverage/default/31.spi_device_cfg_cmd.1330331573 |
|
|
Mar 31 02:46:10 PM PDT 24 |
Mar 31 02:46:16 PM PDT 24 |
332473332 ps |
| T312 |
/workspace/coverage/default/49.spi_device_flash_mode.3202860657 |
|
|
Mar 31 02:47:38 PM PDT 24 |
Mar 31 02:47:57 PM PDT 24 |
2968912029 ps |
| T757 |
/workspace/coverage/default/23.spi_device_tpm_all.422067644 |
|
|
Mar 31 02:45:40 PM PDT 24 |
Mar 31 02:45:56 PM PDT 24 |
5364192540 ps |
| T758 |
/workspace/coverage/default/29.spi_device_tpm_all.1532472065 |
|
|
Mar 31 02:46:01 PM PDT 24 |
Mar 31 02:46:07 PM PDT 24 |
664076730 ps |
| T759 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.956744176 |
|
|
Mar 31 02:45:25 PM PDT 24 |
Mar 31 02:45:30 PM PDT 24 |
950900554 ps |
| T760 |
/workspace/coverage/default/0.spi_device_tpm_rw.3189843754 |
|
|
Mar 31 02:43:40 PM PDT 24 |
Mar 31 02:43:43 PM PDT 24 |
150363435 ps |
| T761 |
/workspace/coverage/default/43.spi_device_tpm_all.1039305355 |
|
|
Mar 31 02:47:04 PM PDT 24 |
Mar 31 02:47:37 PM PDT 24 |
3567568047 ps |
| T306 |
/workspace/coverage/default/48.spi_device_intercept.1857561110 |
|
|
Mar 31 02:47:33 PM PDT 24 |
Mar 31 02:48:09 PM PDT 24 |
18359607106 ps |
| T762 |
/workspace/coverage/default/6.spi_device_read_buffer_direct.1639539601 |
|
|
Mar 31 02:44:16 PM PDT 24 |
Mar 31 02:44:23 PM PDT 24 |
2349341150 ps |
| T763 |
/workspace/coverage/default/41.spi_device_tpm_rw.3413597014 |
|
|
Mar 31 02:46:58 PM PDT 24 |
Mar 31 02:46:59 PM PDT 24 |
38842110 ps |
| T764 |
/workspace/coverage/default/8.spi_device_flash_mode.3062208044 |
|
|
Mar 31 02:44:22 PM PDT 24 |
Mar 31 02:46:00 PM PDT 24 |
7366986035 ps |
| T765 |
/workspace/coverage/default/11.spi_device_ram_cfg.2618035763 |
|
|
Mar 31 02:44:40 PM PDT 24 |
Mar 31 02:44:41 PM PDT 24 |
41658462 ps |
| T766 |
/workspace/coverage/default/14.spi_device_tpm_all.209814871 |
|
|
Mar 31 02:44:56 PM PDT 24 |
Mar 31 02:45:03 PM PDT 24 |
452928815 ps |
| T50 |
/workspace/coverage/default/2.spi_device_sec_cm.2151836993 |
|
|
Mar 31 02:43:55 PM PDT 24 |
Mar 31 02:43:56 PM PDT 24 |
79123740 ps |
| T767 |
/workspace/coverage/default/39.spi_device_read_buffer_direct.3094245443 |
|
|
Mar 31 02:46:48 PM PDT 24 |
Mar 31 02:46:58 PM PDT 24 |
7333927825 ps |
| T331 |
/workspace/coverage/default/39.spi_device_pass_cmd_filtering.1246518335 |
|
|
Mar 31 02:46:52 PM PDT 24 |
Mar 31 02:46:56 PM PDT 24 |
1061375707 ps |
| T768 |
/workspace/coverage/default/44.spi_device_tpm_rw.2273902999 |
|
|
Mar 31 02:47:11 PM PDT 24 |
Mar 31 02:47:13 PM PDT 24 |
125247470 ps |
| T294 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1666194136 |
|
|
Mar 31 02:45:53 PM PDT 24 |
Mar 31 02:46:01 PM PDT 24 |
3680474072 ps |
| T271 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1605225192 |
|
|
Mar 31 02:46:05 PM PDT 24 |
Mar 31 02:46:28 PM PDT 24 |
20024480430 ps |
| T769 |
/workspace/coverage/default/20.spi_device_intercept.1801255619 |
|
|
Mar 31 02:45:17 PM PDT 24 |
Mar 31 02:45:20 PM PDT 24 |
624094893 ps |
| T367 |
/workspace/coverage/default/40.spi_device_flash_mode.397034492 |
|
|
Mar 31 02:46:53 PM PDT 24 |
Mar 31 02:47:10 PM PDT 24 |
1001972742 ps |
| T349 |
/workspace/coverage/default/33.spi_device_mailbox.2006517852 |
|
|
Mar 31 02:46:32 PM PDT 24 |
Mar 31 02:46:53 PM PDT 24 |
1581277090 ps |
| T770 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.3785730694 |
|
|
Mar 31 02:45:38 PM PDT 24 |
Mar 31 02:45:39 PM PDT 24 |
186278354 ps |
| T212 |
/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2571335845 |
|
|
Mar 31 02:44:34 PM PDT 24 |
Mar 31 02:45:02 PM PDT 24 |
41123746400 ps |
| T771 |
/workspace/coverage/default/2.spi_device_tpm_rw.2849208061 |
|
|
Mar 31 02:43:50 PM PDT 24 |
Mar 31 02:43:55 PM PDT 24 |
2322896957 ps |
| T772 |
/workspace/coverage/default/16.spi_device_mem_parity.3376099591 |
|
|
Mar 31 02:45:01 PM PDT 24 |
Mar 31 02:45:02 PM PDT 24 |
47325139 ps |
| T178 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3600593669 |
|
|
Mar 31 12:39:49 PM PDT 24 |
Mar 31 12:39:50 PM PDT 24 |
30208584 ps |
| T35 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.545297223 |
|
|
Mar 31 12:39:53 PM PDT 24 |
Mar 31 12:39:55 PM PDT 24 |
392951873 ps |
| T36 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2174226289 |
|
|
Mar 31 12:39:22 PM PDT 24 |
Mar 31 12:39:45 PM PDT 24 |
1008708555 ps |
| T773 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.4138634288 |
|
|
Mar 31 12:39:53 PM PDT 24 |
Mar 31 12:39:54 PM PDT 24 |
56749667 ps |
| T125 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3803610830 |
|
|
Mar 31 12:39:45 PM PDT 24 |
Mar 31 12:39:46 PM PDT 24 |
78834581 ps |
| T140 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2290520051 |
|
|
Mar 31 12:39:34 PM PDT 24 |
Mar 31 12:39:36 PM PDT 24 |
114185602 ps |
| T37 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3984631555 |
|
|
Mar 31 12:39:18 PM PDT 24 |
Mar 31 12:39:20 PM PDT 24 |
50427220 ps |
| T179 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.2694544457 |
|
|
Mar 31 12:39:56 PM PDT 24 |
Mar 31 12:39:57 PM PDT 24 |
26379550 ps |
| T126 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1191125123 |
|
|
Mar 31 12:39:55 PM PDT 24 |
Mar 31 12:39:57 PM PDT 24 |
65913260 ps |
| T163 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1277553848 |
|
|
Mar 31 12:39:49 PM PDT 24 |
Mar 31 12:39:58 PM PDT 24 |
590079548 ps |
| T127 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.252755623 |
|
|
Mar 31 12:39:31 PM PDT 24 |
Mar 31 12:39:32 PM PDT 24 |
92520626 ps |
| T774 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.845644389 |
|
|
Mar 31 12:39:22 PM PDT 24 |
Mar 31 12:39:23 PM PDT 24 |
15865816 ps |
| T145 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2841573319 |
|
|
Mar 31 12:39:46 PM PDT 24 |
Mar 31 12:39:48 PM PDT 24 |
48626250 ps |
| T171 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4021700874 |
|
|
Mar 31 12:39:30 PM PDT 24 |
Mar 31 12:39:38 PM PDT 24 |
1389969175 ps |
| T149 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.194845924 |
|
|
Mar 31 12:39:29 PM PDT 24 |
Mar 31 12:39:32 PM PDT 24 |
401373398 ps |
| T164 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3263217308 |
|
|
Mar 31 12:39:41 PM PDT 24 |
Mar 31 12:39:44 PM PDT 24 |
113690155 ps |
| T775 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.1062438559 |
|
|
Mar 31 12:39:25 PM PDT 24 |
Mar 31 12:39:31 PM PDT 24 |
15263368 ps |
| T776 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2055339772 |
|
|
Mar 31 12:39:19 PM PDT 24 |
Mar 31 12:39:20 PM PDT 24 |
25888504 ps |
| T131 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2693571558 |
|
|
Mar 31 12:39:46 PM PDT 24 |
Mar 31 12:40:10 PM PDT 24 |
2172234262 ps |
| T133 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3380208271 |
|
|
Mar 31 12:39:23 PM PDT 24 |
Mar 31 12:39:25 PM PDT 24 |
66342558 ps |
| T150 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.338300129 |
|
|
Mar 31 12:39:34 PM PDT 24 |
Mar 31 12:39:35 PM PDT 24 |
60919997 ps |
| T165 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1710540690 |
|
|
Mar 31 12:39:23 PM PDT 24 |
Mar 31 12:39:26 PM PDT 24 |
823780491 ps |
| T132 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3947294907 |
|
|
Mar 31 12:39:39 PM PDT 24 |
Mar 31 12:39:58 PM PDT 24 |
306169819 ps |
| T166 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2585261595 |
|
|
Mar 31 12:39:45 PM PDT 24 |
Mar 31 12:39:49 PM PDT 24 |
64416867 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1697336259 |
|
|
Mar 31 12:39:57 PM PDT 24 |
Mar 31 12:40:00 PM PDT 24 |
343414759 ps |
| T151 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1784100107 |
|
|
Mar 31 12:39:24 PM PDT 24 |
Mar 31 12:39:27 PM PDT 24 |
279823797 ps |
| T777 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2692460154 |
|
|
Mar 31 12:39:50 PM PDT 24 |
Mar 31 12:39:51 PM PDT 24 |
41271227 ps |
| T180 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.1766008859 |
|
|
Mar 31 12:39:51 PM PDT 24 |
Mar 31 12:39:52 PM PDT 24 |
126652471 ps |
| T134 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3879862305 |
|
|
Mar 31 12:39:57 PM PDT 24 |
Mar 31 12:40:02 PM PDT 24 |
131761720 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2269453353 |
|
|
Mar 31 12:39:18 PM PDT 24 |
Mar 31 12:39:24 PM PDT 24 |
59194203 ps |
| T152 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3542913554 |
|
|
Mar 31 12:39:30 PM PDT 24 |
Mar 31 12:39:33 PM PDT 24 |
242072266 ps |
| T146 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1567649707 |
|
|
Mar 31 12:39:48 PM PDT 24 |
Mar 31 12:40:01 PM PDT 24 |
2742892790 ps |
| T778 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3158139735 |
|
|
Mar 31 12:39:18 PM PDT 24 |
Mar 31 12:39:19 PM PDT 24 |
12955832 ps |
| T147 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2658824859 |
|
|
Mar 31 12:39:49 PM PDT 24 |
Mar 31 12:39:51 PM PDT 24 |
101062488 ps |
| T379 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2757900052 |
|
|
Mar 31 12:39:57 PM PDT 24 |
Mar 31 12:40:09 PM PDT 24 |
417635485 ps |
| T172 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1889443397 |
|
|
Mar 31 12:39:39 PM PDT 24 |
Mar 31 12:39:42 PM PDT 24 |
102127200 ps |
| T779 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1056079524 |
|
|
Mar 31 12:39:28 PM PDT 24 |
Mar 31 12:39:29 PM PDT 24 |
50000978 ps |
| T383 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.729085008 |
|
|
Mar 31 12:39:22 PM PDT 24 |
Mar 31 12:39:29 PM PDT 24 |
1145242465 ps |
| T153 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2657936519 |
|
|
Mar 31 12:39:25 PM PDT 24 |
Mar 31 12:39:27 PM PDT 24 |
325820741 ps |
| T135 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2414729827 |
|
|
Mar 31 12:39:46 PM PDT 24 |
Mar 31 12:39:50 PM PDT 24 |
107185550 ps |
| T780 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2584191899 |
|
|
Mar 31 12:39:18 PM PDT 24 |
Mar 31 12:39:30 PM PDT 24 |
364916448 ps |
| T154 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4084656829 |
|
|
Mar 31 12:39:21 PM PDT 24 |
Mar 31 12:39:45 PM PDT 24 |
2448915073 ps |
| T781 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.623158239 |
|
|
Mar 31 12:39:23 PM PDT 24 |
Mar 31 12:39:24 PM PDT 24 |
51990057 ps |