Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.14 97.56 92.92 98.61 80.85 95.95 90.92 88.18


Total test records in report: 882
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T782 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4062237065 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:25 PM PDT 24 268666986 ps
T783 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1667528069 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:27 PM PDT 24 59904120 ps
T173 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.227177712 Mar 31 12:39:32 PM PDT 24 Mar 31 12:39:34 PM PDT 24 225931819 ps
T784 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3750357340 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:28 PM PDT 24 238579708 ps
T785 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2974903278 Mar 31 12:39:28 PM PDT 24 Mar 31 12:39:32 PM PDT 24 692487760 ps
T786 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3324392947 Mar 31 12:39:59 PM PDT 24 Mar 31 12:40:00 PM PDT 24 35582578 ps
T787 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1439316288 Mar 31 12:39:57 PM PDT 24 Mar 31 12:39:58 PM PDT 24 23027534 ps
T788 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3940764649 Mar 31 12:39:42 PM PDT 24 Mar 31 12:39:43 PM PDT 24 24894881 ps
T789 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3738103711 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:24 PM PDT 24 19475023 ps
T155 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.601162924 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:53 PM PDT 24 1808933333 ps
T790 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3092113271 Mar 31 12:39:21 PM PDT 24 Mar 31 12:39:21 PM PDT 24 19484508 ps
T791 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2868539911 Mar 31 12:39:34 PM PDT 24 Mar 31 12:39:35 PM PDT 24 16555517 ps
T792 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4001489399 Mar 31 12:39:56 PM PDT 24 Mar 31 12:39:57 PM PDT 24 41952095 ps
T793 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2642593002 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:20 PM PDT 24 62132063 ps
T794 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1995221968 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:52 PM PDT 24 102506585 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1818438484 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:24 PM PDT 24 77322697 ps
T174 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2083204257 Mar 31 12:39:38 PM PDT 24 Mar 31 12:39:47 PM PDT 24 2064420061 ps
T795 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.563057659 Mar 31 12:39:15 PM PDT 24 Mar 31 12:39:16 PM PDT 24 10696020 ps
T796 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.738930019 Mar 31 12:39:47 PM PDT 24 Mar 31 12:39:49 PM PDT 24 60557232 ps
T797 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1830120605 Mar 31 12:40:02 PM PDT 24 Mar 31 12:40:03 PM PDT 24 22369366 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2090106958 Mar 31 12:39:22 PM PDT 24 Mar 31 12:39:27 PM PDT 24 177806293 ps
T382 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3166944897 Mar 31 12:39:16 PM PDT 24 Mar 31 12:39:29 PM PDT 24 2414019235 ps
T378 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2828500369 Mar 31 12:39:24 PM PDT 24 Mar 31 12:39:44 PM PDT 24 1222506196 ps
T798 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.130553088 Mar 31 12:39:47 PM PDT 24 Mar 31 12:39:48 PM PDT 24 15988318 ps
T156 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3327278789 Mar 31 12:39:45 PM PDT 24 Mar 31 12:39:48 PM PDT 24 147288067 ps
T799 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.298723066 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:21 PM PDT 24 157277998 ps
T800 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1903327773 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:50 PM PDT 24 40761333 ps
T801 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4132964293 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:49 PM PDT 24 16563085 ps
T802 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2792702383 Mar 31 12:39:36 PM PDT 24 Mar 31 12:39:38 PM PDT 24 94040744 ps
T175 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.493431510 Mar 31 12:39:52 PM PDT 24 Mar 31 12:39:55 PM PDT 24 561583779 ps
T803 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.102385345 Mar 31 12:39:58 PM PDT 24 Mar 31 12:39:59 PM PDT 24 38334603 ps
T804 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1828858377 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:50 PM PDT 24 20814236 ps
T805 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3650560767 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:48 PM PDT 24 5240892982 ps
T806 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4074908905 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:19 PM PDT 24 227260738 ps
T157 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1443865967 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:20 PM PDT 24 29036274 ps
T807 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.836243438 Mar 31 12:39:21 PM PDT 24 Mar 31 12:39:22 PM PDT 24 69766893 ps
T808 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.671647514 Mar 31 12:39:39 PM PDT 24 Mar 31 12:39:40 PM PDT 24 55704588 ps
T809 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4291894331 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:50 PM PDT 24 156263663 ps
T176 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3508806050 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:28 PM PDT 24 182152990 ps
T810 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.161085586 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:51 PM PDT 24 16721550 ps
T376 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.384040949 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:51 PM PDT 24 210464993 ps
T811 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2441182270 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:41 PM PDT 24 1243856263 ps
T158 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2073597605 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:32 PM PDT 24 92810993 ps
T144 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2459300340 Mar 31 12:39:40 PM PDT 24 Mar 31 12:39:41 PM PDT 24 98485407 ps
T141 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3123238582 Mar 31 12:39:44 PM PDT 24 Mar 31 12:39:47 PM PDT 24 134179487 ps
T812 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1928616776 Mar 31 12:39:26 PM PDT 24 Mar 31 12:39:27 PM PDT 24 35393024 ps
T137 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2000294280 Mar 31 12:39:18 PM PDT 24 Mar 31 12:39:20 PM PDT 24 109613791 ps
T138 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4289293610 Mar 31 12:39:34 PM PDT 24 Mar 31 12:39:37 PM PDT 24 129896951 ps
T159 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.374285077 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:51 PM PDT 24 103104654 ps
T813 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1482421667 Mar 31 12:39:54 PM PDT 24 Mar 31 12:39:55 PM PDT 24 13228680 ps
T160 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3510255740 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:46 PM PDT 24 920014475 ps
T814 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1226969479 Mar 31 12:39:46 PM PDT 24 Mar 31 12:39:48 PM PDT 24 464192659 ps
T815 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3828221049 Mar 31 12:39:54 PM PDT 24 Mar 31 12:39:58 PM PDT 24 347635145 ps
T816 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2812038993 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:50 PM PDT 24 13575793 ps
T817 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2089577102 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:51 PM PDT 24 205969861 ps
T818 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.638638242 Mar 31 12:40:06 PM PDT 24 Mar 31 12:40:08 PM PDT 24 13272272 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2633384149 Mar 31 12:39:22 PM PDT 24 Mar 31 12:39:24 PM PDT 24 99077743 ps
T142 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4223908438 Mar 31 12:39:26 PM PDT 24 Mar 31 12:39:30 PM PDT 24 566396665 ps
T819 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2047475349 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:51 PM PDT 24 527188462 ps
T820 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.327585813 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:33 PM PDT 24 2358798696 ps
T821 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1469472470 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:18 PM PDT 24 36287702 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.768486715 Mar 31 12:39:10 PM PDT 24 Mar 31 12:39:11 PM PDT 24 92779268 ps
T822 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3967617924 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:30 PM PDT 24 188051847 ps
T823 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.866824854 Mar 31 12:39:44 PM PDT 24 Mar 31 12:39:48 PM PDT 24 170071958 ps
T824 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2322792837 Mar 31 12:39:49 PM PDT 24 Mar 31 12:39:50 PM PDT 24 44937951 ps
T162 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1077976924 Mar 31 12:39:20 PM PDT 24 Mar 31 12:39:34 PM PDT 24 787230298 ps
T825 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1092674800 Mar 31 12:39:15 PM PDT 24 Mar 31 12:39:17 PM PDT 24 24337031 ps
T826 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3972472610 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:49 PM PDT 24 30229830 ps
T827 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3648744535 Mar 31 12:39:40 PM PDT 24 Mar 31 12:39:44 PM PDT 24 194312415 ps
T828 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4148863174 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:21 PM PDT 24 55765142 ps
T829 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1753095112 Mar 31 12:39:38 PM PDT 24 Mar 31 12:39:45 PM PDT 24 443581472 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.990337663 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:27 PM PDT 24 209823770 ps
T830 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1613215701 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:53 PM PDT 24 36916150 ps
T831 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1015673823 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:51 PM PDT 24 39540250 ps
T832 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1008067928 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:49 PM PDT 24 15470215 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.185852259 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:19 PM PDT 24 77826096 ps
T833 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2040194041 Mar 31 12:39:56 PM PDT 24 Mar 31 12:39:58 PM PDT 24 546828186 ps
T834 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.799420701 Mar 31 12:39:54 PM PDT 24 Mar 31 12:39:57 PM PDT 24 106399463 ps
T835 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3010067104 Mar 31 12:39:43 PM PDT 24 Mar 31 12:39:44 PM PDT 24 42618520 ps
T836 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3998432059 Mar 31 12:39:35 PM PDT 24 Mar 31 12:39:37 PM PDT 24 503160772 ps
T837 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.788840572 Mar 31 12:39:58 PM PDT 24 Mar 31 12:39:59 PM PDT 24 36361587 ps
T838 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1237081157 Mar 31 12:39:21 PM PDT 24 Mar 31 12:39:23 PM PDT 24 74353216 ps
T385 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.214980448 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:47 PM PDT 24 1594333956 ps
T839 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3428962819 Mar 31 12:39:36 PM PDT 24 Mar 31 12:39:38 PM PDT 24 28719676 ps
T840 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.336957601 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:51 PM PDT 24 324433891 ps
T841 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1486345827 Mar 31 12:39:54 PM PDT 24 Mar 31 12:39:55 PM PDT 24 21483754 ps
T842 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.883305246 Mar 31 12:39:55 PM PDT 24 Mar 31 12:39:56 PM PDT 24 40747003 ps
T843 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.771085566 Mar 31 12:39:17 PM PDT 24 Mar 31 12:39:19 PM PDT 24 916788928 ps
T844 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3757668517 Mar 31 12:40:00 PM PDT 24 Mar 31 12:40:01 PM PDT 24 12701520 ps
T845 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2397126681 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:35 PM PDT 24 638754514 ps
T381 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.614368424 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:53 PM PDT 24 832986303 ps
T377 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1220524635 Mar 31 12:39:55 PM PDT 24 Mar 31 12:40:00 PM PDT 24 747571741 ps
T846 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.249695555 Mar 31 12:39:40 PM PDT 24 Mar 31 12:39:42 PM PDT 24 126337820 ps
T847 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1280770421 Mar 31 12:39:42 PM PDT 24 Mar 31 12:39:59 PM PDT 24 2906551233 ps
T848 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2201108854 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:20 PM PDT 24 67437042 ps
T849 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3357111625 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:34 PM PDT 24 519112380 ps
T850 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3957427165 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:21 PM PDT 24 229535999 ps
T851 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1941918866 Mar 31 12:39:22 PM PDT 24 Mar 31 12:39:23 PM PDT 24 12311191 ps
T852 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3043987016 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:27 PM PDT 24 326495106 ps
T853 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.502056396 Mar 31 12:39:31 PM PDT 24 Mar 31 12:39:33 PM PDT 24 232089610 ps
T386 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1939882775 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:47 PM PDT 24 1145531588 ps
T854 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.626004232 Mar 31 12:39:48 PM PDT 24 Mar 31 12:39:51 PM PDT 24 90601238 ps
T855 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2822311560 Mar 31 12:39:53 PM PDT 24 Mar 31 12:39:54 PM PDT 24 33471822 ps
T856 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2671910060 Mar 31 12:39:51 PM PDT 24 Mar 31 12:39:51 PM PDT 24 18155566 ps
T857 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3517510301 Mar 31 12:39:18 PM PDT 24 Mar 31 12:39:19 PM PDT 24 27032035 ps
T858 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2906107374 Mar 31 12:39:24 PM PDT 24 Mar 31 12:39:25 PM PDT 24 21510774 ps
T859 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.949802794 Mar 31 12:39:30 PM PDT 24 Mar 31 12:39:33 PM PDT 24 37994553 ps
T860 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.976612999 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:27 PM PDT 24 91787072 ps
T861 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.93617590 Mar 31 12:39:57 PM PDT 24 Mar 31 12:39:58 PM PDT 24 162583184 ps
T862 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1622361456 Mar 31 12:39:19 PM PDT 24 Mar 31 12:39:22 PM PDT 24 98736235 ps
T863 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2547674518 Mar 31 12:39:24 PM PDT 24 Mar 31 12:39:25 PM PDT 24 52603208 ps
T864 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2614817974 Mar 31 12:39:22 PM PDT 24 Mar 31 12:39:25 PM PDT 24 498164100 ps
T865 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1332702428 Mar 31 12:40:00 PM PDT 24 Mar 31 12:40:01 PM PDT 24 30265467 ps
T866 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.12474545 Mar 31 12:39:53 PM PDT 24 Mar 31 12:39:55 PM PDT 24 100937807 ps
T867 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3396224610 Mar 31 12:39:41 PM PDT 24 Mar 31 12:39:45 PM PDT 24 160627319 ps
T868 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.719804205 Mar 31 12:39:41 PM PDT 24 Mar 31 12:39:44 PM PDT 24 103520735 ps
T869 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3420202939 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:38 PM PDT 24 3077538897 ps
T870 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1363138412 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:24 PM PDT 24 53960838 ps
T871 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2964196126 Mar 31 12:39:56 PM PDT 24 Mar 31 12:39:59 PM PDT 24 134546546 ps
T872 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2094178792 Mar 31 12:39:44 PM PDT 24 Mar 31 12:39:45 PM PDT 24 12509300 ps
T873 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.377865730 Mar 31 12:39:50 PM PDT 24 Mar 31 12:39:50 PM PDT 24 18365114 ps
T874 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2524442709 Mar 31 12:39:34 PM PDT 24 Mar 31 12:39:36 PM PDT 24 25547574 ps
T380 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4288563343 Mar 31 12:39:49 PM PDT 24 Mar 31 12:40:02 PM PDT 24 394371817 ps
T875 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2784174658 Mar 31 12:39:39 PM PDT 24 Mar 31 12:39:46 PM PDT 24 554203784 ps
T876 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.676681027 Mar 31 12:39:21 PM PDT 24 Mar 31 12:39:23 PM PDT 24 35295896 ps
T877 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.551944692 Mar 31 12:39:29 PM PDT 24 Mar 31 12:39:30 PM PDT 24 13399853 ps
T878 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1325723614 Mar 31 12:39:57 PM PDT 24 Mar 31 12:39:59 PM PDT 24 143266425 ps
T879 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.144095885 Mar 31 12:39:25 PM PDT 24 Mar 31 12:39:30 PM PDT 24 135548136 ps
T880 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3070165040 Mar 31 12:39:23 PM PDT 24 Mar 31 12:39:24 PM PDT 24 34042310 ps
T384 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2937970897 Mar 31 12:39:46 PM PDT 24 Mar 31 12:40:08 PM PDT 24 909119559 ps
T881 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2367340446 Mar 31 12:39:51 PM PDT 24 Mar 31 12:39:51 PM PDT 24 52378592 ps
T882 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.595127977 Mar 31 12:39:45 PM PDT 24 Mar 31 12:39:46 PM PDT 24 13009343 ps

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.329840433
Short name T4
Test name
Test status
Simulation time 882514632 ps
CPU time 9.6 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:22 PM PDT 24
Peak memory 223268 kb
Host smart-49e45d93-7733-47a4-b977-8c5fdd1dcd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329840433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.329840433
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3332776890
Short name T13
Test name
Test status
Simulation time 3673459088 ps
CPU time 29.01 seconds
Started Mar 31 02:47:22 PM PDT 24
Finished Mar 31 02:47:51 PM PDT 24
Peak memory 216660 kb
Host smart-f5ffbdac-e818-4500-9735-ddf695c814bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332776890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3332776890
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2490908689
Short name T105
Test name
Test status
Simulation time 3292076384 ps
CPU time 45.1 seconds
Started Mar 31 02:44:31 PM PDT 24
Finished Mar 31 02:45:16 PM PDT 24
Peak memory 238208 kb
Host smart-2d195f47-d4a3-4145-b1ba-99c75bba8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490908689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2490908689
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2239988204
Short name T108
Test name
Test status
Simulation time 13751058485 ps
CPU time 23.02 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:44:06 PM PDT 24
Peak memory 222892 kb
Host smart-8f2033a8-441a-43ad-9696-fd65fb550e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239988204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2239988204
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2174226289
Short name T36
Test name
Test status
Simulation time 1008708555 ps
CPU time 22.74 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 221152 kb
Host smart-fca910de-fa5a-442e-a40d-a9f76de10fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174226289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2174226289
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1091145692
Short name T52
Test name
Test status
Simulation time 53868838 ps
CPU time 1.2 seconds
Started Mar 31 02:46:02 PM PDT 24
Finished Mar 31 02:46:03 PM PDT 24
Peak memory 207796 kb
Host smart-451c17bc-b037-4a2b-88b2-7f71b53b8b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091145692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1091145692
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2660873984
Short name T5
Test name
Test status
Simulation time 1460225635 ps
CPU time 10.11 seconds
Started Mar 31 02:45:18 PM PDT 24
Finished Mar 31 02:45:29 PM PDT 24
Peak memory 216692 kb
Host smart-d9ee5637-b348-4ab4-b464-05117af5d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660873984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2660873984
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.907930506
Short name T397
Test name
Test status
Simulation time 8304225949 ps
CPU time 44.07 seconds
Started Mar 31 02:43:42 PM PDT 24
Finished Mar 31 02:44:26 PM PDT 24
Peak memory 218872 kb
Host smart-7af49674-dd56-4a36-9a43-8765150c00f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907930506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.907930506
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2470201362
Short name T80
Test name
Test status
Simulation time 74314016726 ps
CPU time 55.87 seconds
Started Mar 31 02:43:38 PM PDT 24
Finished Mar 31 02:44:35 PM PDT 24
Peak memory 231040 kb
Host smart-0a1f7086-ba40-4c11-83c3-c423b83436c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470201362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2470201362
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3025488318
Short name T124
Test name
Test status
Simulation time 1756759519 ps
CPU time 12.04 seconds
Started Mar 31 02:45:54 PM PDT 24
Finished Mar 31 02:46:06 PM PDT 24
Peak memory 232844 kb
Host smart-d6235717-b1d9-44e2-96eb-480526522d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025488318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3025488318
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.830469709
Short name T39
Test name
Test status
Simulation time 46008507 ps
CPU time 0.71 seconds
Started Mar 31 02:43:40 PM PDT 24
Finished Mar 31 02:43:41 PM PDT 24
Peak memory 216300 kb
Host smart-a41934c1-18ff-4fa6-bce0-84daa9b9de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830469709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.830469709
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4053051643
Short name T393
Test name
Test status
Simulation time 18966202821 ps
CPU time 52.64 seconds
Started Mar 31 02:46:46 PM PDT 24
Finished Mar 31 02:47:39 PM PDT 24
Peak memory 216492 kb
Host smart-b4682dbb-bb31-4a58-b51e-707ffe00e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053051643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4053051643
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3699522946
Short name T25
Test name
Test status
Simulation time 72328369 ps
CPU time 3.05 seconds
Started Mar 31 02:47:07 PM PDT 24
Finished Mar 31 02:47:11 PM PDT 24
Peak memory 223064 kb
Host smart-0bc783f6-55e3-4cad-93b2-88fd5c2c03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699522946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3699522946
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_intercept.793846842
Short name T130
Test name
Test status
Simulation time 2441097857 ps
CPU time 7.29 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:19 PM PDT 24
Peak memory 232824 kb
Host smart-511210e7-86ab-40b6-bb87-4054fa6809cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793846842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.793846842
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.35664068
Short name T272
Test name
Test status
Simulation time 4038648133 ps
CPU time 35.34 seconds
Started Mar 31 02:44:28 PM PDT 24
Finished Mar 31 02:45:03 PM PDT 24
Peak memory 220664 kb
Host smart-144580b9-153b-4041-9cbc-178cad311db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35664068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.35664068
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4056339732
Short name T70
Test name
Test status
Simulation time 4718055388 ps
CPU time 11.43 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:29 PM PDT 24
Peak memory 232644 kb
Host smart-069ceae5-414f-4c88-8ccb-c6cd7661286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056339732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4056339732
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3879862305
Short name T134
Test name
Test status
Simulation time 131761720 ps
CPU time 4.66 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:40:02 PM PDT 24
Peak memory 215628 kb
Host smart-53f1c1a5-d998-43e0-a925-ec3bde60f6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879862305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3879862305
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4241655489
Short name T29
Test name
Test status
Simulation time 18241806 ps
CPU time 0.71 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 205708 kb
Host smart-771a10b0-d5e1-4204-9464-2f3066f1befc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241655489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4241655489
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3079364953
Short name T244
Test name
Test status
Simulation time 6530732209 ps
CPU time 21.64 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 232840 kb
Host smart-7f4fea82-c5f5-40da-833e-a5c63f56a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079364953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3079364953
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2155555942
Short name T85
Test name
Test status
Simulation time 17879286711 ps
CPU time 14.07 seconds
Started Mar 31 02:44:32 PM PDT 24
Finished Mar 31 02:44:46 PM PDT 24
Peak memory 216792 kb
Host smart-188aff18-7081-4236-b9b5-330ea36f9e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155555942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2155555942
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.338300129
Short name T150
Test name
Test status
Simulation time 60919997 ps
CPU time 1.24 seconds
Started Mar 31 12:39:34 PM PDT 24
Finished Mar 31 12:39:35 PM PDT 24
Peak memory 207300 kb
Host smart-7830727b-c4ec-4ed2-b59c-15de911d1445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338300129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.338300129
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2286017918
Short name T77
Test name
Test status
Simulation time 552037366 ps
CPU time 5.68 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:45:13 PM PDT 24
Peak memory 221212 kb
Host smart-a3860036-297b-44ee-8601-44ab94ff6b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286017918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2286017918
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3329514175
Short name T1
Test name
Test status
Simulation time 4837416355 ps
CPU time 49.5 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:47:46 PM PDT 24
Peak memory 218512 kb
Host smart-fac0298a-f77c-4064-8fe5-05680713e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329514175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3329514175
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.365421205
Short name T204
Test name
Test status
Simulation time 3468099166 ps
CPU time 7.72 seconds
Started Mar 31 02:44:27 PM PDT 24
Finished Mar 31 02:44:35 PM PDT 24
Peak memory 224196 kb
Host smart-7141f1c3-6435-4e0b-8017-0aea0edd62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365421205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.365421205
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1504489450
Short name T202
Test name
Test status
Simulation time 57371078079 ps
CPU time 11.35 seconds
Started Mar 31 02:45:01 PM PDT 24
Finished Mar 31 02:45:12 PM PDT 24
Peak memory 221700 kb
Host smart-037c8e39-50e7-486d-aa84-93b754910096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504489450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1504489450
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1834201585
Short name T392
Test name
Test status
Simulation time 15840220818 ps
CPU time 79.82 seconds
Started Mar 31 02:44:01 PM PDT 24
Finished Mar 31 02:45:21 PM PDT 24
Peak memory 216488 kb
Host smart-de925e88-40b1-4111-bcef-3448e1ad3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834201585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1834201585
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.728404224
Short name T290
Test name
Test status
Simulation time 41481006119 ps
CPU time 113.39 seconds
Started Mar 31 02:45:19 PM PDT 24
Finished Mar 31 02:47:13 PM PDT 24
Peak memory 224604 kb
Host smart-90ff75bf-bc38-4683-8b67-69000abe8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728404224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.728404224
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3556066837
Short name T223
Test name
Test status
Simulation time 1522845569 ps
CPU time 8.78 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 233940 kb
Host smart-2503c423-9d1f-4d31-bec3-23f4677ca27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556066837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3556066837
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.493632189
Short name T72
Test name
Test status
Simulation time 2009346111 ps
CPU time 13.62 seconds
Started Mar 31 02:45:57 PM PDT 24
Finished Mar 31 02:46:11 PM PDT 24
Peak memory 240028 kb
Host smart-67d8724f-09d4-4024-8f7a-4281c9cbb6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493632189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.493632189
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2144657287
Short name T81
Test name
Test status
Simulation time 904711310 ps
CPU time 6.66 seconds
Started Mar 31 02:46:58 PM PDT 24
Finished Mar 31 02:47:05 PM PDT 24
Peak memory 222500 kb
Host smart-69e852db-2625-4db1-8c4a-ee4f5ebbee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144657287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2144657287
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1605225192
Short name T271
Test name
Test status
Simulation time 20024480430 ps
CPU time 22.5 seconds
Started Mar 31 02:46:05 PM PDT 24
Finished Mar 31 02:46:28 PM PDT 24
Peak memory 232760 kb
Host smart-3bbec6c3-d03d-4890-8e51-540cf7e35332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605225192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1605225192
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3860759878
Short name T34
Test name
Test status
Simulation time 231212568 ps
CPU time 1.1 seconds
Started Mar 31 02:43:45 PM PDT 24
Finished Mar 31 02:43:46 PM PDT 24
Peak memory 216824 kb
Host smart-9a2c00f5-4816-4950-aa9e-ed8da92dc81c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860759878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3860759878
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3197486050
Short name T304
Test name
Test status
Simulation time 9714458800 ps
CPU time 10.2 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:44:52 PM PDT 24
Peak memory 224580 kb
Host smart-e905dc7b-ea7e-47c8-a20e-0dca592e200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197486050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3197486050
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1414477444
Short name T60
Test name
Test status
Simulation time 4013667268 ps
CPU time 8.84 seconds
Started Mar 31 02:44:53 PM PDT 24
Finished Mar 31 02:45:02 PM PDT 24
Peak memory 216356 kb
Host smart-43297a3a-602a-41b7-a54a-3fb2c9c0fd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414477444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1414477444
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3799956548
Short name T169
Test name
Test status
Simulation time 1350934998 ps
CPU time 31.59 seconds
Started Mar 31 02:44:59 PM PDT 24
Finished Mar 31 02:45:31 PM PDT 24
Peak memory 232796 kb
Host smart-62908da5-6f99-4103-8cea-f56f1d55e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799956548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3799956548
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1891977424
Short name T336
Test name
Test status
Simulation time 6145861432 ps
CPU time 27.45 seconds
Started Mar 31 02:46:04 PM PDT 24
Finished Mar 31 02:46:32 PM PDT 24
Peak memory 236548 kb
Host smart-d310feac-c6b9-4b88-bff6-cca8fab1c053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891977424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1891977424
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.204703581
Short name T292
Test name
Test status
Simulation time 316288313 ps
CPU time 11.06 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:53 PM PDT 24
Peak memory 218472 kb
Host smart-756111fd-5b82-4794-bec8-6385ec59eabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204703581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.204703581
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1666551321
Short name T48
Test name
Test status
Simulation time 110286069 ps
CPU time 0.99 seconds
Started Mar 31 02:43:42 PM PDT 24
Finished Mar 31 02:43:43 PM PDT 24
Peak memory 234980 kb
Host smart-b0949031-1fa7-4c22-b76a-508d4e11b518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666551321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1666551321
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3342836801
Short name T7
Test name
Test status
Simulation time 4394281551 ps
CPU time 8.06 seconds
Started Mar 31 02:44:29 PM PDT 24
Finished Mar 31 02:44:37 PM PDT 24
Peak memory 223652 kb
Host smart-9f45fc9a-3936-4af9-b123-a48cee9b7f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342836801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3342836801
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4001348479
Short name T230
Test name
Test status
Simulation time 25072197506 ps
CPU time 15.84 seconds
Started Mar 31 02:44:54 PM PDT 24
Finished Mar 31 02:45:10 PM PDT 24
Peak memory 223128 kb
Host smart-53dc14bd-d01d-416a-8fcc-390df2128512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001348479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4001348479
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2347495155
Short name T361
Test name
Test status
Simulation time 1474094133 ps
CPU time 5.49 seconds
Started Mar 31 02:45:44 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 218552 kb
Host smart-e649b65a-613c-44c3-ab0a-76f534f0d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347495155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2347495155
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1072740587
Short name T229
Test name
Test status
Simulation time 216636536 ps
CPU time 3.93 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:10 PM PDT 24
Peak memory 223024 kb
Host smart-91124d8e-832c-49b7-91c7-9616804148e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072740587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1072740587
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_upload.2672995428
Short name T205
Test name
Test status
Simulation time 12068292373 ps
CPU time 14.97 seconds
Started Mar 31 02:45:38 PM PDT 24
Finished Mar 31 02:45:55 PM PDT 24
Peak memory 233852 kb
Host smart-19effb6f-dfa1-46d9-9717-c626ea7fd649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672995428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2672995428
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.1667456336
Short name T268
Test name
Test status
Simulation time 29713166441 ps
CPU time 24.11 seconds
Started Mar 31 02:46:17 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 234716 kb
Host smart-62b4660f-851d-4a62-aa81-f39a719ea29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667456336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1667456336
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.632071365
Short name T96
Test name
Test status
Simulation time 38656595255 ps
CPU time 140.03 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:49:54 PM PDT 24
Peak memory 223928 kb
Host smart-65f85f6f-08c0-46df-8a68-c44d335cb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632071365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.632071365
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_upload.3966100000
Short name T215
Test name
Test status
Simulation time 924417056 ps
CPU time 4.36 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:44:44 PM PDT 24
Peak memory 216448 kb
Host smart-c55876f3-037c-42be-9b26-75d2a9b1dfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966100000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3966100000
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.849146628
Short name T363
Test name
Test status
Simulation time 27413915440 ps
CPU time 14.63 seconds
Started Mar 31 02:45:24 PM PDT 24
Finished Mar 31 02:45:39 PM PDT 24
Peak memory 219596 kb
Host smart-bd494f22-d98a-4f78-a9f0-416b23c71d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849146628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.849146628
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.74017185
Short name T86
Test name
Test status
Simulation time 1668847111 ps
CPU time 8.27 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 219080 kb
Host smart-8ebd2e66-dec0-4782-930e-4956977e6602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74017185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.74017185
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_upload.717366087
Short name T337
Test name
Test status
Simulation time 363633285 ps
CPU time 5.1 seconds
Started Mar 31 02:47:10 PM PDT 24
Finished Mar 31 02:47:16 PM PDT 24
Peak memory 236636 kb
Host smart-b3213b1a-89c2-481f-9e51-64de51428350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717366087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.717366087
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1148757055
Short name T200
Test name
Test status
Simulation time 96465306665 ps
CPU time 29.61 seconds
Started Mar 31 02:47:33 PM PDT 24
Finished Mar 31 02:48:03 PM PDT 24
Peak memory 235208 kb
Host smart-e61c0751-0f07-44eb-b0af-5ec48cac3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148757055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1148757055
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3831780643
Short name T396
Test name
Test status
Simulation time 4152169839 ps
CPU time 34.61 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:46:16 PM PDT 24
Peak memory 216456 kb
Host smart-8ec76c1b-634b-4245-9718-8f196bc10b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831780643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3831780643
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4198807360
Short name T69
Test name
Test status
Simulation time 31121173165 ps
CPU time 37.8 seconds
Started Mar 31 02:46:16 PM PDT 24
Finished Mar 31 02:46:54 PM PDT 24
Peak memory 216408 kb
Host smart-469bc646-36c3-4278-bc2d-fa5059f27c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198807360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4198807360
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_intercept.492301951
Short name T191
Test name
Test status
Simulation time 9417806335 ps
CPU time 23.69 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:47:21 PM PDT 24
Peak memory 224300 kb
Host smart-454ed8a9-0944-4ca6-a349-a13b7f16fdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492301951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.492301951
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3115356266
Short name T112
Test name
Test status
Simulation time 626648992 ps
CPU time 10.56 seconds
Started Mar 31 02:45:49 PM PDT 24
Finished Mar 31 02:46:00 PM PDT 24
Peak memory 232552 kb
Host smart-04ed1a12-c7c2-4813-91b0-94f1d903ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115356266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3115356266
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1567649707
Short name T146
Test name
Test status
Simulation time 2742892790 ps
CPU time 12.52 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:40:01 PM PDT 24
Peak memory 216184 kb
Host smart-57e17933-73af-4d88-86f0-0409cb2f9aac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567649707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1567649707
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.165561372
Short name T232
Test name
Test status
Simulation time 7394314904 ps
CPU time 7.85 seconds
Started Mar 31 02:44:48 PM PDT 24
Finished Mar 31 02:44:56 PM PDT 24
Peak memory 222864 kb
Host smart-d77dc95a-b030-4b2a-9329-74296b487a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165561372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.165561372
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2383439055
Short name T111
Test name
Test status
Simulation time 3183399568 ps
CPU time 24.98 seconds
Started Mar 31 02:45:08 PM PDT 24
Finished Mar 31 02:45:33 PM PDT 24
Peak memory 218948 kb
Host smart-8cd9a757-be23-4c70-848b-ccd8409d4cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383439055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2383439055
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3952697647
Short name T100
Test name
Test status
Simulation time 1626716554 ps
CPU time 13.83 seconds
Started Mar 31 02:46:47 PM PDT 24
Finished Mar 31 02:47:01 PM PDT 24
Peak memory 224608 kb
Host smart-e4fdedf4-e307-4011-a791-a13bb204bd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952697647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3952697647
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2812037119
Short name T250
Test name
Test status
Simulation time 8173328249 ps
CPU time 13.35 seconds
Started Mar 31 02:46:53 PM PDT 24
Finished Mar 31 02:47:07 PM PDT 24
Peak memory 216924 kb
Host smart-e2f877b2-8426-4ca0-b619-6fea9811bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812037119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2812037119
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_upload.1537585143
Short name T237
Test name
Test status
Simulation time 825004595 ps
CPU time 6.36 seconds
Started Mar 31 02:46:52 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 222912 kb
Host smart-893e77ef-4301-4f11-9ee1-30c76c444a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537585143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1537585143
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3163330892
Short name T73
Test name
Test status
Simulation time 921933768 ps
CPU time 8.02 seconds
Started Mar 31 02:47:06 PM PDT 24
Finished Mar 31 02:47:15 PM PDT 24
Peak memory 233652 kb
Host smart-0d396cbf-a2dd-403d-8490-d11f3bf23c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163330892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3163330892
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1681956302
Short name T219
Test name
Test status
Simulation time 1063463047 ps
CPU time 5.44 seconds
Started Mar 31 02:47:19 PM PDT 24
Finished Mar 31 02:47:24 PM PDT 24
Peak memory 224464 kb
Host smart-f794952e-2ef8-4eed-bb27-0877933cbc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681956302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1681956302
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3028565892
Short name T254
Test name
Test status
Simulation time 356282727 ps
CPU time 5.63 seconds
Started Mar 31 02:47:40 PM PDT 24
Finished Mar 31 02:47:46 PM PDT 24
Peak memory 221444 kb
Host smart-06fc3d39-fcf4-4583-8e51-a38648344ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028565892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3028565892
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3235432434
Short name T261
Test name
Test status
Simulation time 1151563668 ps
CPU time 3.73 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:43:47 PM PDT 24
Peak memory 221300 kb
Host smart-c07cc4f3-8743-403d-9925-1eae939ffa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235432434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3235432434
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1762982417
Short name T259
Test name
Test status
Simulation time 635893483 ps
CPU time 4.62 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:18 PM PDT 24
Peak memory 224488 kb
Host smart-a36199dc-bb1a-42b2-a9ff-fe20d8ed0dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762982417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1762982417
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1530326721
Short name T94
Test name
Test status
Simulation time 12735816399 ps
CPU time 9.88 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:52 PM PDT 24
Peak memory 223384 kb
Host smart-f56031e9-78ca-4d87-b85d-1bd4e2562d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530326721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1530326721
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.647696945
Short name T83
Test name
Test status
Simulation time 2297281200 ps
CPU time 8.09 seconds
Started Mar 31 02:45:47 PM PDT 24
Finished Mar 31 02:45:55 PM PDT 24
Peak memory 218844 kb
Host smart-7b3e0f54-94c9-49c9-9e06-41d401833601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647696945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.647696945
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1364892491
Short name T87
Test name
Test status
Simulation time 47539234794 ps
CPU time 18.74 seconds
Started Mar 31 02:46:27 PM PDT 24
Finished Mar 31 02:46:46 PM PDT 24
Peak memory 234892 kb
Host smart-a473a141-70bb-4d85-b4a6-3df9ca8bebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364892491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1364892491
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1246518335
Short name T331
Test name
Test status
Simulation time 1061375707 ps
CPU time 3.86 seconds
Started Mar 31 02:46:52 PM PDT 24
Finished Mar 31 02:46:56 PM PDT 24
Peak memory 222636 kb
Host smart-38508d2f-1d9d-452e-8284-458a0139875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246518335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1246518335
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3268189006
Short name T193
Test name
Test status
Simulation time 1328015506 ps
CPU time 5.37 seconds
Started Mar 31 02:46:59 PM PDT 24
Finished Mar 31 02:47:04 PM PDT 24
Peak memory 219120 kb
Host smart-a744adfd-0042-47ea-b9d9-9aa92b573529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268189006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3268189006
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1220524635
Short name T377
Test name
Test status
Simulation time 747571741 ps
CPU time 4.74 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:40:00 PM PDT 24
Peak memory 215648 kb
Host smart-8063b607-9b52-4dfc-a267-fa9bf074bfff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220524635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1220524635
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2828500369
Short name T378
Test name
Test status
Simulation time 1222506196 ps
CPU time 19.62 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 215476 kb
Host smart-3f93f4a9-e7d4-41ea-9217-cb9a6b191366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828500369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2828500369
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_upload.3418138924
Short name T300
Test name
Test status
Simulation time 3561527940 ps
CPU time 13.51 seconds
Started Mar 31 02:43:45 PM PDT 24
Finished Mar 31 02:43:59 PM PDT 24
Peak memory 222724 kb
Host smart-a738d241-14e7-4431-bc0e-6250e754849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418138924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3418138924
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_intercept.991339694
Short name T101
Test name
Test status
Simulation time 5323698402 ps
CPU time 26.51 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 223420 kb
Host smart-dfc21146-2c10-4a90-b6c1-cdc9efaaf38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991339694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.991339694
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_upload.2469234951
Short name T78
Test name
Test status
Simulation time 235046707 ps
CPU time 4.92 seconds
Started Mar 31 02:44:48 PM PDT 24
Finished Mar 31 02:44:53 PM PDT 24
Peak memory 223944 kb
Host smart-6c017d3b-54a9-4dfd-a56a-d6a36825346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469234951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2469234951
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4060916250
Short name T351
Test name
Test status
Simulation time 3939512762 ps
CPU time 13.72 seconds
Started Mar 31 02:44:50 PM PDT 24
Finished Mar 31 02:45:04 PM PDT 24
Peak memory 220376 kb
Host smart-94673e43-d7db-4fc5-b747-d426afbe7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060916250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4060916250
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_upload.1653763232
Short name T42
Test name
Test status
Simulation time 994590353 ps
CPU time 7.28 seconds
Started Mar 31 02:44:52 PM PDT 24
Finished Mar 31 02:44:59 PM PDT 24
Peak memory 222884 kb
Host smart-e45a4415-124b-4c93-a2ae-95f7edcca86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653763232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1653763232
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.742660885
Short name T258
Test name
Test status
Simulation time 66276131126 ps
CPU time 33.24 seconds
Started Mar 31 02:45:01 PM PDT 24
Finished Mar 31 02:45:35 PM PDT 24
Peak memory 232764 kb
Host smart-13c9ffab-d5c9-489f-b4e3-fbc4fc891c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742660885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.742660885
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2301277673
Short name T51
Test name
Test status
Simulation time 5828647328 ps
CPU time 6.73 seconds
Started Mar 31 02:45:04 PM PDT 24
Finished Mar 31 02:45:11 PM PDT 24
Peak memory 224652 kb
Host smart-aa75199d-e100-474a-b1b7-a0016bce2768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301277673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2301277673
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1745773142
Short name T187
Test name
Test status
Simulation time 354240039 ps
CPU time 2.49 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:15 PM PDT 24
Peak memory 223068 kb
Host smart-51494d0d-ff90-41c1-b4ee-3ab30379edf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745773142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1745773142
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2607264429
Short name T221
Test name
Test status
Simulation time 6455833526 ps
CPU time 9.74 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:23 PM PDT 24
Peak memory 220820 kb
Host smart-3a27143d-19ba-4858-80b1-98f6065cae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607264429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2607264429
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_upload.1594323318
Short name T195
Test name
Test status
Simulation time 398079077 ps
CPU time 4.28 seconds
Started Mar 31 02:45:18 PM PDT 24
Finished Mar 31 02:45:23 PM PDT 24
Peak memory 220692 kb
Host smart-5befd3f0-cdd4-4156-b48c-db5eb6cc0239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594323318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1594323318
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2423891304
Short name T79
Test name
Test status
Simulation time 200132502 ps
CPU time 2.88 seconds
Started Mar 31 02:45:47 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 221132 kb
Host smart-2b240cee-cb4d-4df3-bee7-45c10a04430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423891304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2423891304
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2138751912
Short name T308
Test name
Test status
Simulation time 2710332024 ps
CPU time 9.27 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:09 PM PDT 24
Peak memory 232164 kb
Host smart-9b45e237-4a10-4576-af97-4380dd524b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138751912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2138751912
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.671538853
Short name T262
Test name
Test status
Simulation time 14013672747 ps
CPU time 48.92 seconds
Started Mar 31 02:46:15 PM PDT 24
Finished Mar 31 02:47:04 PM PDT 24
Peak memory 239376 kb
Host smart-335c65e8-5ab8-4bcf-8917-6ddca5247121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671538853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.671538853
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.643335818
Short name T71
Test name
Test status
Simulation time 1472719366 ps
CPU time 7.72 seconds
Started Mar 31 02:46:11 PM PDT 24
Finished Mar 31 02:46:19 PM PDT 24
Peak memory 224540 kb
Host smart-ba375ee4-d7c3-4c5f-a4be-8b6c09571383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643335818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.643335818
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.41274749
Short name T315
Test name
Test status
Simulation time 1687095066 ps
CPU time 17.95 seconds
Started Mar 31 02:46:22 PM PDT 24
Finished Mar 31 02:46:40 PM PDT 24
Peak memory 249204 kb
Host smart-ad884c47-35c3-4389-986a-707a19c7cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41274749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.41274749
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2006517852
Short name T349
Test name
Test status
Simulation time 1581277090 ps
CPU time 20.56 seconds
Started Mar 31 02:46:32 PM PDT 24
Finished Mar 31 02:46:53 PM PDT 24
Peak memory 234324 kb
Host smart-49382b1b-6daf-4fe0-a0c2-a2178e52be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006517852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2006517852
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3728525174
Short name T303
Test name
Test status
Simulation time 39448353227 ps
CPU time 29.09 seconds
Started Mar 31 02:46:24 PM PDT 24
Finished Mar 31 02:46:53 PM PDT 24
Peak memory 232860 kb
Host smart-a4ddf6db-0dd2-48cb-a3f7-818bfb298917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728525174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3728525174
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.647790097
Short name T239
Test name
Test status
Simulation time 3062976480 ps
CPU time 13.54 seconds
Started Mar 31 02:46:24 PM PDT 24
Finished Mar 31 02:46:37 PM PDT 24
Peak memory 223812 kb
Host smart-362f121c-3681-429d-a479-9bc7149e9738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647790097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.647790097
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_upload.2573109285
Short name T208
Test name
Test status
Simulation time 485456211 ps
CPU time 5.17 seconds
Started Mar 31 02:46:25 PM PDT 24
Finished Mar 31 02:46:30 PM PDT 24
Peak memory 224652 kb
Host smart-9fe5fb36-3719-4bf0-b0dd-5e050dc8e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573109285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2573109285
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.3374150195
Short name T347
Test name
Test status
Simulation time 28258226563 ps
CPU time 24.78 seconds
Started Mar 31 02:44:08 PM PDT 24
Finished Mar 31 02:44:33 PM PDT 24
Peak memory 224572 kb
Host smart-82ce95df-cf5f-4a62-9f2f-39917b90a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374150195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3374150195
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_upload.1577363113
Short name T75
Test name
Test status
Simulation time 439989769 ps
CPU time 5.93 seconds
Started Mar 31 02:47:23 PM PDT 24
Finished Mar 31 02:47:29 PM PDT 24
Peak memory 234876 kb
Host smart-aa177d76-d816-4716-ace9-7fb4d3990374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577363113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1577363113
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.352260157
Short name T31
Test name
Test status
Simulation time 221793297 ps
CPU time 1.06 seconds
Started Mar 31 02:46:53 PM PDT 24
Finished Mar 31 02:46:54 PM PDT 24
Peak memory 207084 kb
Host smart-c4997784-1d8a-4ff7-9699-b42135213c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352260157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.352260157
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.250653271
Short name T66
Test name
Test status
Simulation time 7608733215 ps
CPU time 32.78 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:45:14 PM PDT 24
Peak memory 216468 kb
Host smart-f0af4da1-41c9-4914-8e4a-11160c04de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250653271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.250653271
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_upload.3065629987
Short name T2
Test name
Test status
Simulation time 1538148529 ps
CPU time 7.68 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:25 PM PDT 24
Peak memory 218800 kb
Host smart-fb562bd1-b8f0-4181-a405-c40940db118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065629987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3065629987
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2937970897
Short name T384
Test name
Test status
Simulation time 909119559 ps
CPU time 21.75 seconds
Started Mar 31 12:39:46 PM PDT 24
Finished Mar 31 12:40:08 PM PDT 24
Peak memory 215528 kb
Host smart-aa030a95-7112-40e4-966e-8a950abe31c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937970897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2937970897
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2571335845
Short name T212
Test name
Test status
Simulation time 41123746400 ps
CPU time 28.66 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:45:02 PM PDT 24
Peak memory 224676 kb
Host smart-48bf2952-6bad-48e0-9c49-a4f5cbbecb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571335845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2571335845
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1881016721
Short name T214
Test name
Test status
Simulation time 1375445371 ps
CPU time 7.87 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:44:55 PM PDT 24
Peak memory 233064 kb
Host smart-986da377-7f17-4383-a423-31c7db358fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881016721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1881016721
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.1011694714
Short name T326
Test name
Test status
Simulation time 4789737867 ps
CPU time 15.06 seconds
Started Mar 31 02:44:46 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 218664 kb
Host smart-5af4b8e7-7fbc-4d47-bfa4-9cc770700f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011694714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1011694714
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3245703843
Short name T122
Test name
Test status
Simulation time 18759184196 ps
CPU time 76.13 seconds
Started Mar 31 02:44:54 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 224692 kb
Host smart-fe836cf4-35dc-46ea-a4b4-8987a9b194a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245703843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3245703843
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4141105049
Short name T241
Test name
Test status
Simulation time 1378298118 ps
CPU time 5.38 seconds
Started Mar 31 02:44:52 PM PDT 24
Finished Mar 31 02:44:58 PM PDT 24
Peak memory 218480 kb
Host smart-86282d28-1401-450b-8742-1ae5a7d99d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141105049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4141105049
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2503903772
Short name T344
Test name
Test status
Simulation time 959340728 ps
CPU time 8.42 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:45:15 PM PDT 24
Peak memory 223584 kb
Host smart-32ba3657-674c-4e6c-b3a2-6fd4c90d25f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503903772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2503903772
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2246805913
Short name T243
Test name
Test status
Simulation time 6562699018 ps
CPU time 8.34 seconds
Started Mar 31 02:45:01 PM PDT 24
Finished Mar 31 02:45:10 PM PDT 24
Peak memory 224956 kb
Host smart-241d588a-6349-4422-825a-1699caab836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246805913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2246805913
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3068751950
Short name T9
Test name
Test status
Simulation time 988910433 ps
CPU time 4.75 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:12 PM PDT 24
Peak memory 218600 kb
Host smart-c83a4217-07a3-4109-aef3-cb23eae521ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068751950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3068751950
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2757983628
Short name T194
Test name
Test status
Simulation time 7506828916 ps
CPU time 8.15 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:21 PM PDT 24
Peak memory 239640 kb
Host smart-cb8e7991-16e2-4e2b-9d55-cff0e1223ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757983628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2757983628
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_intercept.203994866
Short name T224
Test name
Test status
Simulation time 370825954 ps
CPU time 6.92 seconds
Started Mar 31 02:43:48 PM PDT 24
Finished Mar 31 02:43:55 PM PDT 24
Peak memory 224720 kb
Host smart-7afad575-583f-46da-ac9e-15f9ae348ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203994866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.203994866
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4171145747
Short name T84
Test name
Test status
Simulation time 3675268235 ps
CPU time 15.73 seconds
Started Mar 31 02:43:48 PM PDT 24
Finished Mar 31 02:44:04 PM PDT 24
Peak memory 233564 kb
Host smart-a2338942-2f2f-4555-81e9-d1b338408961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171145747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4171145747
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4081089886
Short name T129
Test name
Test status
Simulation time 1079685255 ps
CPU time 4.5 seconds
Started Mar 31 02:45:25 PM PDT 24
Finished Mar 31 02:45:29 PM PDT 24
Peak memory 216744 kb
Host smart-cf113a40-43be-49c6-be8c-bfc96542b613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081089886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4081089886
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2486348887
Short name T369
Test name
Test status
Simulation time 4387458716 ps
CPU time 30.83 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:46:03 PM PDT 24
Peak memory 234996 kb
Host smart-14e86106-e55e-4cac-b093-e5450e0733a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486348887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2486348887
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3471825689
Short name T197
Test name
Test status
Simulation time 2412341399 ps
CPU time 8.71 seconds
Started Mar 31 02:45:34 PM PDT 24
Finished Mar 31 02:45:43 PM PDT 24
Peak memory 236796 kb
Host smart-8db21fc7-510c-4824-81af-8d42d37b8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471825689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3471825689
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_upload.1137595434
Short name T355
Test name
Test status
Simulation time 1972247773 ps
CPU time 13.58 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 232896 kb
Host smart-69028181-f98c-4119-bfe4-fbe047d78281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137595434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1137595434
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3101130536
Short name T293
Test name
Test status
Simulation time 2126199823 ps
CPU time 7.07 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:49 PM PDT 24
Peak memory 222896 kb
Host smart-7518a547-cd8e-468d-987d-506bb759e612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101130536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3101130536
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1172355578
Short name T263
Test name
Test status
Simulation time 1009667626 ps
CPU time 5.97 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:47 PM PDT 24
Peak memory 218796 kb
Host smart-d33da82b-e99c-4482-8506-b3485f410ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172355578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1172355578
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.552602059
Short name T27
Test name
Test status
Simulation time 15897184972 ps
CPU time 10.4 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:52 PM PDT 24
Peak memory 223288 kb
Host smart-57cd8304-ca5a-45f3-b549-c4da98848f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552602059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.552602059
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4051587374
Short name T245
Test name
Test status
Simulation time 300168960 ps
CPU time 2.45 seconds
Started Mar 31 02:45:45 PM PDT 24
Finished Mar 31 02:45:48 PM PDT 24
Peak memory 222960 kb
Host smart-a91e4d64-0f6f-4e7f-b4b2-3c8372ffb05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051587374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4051587374
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1666194136
Short name T294
Test name
Test status
Simulation time 3680474072 ps
CPU time 8.24 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:46:01 PM PDT 24
Peak memory 222820 kb
Host smart-8d685c23-a819-455e-9944-365e235ca446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666194136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1666194136
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2256471894
Short name T299
Test name
Test status
Simulation time 343157710 ps
CPU time 5.39 seconds
Started Mar 31 02:45:57 PM PDT 24
Finished Mar 31 02:46:03 PM PDT 24
Peak memory 234820 kb
Host smart-7d3bab7d-9a3f-4ff8-b063-050bc87e9372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256471894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2256471894
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.579715136
Short name T284
Test name
Test status
Simulation time 3294114708 ps
CPU time 11.05 seconds
Started Mar 31 02:43:53 PM PDT 24
Finished Mar 31 02:44:05 PM PDT 24
Peak memory 216956 kb
Host smart-a935013c-67f7-4539-afdc-60c31fecf1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579715136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
579715136
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2149406464
Short name T24
Test name
Test status
Simulation time 822091498 ps
CPU time 3.44 seconds
Started Mar 31 02:46:32 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 222084 kb
Host smart-977546c0-156f-4f3a-9d50-ababf550f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149406464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2149406464
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_upload.3668549492
Short name T102
Test name
Test status
Simulation time 1927938284 ps
CPU time 3.83 seconds
Started Mar 31 02:46:32 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 219492 kb
Host smart-6559794f-295c-4d56-a857-f78ce8faed6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668549492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3668549492
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3485534448
Short name T282
Test name
Test status
Simulation time 76324990 ps
CPU time 2.44 seconds
Started Mar 31 02:46:42 PM PDT 24
Finished Mar 31 02:46:44 PM PDT 24
Peak memory 218656 kb
Host smart-788536ef-7bbd-453f-bfd4-8851b9e63663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485534448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3485534448
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2073493485
Short name T305
Test name
Test status
Simulation time 298029804 ps
CPU time 5.9 seconds
Started Mar 31 02:46:42 PM PDT 24
Finished Mar 31 02:46:48 PM PDT 24
Peak memory 238992 kb
Host smart-ab5b6a1a-0886-4907-afc1-4b6cdd8b1845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073493485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2073493485
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4011835823
Short name T362
Test name
Test status
Simulation time 14303806833 ps
CPU time 10.84 seconds
Started Mar 31 02:46:50 PM PDT 24
Finished Mar 31 02:47:01 PM PDT 24
Peak memory 216904 kb
Host smart-0e808d3c-d0c9-4df8-816e-3b472bce9e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011835823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4011835823
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2843146670
Short name T370
Test name
Test status
Simulation time 1617540613 ps
CPU time 13.18 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:19 PM PDT 24
Peak memory 235984 kb
Host smart-f9906bfa-538b-440b-8a42-ff4f0669393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843146670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2843146670
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2218286186
Short name T357
Test name
Test status
Simulation time 1576271342 ps
CPU time 9.29 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:10 PM PDT 24
Peak memory 234576 kb
Host smart-8f29f0e4-92ca-43ce-8d13-005f119e7db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218286186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2218286186
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.670985889
Short name T198
Test name
Test status
Simulation time 3775865131 ps
CPU time 7.6 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 230068 kb
Host smart-0afdd05a-9b75-4a3b-a1a0-e79e3ccbffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670985889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.670985889
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_upload.1855350011
Short name T231
Test name
Test status
Simulation time 1326668119 ps
CPU time 2.61 seconds
Started Mar 31 02:46:58 PM PDT 24
Finished Mar 31 02:47:01 PM PDT 24
Peak memory 218544 kb
Host smart-cc358083-c68f-4674-bc68-97c783ff099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855350011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1855350011
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3527814741
Short name T280
Test name
Test status
Simulation time 35026369331 ps
CPU time 59.2 seconds
Started Mar 31 02:47:04 PM PDT 24
Finished Mar 31 02:48:04 PM PDT 24
Peak memory 217200 kb
Host smart-407ea2ae-8a43-4b52-b9c7-6b4329bc5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527814741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3527814741
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.592202776
Short name T238
Test name
Test status
Simulation time 18541841361 ps
CPU time 24.45 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:47:38 PM PDT 24
Peak memory 235228 kb
Host smart-cd1f3c18-ace9-4ce5-bc4b-bf5ddbbb53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592202776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.592202776
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3371902155
Short name T358
Test name
Test status
Simulation time 5316729262 ps
CPU time 17.08 seconds
Started Mar 31 02:47:28 PM PDT 24
Finished Mar 31 02:47:45 PM PDT 24
Peak memory 224492 kb
Host smart-4be71d75-956a-4076-b996-265517227499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371902155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3371902155
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_upload.4242290177
Short name T97
Test name
Test status
Simulation time 13865178179 ps
CPU time 12.04 seconds
Started Mar 31 02:47:27 PM PDT 24
Finished Mar 31 02:47:39 PM PDT 24
Peak memory 221964 kb
Host smart-cd011925-56bf-4349-8dcf-57192a0e835a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242290177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4242290177
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3202860657
Short name T312
Test name
Test status
Simulation time 2968912029 ps
CPU time 19.18 seconds
Started Mar 31 02:47:38 PM PDT 24
Finished Mar 31 02:47:57 PM PDT 24
Peak memory 238000 kb
Host smart-874bd84c-7d5d-48af-9f1e-1d24b73196ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202860657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3202860657
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3220707677
Short name T226
Test name
Test status
Simulation time 4470110547 ps
CPU time 8.53 seconds
Started Mar 31 02:47:43 PM PDT 24
Finished Mar 31 02:47:51 PM PDT 24
Peak memory 235920 kb
Host smart-834a64d1-aac5-476b-a5ef-01a158a50d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220707677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3220707677
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_upload.1146595657
Short name T210
Test name
Test status
Simulation time 13872326758 ps
CPU time 12.6 seconds
Started Mar 31 02:47:39 PM PDT 24
Finished Mar 31 02:47:52 PM PDT 24
Peak memory 223152 kb
Host smart-588b8c44-8a68-4f42-a6f8-636157921b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146595657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1146595657
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.768486715
Short name T117
Test name
Test status
Simulation time 92779268 ps
CPU time 1.4 seconds
Started Mar 31 12:39:10 PM PDT 24
Finished Mar 31 12:39:11 PM PDT 24
Peak memory 216700 kb
Host smart-3fc4acba-b85a-484d-a2dc-79181e6a5637
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768486715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.768486715
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3380208271
Short name T133
Test name
Test status
Simulation time 66342558 ps
CPU time 2.11 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 215600 kb
Host smart-827526d6-9ef6-438f-bc89-eef28d63cf44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380208271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
380208271
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3510255740
Short name T160
Test name
Test status
Simulation time 920014475 ps
CPU time 23.37 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:46 PM PDT 24
Peak memory 207224 kb
Host smart-7ae879b5-aa85-4d6e-8715-2fcec65e8cf9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510255740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3510255740
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2584191899
Short name T780
Test name
Test status
Simulation time 364916448 ps
CPU time 12.11 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 207332 kb
Host smart-1b36bd1b-6b36-410a-ae1a-a43c92ff03c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584191899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2584191899
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2269453353
Short name T115
Test name
Test status
Simulation time 59194203 ps
CPU time 1.18 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 207140 kb
Host smart-92c8219c-862c-452f-8971-b3084ae557f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269453353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2269453353
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.623158239
Short name T781
Test name
Test status
Simulation time 51990057 ps
CPU time 1.77 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 215684 kb
Host smart-2f8c0319-c4bb-4859-b991-265e98fd39a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623158239 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.623158239
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3738103711
Short name T789
Test name
Test status
Simulation time 19475023 ps
CPU time 1.27 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 207220 kb
Host smart-77fe2c1b-8e5f-4d6f-95e4-e686b8bfd7a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738103711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
738103711
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3158139735
Short name T778
Test name
Test status
Simulation time 12955832 ps
CPU time 0.76 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 203568 kb
Host smart-1a6a2621-cfaf-46a1-a801-54ebf68adfd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158139735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
158139735
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.676681027
Short name T876
Test name
Test status
Simulation time 35295896 ps
CPU time 1.37 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 215560 kb
Host smart-4dcc1d9b-8d1e-442d-b05c-d71fb9a170ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676681027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.676681027
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.563057659
Short name T795
Test name
Test status
Simulation time 10696020 ps
CPU time 0.71 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:16 PM PDT 24
Peak memory 203700 kb
Host smart-a3c1e747-99cb-4be9-a811-11f48a382e6f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563057659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.563057659
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4074908905
Short name T806
Test name
Test status
Simulation time 227260738 ps
CPU time 1.82 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 207220 kb
Host smart-02adfd2c-c179-4bde-9f38-c5203f3f47d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074908905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4074908905
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4084656829
Short name T154
Test name
Test status
Simulation time 2448915073 ps
CPU time 24.47 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 207364 kb
Host smart-8e5a275a-ef19-49cd-9741-03dac79e87f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084656829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4084656829
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3650560767
Short name T805
Test name
Test status
Simulation time 5240892982 ps
CPU time 25.12 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 207300 kb
Host smart-d0e48985-6bdb-41a8-83e5-2c2ff6ff3302
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650560767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3650560767
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1092674800
Short name T825
Test name
Test status
Simulation time 24337031 ps
CPU time 1.53 seconds
Started Mar 31 12:39:15 PM PDT 24
Finished Mar 31 12:39:17 PM PDT 24
Peak memory 215728 kb
Host smart-c7f09b32-9aff-433a-a7c4-4a5c1d07d1c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092674800 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1092674800
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4062237065
Short name T782
Test name
Test status
Simulation time 268666986 ps
CPU time 2.17 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 207204 kb
Host smart-fe4c8f2b-a824-42b0-ba0b-ba495c1521b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062237065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
062237065
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1941918866
Short name T851
Test name
Test status
Simulation time 12311191 ps
CPU time 0.7 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 203820 kb
Host smart-1eb46b0c-b410-4b81-a2f7-419cbe5a404e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941918866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
941918866
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2633384149
Short name T161
Test name
Test status
Simulation time 99077743 ps
CPU time 2.44 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 215536 kb
Host smart-b7c411d1-fe0e-43ee-84c3-407fff551318
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633384149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2633384149
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2642593002
Short name T793
Test name
Test status
Simulation time 62132063 ps
CPU time 0.66 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 203580 kb
Host smart-68833d2c-64cf-4bb1-846d-9926be4aae38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642593002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2642593002
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2614817974
Short name T864
Test name
Test status
Simulation time 498164100 ps
CPU time 3.03 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 215692 kb
Host smart-938fe9b0-957c-4430-bc42-2f8ea4a9087b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614817974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2614817974
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2090106958
Short name T136
Test name
Test status
Simulation time 177806293 ps
CPU time 4.71 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 215556 kb
Host smart-822435fd-b889-48a9-aafa-711e794cf7c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090106958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
090106958
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3166944897
Short name T382
Test name
Test status
Simulation time 2414019235 ps
CPU time 12.5 seconds
Started Mar 31 12:39:16 PM PDT 24
Finished Mar 31 12:39:29 PM PDT 24
Peak memory 215636 kb
Host smart-70e8c73e-4ae1-4900-aa60-fed8da8a8994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166944897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3166944897
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2459300340
Short name T144
Test name
Test status
Simulation time 98485407 ps
CPU time 1.62 seconds
Started Mar 31 12:39:40 PM PDT 24
Finished Mar 31 12:39:41 PM PDT 24
Peak memory 215764 kb
Host smart-e549a8e3-cef3-4882-b7bb-fd60cf731620
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459300340 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2459300340
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.845644389
Short name T774
Test name
Test status
Simulation time 15865816 ps
CPU time 0.69 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 203516 kb
Host smart-c5a587d2-1ffa-47f0-9935-e0d40cc83a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845644389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.845644389
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3750357340
Short name T784
Test name
Test status
Simulation time 238579708 ps
CPU time 1.94 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:28 PM PDT 24
Peak memory 215572 kb
Host smart-8b971cf7-f67b-4295-be6c-e7fa6401a0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750357340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3750357340
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3396224610
Short name T867
Test name
Test status
Simulation time 160627319 ps
CPU time 4.26 seconds
Started Mar 31 12:39:41 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 215656 kb
Host smart-24b43e82-92c7-4dd2-b96c-1757ce57141a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396224610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3396224610
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2841573319
Short name T145
Test name
Test status
Simulation time 48626250 ps
CPU time 1.72 seconds
Started Mar 31 12:39:46 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 215768 kb
Host smart-43fe9c97-0e8b-4a1f-8396-6d28e04e03cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841573319 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2841573319
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.194845924
Short name T149
Test name
Test status
Simulation time 401373398 ps
CPU time 2.24 seconds
Started Mar 31 12:39:29 PM PDT 24
Finished Mar 31 12:39:32 PM PDT 24
Peak memory 215424 kb
Host smart-d9418245-502b-4344-96ac-155501789228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194845924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.194845924
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.671647514
Short name T808
Test name
Test status
Simulation time 55704588 ps
CPU time 0.69 seconds
Started Mar 31 12:39:39 PM PDT 24
Finished Mar 31 12:39:40 PM PDT 24
Peak memory 203632 kb
Host smart-e28909a5-7847-413d-91c2-dcedab6c59e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671647514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.671647514
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1277553848
Short name T163
Test name
Test status
Simulation time 590079548 ps
CPU time 3.91 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 215516 kb
Host smart-cfbda6b3-90e7-4ae5-a4e0-8d09c6e11324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277553848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1277553848
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2414729827
Short name T135
Test name
Test status
Simulation time 107185550 ps
CPU time 3.95 seconds
Started Mar 31 12:39:46 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 215632 kb
Host smart-3dbda82e-d685-4436-80fc-b596541dd404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414729827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2414729827
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3998432059
Short name T836
Test name
Test status
Simulation time 503160772 ps
CPU time 1.7 seconds
Started Mar 31 12:39:35 PM PDT 24
Finished Mar 31 12:39:37 PM PDT 24
Peak memory 215596 kb
Host smart-37104e61-0942-41e7-a5dd-be43ba6833af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998432059 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3998432059
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2792702383
Short name T802
Test name
Test status
Simulation time 94040744 ps
CPU time 2.72 seconds
Started Mar 31 12:39:36 PM PDT 24
Finished Mar 31 12:39:38 PM PDT 24
Peak memory 215592 kb
Host smart-15bf6773-9bd5-4c0e-abe2-665ec80bddee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792702383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2792702383
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4132964293
Short name T801
Test name
Test status
Simulation time 16563085 ps
CPU time 0.76 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:49 PM PDT 24
Peak memory 203836 kb
Host smart-4b821c97-8278-49fb-94a7-30882dca5367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132964293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4132964293
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.545297223
Short name T35
Test name
Test status
Simulation time 392951873 ps
CPU time 1.94 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 207424 kb
Host smart-cf8d169f-9041-432a-b101-28ab8bc3c676
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545297223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.545297223
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.249695555
Short name T846
Test name
Test status
Simulation time 126337820 ps
CPU time 2.16 seconds
Started Mar 31 12:39:40 PM PDT 24
Finished Mar 31 12:39:42 PM PDT 24
Peak memory 215768 kb
Host smart-bb462926-6eec-4f4f-84e4-449c340e8eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249695555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.249695555
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1753095112
Short name T829
Test name
Test status
Simulation time 443581472 ps
CPU time 6.92 seconds
Started Mar 31 12:39:38 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 215844 kb
Host smart-9a3600fc-7c48-4e82-96f5-0bfa7fef74bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753095112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1753095112
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.866824854
Short name T823
Test name
Test status
Simulation time 170071958 ps
CPU time 3.93 seconds
Started Mar 31 12:39:44 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 218308 kb
Host smart-77e43ffd-0b4c-45bd-be99-baefd75c24a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866824854 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.866824854
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1613215701
Short name T830
Test name
Test status
Simulation time 36916150 ps
CPU time 2.44 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:53 PM PDT 24
Peak memory 215596 kb
Host smart-e71d8fdb-dd0f-46f6-8036-5cbdfabcf7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613215701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1613215701
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1008067928
Short name T832
Test name
Test status
Simulation time 15470215 ps
CPU time 0.84 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:49 PM PDT 24
Peak memory 203628 kb
Host smart-f297065d-6450-4b4e-9f80-26be95188efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008067928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1008067928
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3263217308
Short name T164
Test name
Test status
Simulation time 113690155 ps
CPU time 2.73 seconds
Started Mar 31 12:39:41 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 215720 kb
Host smart-a974b229-a432-44ba-bae5-b101792abaca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263217308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3263217308
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3428962819
Short name T839
Test name
Test status
Simulation time 28719676 ps
CPU time 1.68 seconds
Started Mar 31 12:39:36 PM PDT 24
Finished Mar 31 12:39:38 PM PDT 24
Peak memory 215648 kb
Host smart-60124214-b976-46b0-ba4f-61e52c67eb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428962819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3428962819
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2083204257
Short name T174
Test name
Test status
Simulation time 2064420061 ps
CPU time 8.49 seconds
Started Mar 31 12:39:38 PM PDT 24
Finished Mar 31 12:39:47 PM PDT 24
Peak memory 215636 kb
Host smart-0c73c017-f1c2-41b9-be76-e167767845ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083204257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2083204257
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.719804205
Short name T868
Test name
Test status
Simulation time 103520735 ps
CPU time 2.93 seconds
Started Mar 31 12:39:41 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 216996 kb
Host smart-150d4d9a-44a1-46ae-9580-0460b892425f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719804205 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.719804205
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2047475349
Short name T819
Test name
Test status
Simulation time 527188462 ps
CPU time 2.49 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 207276 kb
Host smart-f4f26c4e-bf05-41df-b6e3-efa3137d25e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047475349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2047475349
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2868539911
Short name T791
Test name
Test status
Simulation time 16555517 ps
CPU time 0.73 seconds
Started Mar 31 12:39:34 PM PDT 24
Finished Mar 31 12:39:35 PM PDT 24
Peak memory 203904 kb
Host smart-e0a1ce8e-f7b0-42a6-b88e-a6d3736366ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868539911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2868539911
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.738930019
Short name T796
Test name
Test status
Simulation time 60557232 ps
CPU time 1.86 seconds
Started Mar 31 12:39:47 PM PDT 24
Finished Mar 31 12:39:49 PM PDT 24
Peak memory 207344 kb
Host smart-ae71041c-d4f9-4880-837a-92b98a2f7154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738930019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.738930019
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3803610830
Short name T125
Test name
Test status
Simulation time 78834581 ps
CPU time 1.56 seconds
Started Mar 31 12:39:45 PM PDT 24
Finished Mar 31 12:39:46 PM PDT 24
Peak memory 215620 kb
Host smart-fb317e76-55a1-4b54-86d5-dbe2acee1852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803610830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3803610830
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.614368424
Short name T381
Test name
Test status
Simulation time 832986303 ps
CPU time 21.97 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:53 PM PDT 24
Peak memory 223744 kb
Host smart-1a6df917-b6aa-4635-8c7f-9de1e607102a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614368424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.614368424
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1697336259
Short name T139
Test name
Test status
Simulation time 343414759 ps
CPU time 2.7 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:40:00 PM PDT 24
Peak memory 217860 kb
Host smart-2b1e936c-4cc4-4f29-aae7-a98157580197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697336259 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1697336259
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3327278789
Short name T156
Test name
Test status
Simulation time 147288067 ps
CPU time 2.73 seconds
Started Mar 31 12:39:45 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 215508 kb
Host smart-cbb09e71-2310-4536-a933-9a7301b45d06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327278789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3327278789
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.551944692
Short name T877
Test name
Test status
Simulation time 13399853 ps
CPU time 0.69 seconds
Started Mar 31 12:39:29 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 203580 kb
Host smart-9e689606-7b8e-48bc-a32f-37fede0e227b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551944692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.551944692
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.502056396
Short name T853
Test name
Test status
Simulation time 232089610 ps
CPU time 1.95 seconds
Started Mar 31 12:39:31 PM PDT 24
Finished Mar 31 12:39:33 PM PDT 24
Peak memory 215460 kb
Host smart-233b989f-38d1-4b32-a32f-9317535fb689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502056396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.502056396
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3123238582
Short name T141
Test name
Test status
Simulation time 134179487 ps
CPU time 2.54 seconds
Started Mar 31 12:39:44 PM PDT 24
Finished Mar 31 12:39:47 PM PDT 24
Peak memory 215716 kb
Host smart-4589cb03-4b86-4d8c-bff6-843aa4ae12be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123238582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3123238582
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1280770421
Short name T847
Test name
Test status
Simulation time 2906551233 ps
CPU time 16.73 seconds
Started Mar 31 12:39:42 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 216188 kb
Host smart-c10e4362-d052-419b-a940-48fcd04c7ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280770421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1280770421
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.384040949
Short name T376
Test name
Test status
Simulation time 210464993 ps
CPU time 1.9 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 215672 kb
Host smart-57fdfb6c-31a8-4338-8fec-e6fbd4498a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384040949 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.384040949
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.374285077
Short name T159
Test name
Test status
Simulation time 103104654 ps
CPU time 2.48 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 207316 kb
Host smart-f4f7371b-e2c7-4db6-b931-64378333be76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374285077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.374285077
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3010067104
Short name T835
Test name
Test status
Simulation time 42618520 ps
CPU time 0.72 seconds
Started Mar 31 12:39:43 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 203828 kb
Host smart-4886318d-79bd-4990-b7fe-5a46614221d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010067104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3010067104
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3828221049
Short name T815
Test name
Test status
Simulation time 347635145 ps
CPU time 3.93 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 215708 kb
Host smart-f1a43cec-289f-4503-8164-b0b1f1fbee74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828221049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3828221049
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1191125123
Short name T126
Test name
Test status
Simulation time 65913260 ps
CPU time 2.18 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:39:57 PM PDT 24
Peak memory 215768 kb
Host smart-6affa6cf-62b5-4686-aeee-2f79663a8bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191125123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1191125123
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2693571558
Short name T131
Test name
Test status
Simulation time 2172234262 ps
CPU time 23.67 seconds
Started Mar 31 12:39:46 PM PDT 24
Finished Mar 31 12:40:10 PM PDT 24
Peak memory 215696 kb
Host smart-40ec79b2-0a60-4758-ba2c-6e4adb619b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693571558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2693571558
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1226969479
Short name T814
Test name
Test status
Simulation time 464192659 ps
CPU time 1.7 seconds
Started Mar 31 12:39:46 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 215776 kb
Host smart-9821aacb-1ddc-4bbb-9f34-cc028f34dcac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226969479 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1226969479
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1325723614
Short name T878
Test name
Test status
Simulation time 143266425 ps
CPU time 1.27 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 207260 kb
Host smart-fc1097f7-aa0f-49fa-8fb1-c8c1217f2c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325723614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1325723614
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3940764649
Short name T788
Test name
Test status
Simulation time 24894881 ps
CPU time 0.69 seconds
Started Mar 31 12:39:42 PM PDT 24
Finished Mar 31 12:39:43 PM PDT 24
Peak memory 203784 kb
Host smart-796c9356-ac68-41ac-acbc-5fa77509c226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940764649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3940764649
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2089577102
Short name T817
Test name
Test status
Simulation time 205969861 ps
CPU time 2.85 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 215636 kb
Host smart-cfc21bf9-872a-4c9e-96b4-bf9c352f9158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089577102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2089577102
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4288563343
Short name T380
Test name
Test status
Simulation time 394371817 ps
CPU time 13.01 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:40:02 PM PDT 24
Peak memory 215732 kb
Host smart-1db4c9f6-c5e0-4877-882c-8d7211d7b427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288563343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4288563343
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.626004232
Short name T854
Test name
Test status
Simulation time 90601238 ps
CPU time 2.53 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 217132 kb
Host smart-99b013dc-6b91-4e4a-936d-b6b3da33aa3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626004232 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.626004232
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1995221968
Short name T794
Test name
Test status
Simulation time 102506585 ps
CPU time 1.94 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:52 PM PDT 24
Peak memory 215588 kb
Host smart-f918a65a-7a52-4c16-a317-1e8095693b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995221968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1995221968
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2094178792
Short name T872
Test name
Test status
Simulation time 12509300 ps
CPU time 0.78 seconds
Started Mar 31 12:39:44 PM PDT 24
Finished Mar 31 12:39:45 PM PDT 24
Peak memory 203864 kb
Host smart-cca5de57-0c22-4427-a1f6-094f59a2449c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094178792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2094178792
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2964196126
Short name T871
Test name
Test status
Simulation time 134546546 ps
CPU time 2.94 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 215408 kb
Host smart-416aa5c7-a4fb-4c13-9df0-41db009291e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964196126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2964196126
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.12474545
Short name T866
Test name
Test status
Simulation time 100937807 ps
CPU time 2 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 216644 kb
Host smart-39e5c39f-d329-42f0-95be-15b46b665baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.12474545
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3947294907
Short name T132
Test name
Test status
Simulation time 306169819 ps
CPU time 18.97 seconds
Started Mar 31 12:39:39 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 215548 kb
Host smart-629cb038-bdbf-46ed-9535-5c69c9b5c71c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947294907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3947294907
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2040194041
Short name T833
Test name
Test status
Simulation time 546828186 ps
CPU time 1.67 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 215616 kb
Host smart-e6800f94-8c7f-4eb1-bd5d-a0ffcaba294f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040194041 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2040194041
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.799420701
Short name T834
Test name
Test status
Simulation time 106399463 ps
CPU time 2.47 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:39:57 PM PDT 24
Peak memory 215596 kb
Host smart-12f641f1-f7c0-41ea-9dc0-69d29205c4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799420701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.799420701
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3600593669
Short name T178
Test name
Test status
Simulation time 30208584 ps
CPU time 0.76 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203888 kb
Host smart-aed38ab9-b1ea-41d7-a6d4-c7a892e51b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600593669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3600593669
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.493431510
Short name T175
Test name
Test status
Simulation time 561583779 ps
CPU time 3.17 seconds
Started Mar 31 12:39:52 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 215460 kb
Host smart-b74f9ad4-40bc-4f7a-913d-183406d92c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493431510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.493431510
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2757900052
Short name T379
Test name
Test status
Simulation time 417635485 ps
CPU time 12.67 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:40:09 PM PDT 24
Peak memory 215616 kb
Host smart-5cbebda3-6b2a-4643-ab6b-a212af8eee1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757900052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2757900052
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.336957601
Short name T840
Test name
Test status
Simulation time 324433891 ps
CPU time 20.94 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 215536 kb
Host smart-4b371015-7ee5-4cc9-8e9d-78854d1a0d5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336957601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.336957601
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2397126681
Short name T845
Test name
Test status
Simulation time 638754514 ps
CPU time 11.03 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:35 PM PDT 24
Peak memory 207272 kb
Host smart-41612185-0627-429e-9b1e-6650f765db54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397126681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2397126681
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.976612999
Short name T860
Test name
Test status
Simulation time 91787072 ps
CPU time 1.45 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 216584 kb
Host smart-7a0f51ca-b875-4bc0-9358-2d78a52552f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976612999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.976612999
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4148863174
Short name T828
Test name
Test status
Simulation time 55765142 ps
CPU time 1.87 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 215592 kb
Host smart-890d59db-f452-48d2-98ed-7e896878af13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148863174 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4148863174
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.949802794
Short name T859
Test name
Test status
Simulation time 37994553 ps
CPU time 2.43 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:33 PM PDT 24
Peak memory 215536 kb
Host smart-f8655c0a-192c-4d45-bdfb-fe324f271459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949802794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.949802794
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3517510301
Short name T857
Test name
Test status
Simulation time 27032035 ps
CPU time 0.76 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 203820 kb
Host smart-797b6ce3-9140-4b10-833d-0db5461c51f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517510301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
517510301
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1443865967
Short name T157
Test name
Test status
Simulation time 29036274 ps
CPU time 1.98 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 215520 kb
Host smart-5020e7f8-be36-4582-b1c7-15ea1cc4b52f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443865967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1443865967
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.595127977
Short name T882
Test name
Test status
Simulation time 13009343 ps
CPU time 0.7 seconds
Started Mar 31 12:39:45 PM PDT 24
Finished Mar 31 12:39:46 PM PDT 24
Peak memory 203620 kb
Host smart-86043a68-927e-4f9e-b7a1-108d3d762c34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595127977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.595127977
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3957427165
Short name T850
Test name
Test status
Simulation time 229535999 ps
CPU time 1.8 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 207492 kb
Host smart-384313df-7f89-4c3b-918c-0874441e2179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957427165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3957427165
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2000294280
Short name T137
Test name
Test status
Simulation time 109613791 ps
CPU time 2.3 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 215552 kb
Host smart-c0fd929c-52c0-45ab-bdc8-9020b7dc0005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000294280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
000294280
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3324392947
Short name T786
Test name
Test status
Simulation time 35582578 ps
CPU time 0.71 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:40:00 PM PDT 24
Peak memory 203644 kb
Host smart-2190f124-6946-4384-b963-96a21fc31932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324392947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3324392947
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2812038993
Short name T816
Test name
Test status
Simulation time 13575793 ps
CPU time 0.74 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203776 kb
Host smart-7a8c53c6-cfe8-4efe-9a3b-3df338455be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812038993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2812038993
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2692460154
Short name T777
Test name
Test status
Simulation time 41271227 ps
CPU time 0.72 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 203500 kb
Host smart-e967bcbf-247c-4d4c-9e62-f4200687182b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692460154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2692460154
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.883305246
Short name T842
Test name
Test status
Simulation time 40747003 ps
CPU time 0.75 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:39:56 PM PDT 24
Peak memory 203564 kb
Host smart-76ed417c-c7ef-4d66-8526-c8a1eb8f839e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883305246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.883305246
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1439316288
Short name T787
Test name
Test status
Simulation time 23027534 ps
CPU time 0.73 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 203848 kb
Host smart-d9f61b9b-3832-4f3f-a4ad-340a00ab1193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439316288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1439316288
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1828858377
Short name T804
Test name
Test status
Simulation time 20814236 ps
CPU time 0.72 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203776 kb
Host smart-63fa5480-bc16-4729-96c5-6990c85f596d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828858377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1828858377
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.161085586
Short name T810
Test name
Test status
Simulation time 16721550 ps
CPU time 0.73 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 203912 kb
Host smart-9a9453f3-6117-4a2a-99ec-8cd351c46374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161085586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.161085586
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.377865730
Short name T873
Test name
Test status
Simulation time 18365114 ps
CPU time 0.8 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203656 kb
Host smart-5733e129-ae20-4ca8-9d1f-371251cf34c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377865730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.377865730
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2822311560
Short name T855
Test name
Test status
Simulation time 33471822 ps
CPU time 0.7 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:39:54 PM PDT 24
Peak memory 203580 kb
Host smart-56fe0952-202e-4ae9-bb34-6c86f1a2d383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822311560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2822311560
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2367340446
Short name T881
Test name
Test status
Simulation time 52378592 ps
CPU time 0.79 seconds
Started Mar 31 12:39:51 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 203600 kb
Host smart-237574b6-25d7-452e-87a3-0cc4dc84c3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367340446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2367340446
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1077976924
Short name T162
Test name
Test status
Simulation time 787230298 ps
CPU time 13.76 seconds
Started Mar 31 12:39:20 PM PDT 24
Finished Mar 31 12:39:34 PM PDT 24
Peak memory 215504 kb
Host smart-7b22a94c-8f0b-429a-9791-7bbc61def90a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077976924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1077976924
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.601162924
Short name T155
Test name
Test status
Simulation time 1808933333 ps
CPU time 27.51 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:53 PM PDT 24
Peak memory 207108 kb
Host smart-9f073736-0932-47f4-901c-ce70028cd881
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601162924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.601162924
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1818438484
Short name T116
Test name
Test status
Simulation time 77322697 ps
CPU time 1.43 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 216496 kb
Host smart-28f9a917-3bc7-4b8a-9ab5-d6af21a957c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818438484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1818438484
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.298723066
Short name T799
Test name
Test status
Simulation time 157277998 ps
CPU time 1.69 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 215616 kb
Host smart-267c9484-68dd-45d3-b889-9ca76f4865b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298723066 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.298723066
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2201108854
Short name T848
Test name
Test status
Simulation time 67437042 ps
CPU time 1.33 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 207384 kb
Host smart-d81dc6e9-d61d-4e81-ad7c-928767c7bf0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201108854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
201108854
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1062438559
Short name T775
Test name
Test status
Simulation time 15263368 ps
CPU time 0.73 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:31 PM PDT 24
Peak memory 203568 kb
Host smart-e3c2a94d-5336-4bb5-9491-f2bf7d876a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062438559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
062438559
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3542913554
Short name T152
Test name
Test status
Simulation time 242072266 ps
CPU time 2.05 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:33 PM PDT 24
Peak memory 215652 kb
Host smart-3dd1a0e0-ff34-49c3-8315-a724cb0a1277
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542913554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3542913554
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2547674518
Short name T863
Test name
Test status
Simulation time 52603208 ps
CPU time 0.67 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 203556 kb
Host smart-6cd69f3a-a50e-4119-85f2-04bf1718a260
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547674518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2547674518
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.771085566
Short name T843
Test name
Test status
Simulation time 916788928 ps
CPU time 1.81 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 215500 kb
Host smart-d13b84df-3ac5-4b6c-b9ff-82bffe4b3c31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771085566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.771085566
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3357111625
Short name T849
Test name
Test status
Simulation time 519112380 ps
CPU time 3.12 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:34 PM PDT 24
Peak memory 215652 kb
Host smart-cdcd7f84-feb0-44a8-813a-01b68e067176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357111625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
357111625
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3420202939
Short name T869
Test name
Test status
Simulation time 3077538897 ps
CPU time 15.52 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:38 PM PDT 24
Peak memory 215724 kb
Host smart-57f490b2-2121-4882-abaf-a834d3d254f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420202939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3420202939
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1903327773
Short name T800
Test name
Test status
Simulation time 40761333 ps
CPU time 0.76 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203568 kb
Host smart-fd426cee-b64f-4d43-99ad-5a6b6204a359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903327773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1903327773
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1015673823
Short name T831
Test name
Test status
Simulation time 39540250 ps
CPU time 0.71 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 203560 kb
Host smart-a6622e61-5cf3-4bc3-a2f1-a1051c4edb19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015673823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1015673823
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1332702428
Short name T865
Test name
Test status
Simulation time 30265467 ps
CPU time 0.74 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:01 PM PDT 24
Peak memory 203556 kb
Host smart-27595227-ce0f-41dc-bc0f-0ac0cd51c569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332702428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1332702428
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1482421667
Short name T813
Test name
Test status
Simulation time 13228680 ps
CPU time 0.75 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 203500 kb
Host smart-57dc3fe4-1d3e-49fe-aab3-c71ae98c6423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482421667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1482421667
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.130553088
Short name T798
Test name
Test status
Simulation time 15988318 ps
CPU time 0.74 seconds
Started Mar 31 12:39:47 PM PDT 24
Finished Mar 31 12:39:48 PM PDT 24
Peak memory 203824 kb
Host smart-64d20ccc-7e86-4cad-9236-16dc7df395ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130553088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.130553088
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2671910060
Short name T856
Test name
Test status
Simulation time 18155566 ps
CPU time 0.75 seconds
Started Mar 31 12:39:51 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 203832 kb
Host smart-c4811e55-8cb4-4760-8a86-cc2ba433a7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671910060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2671910060
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.93617590
Short name T861
Test name
Test status
Simulation time 162583184 ps
CPU time 0.71 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:39:58 PM PDT 24
Peak memory 203572 kb
Host smart-09335f14-3ae0-4d63-b066-174ad0252371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93617590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.93617590
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4291894331
Short name T809
Test name
Test status
Simulation time 156263663 ps
CPU time 0.76 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203548 kb
Host smart-92621e84-ee6a-410b-bd3d-f078b3823eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291894331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4291894331
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4001489399
Short name T792
Test name
Test status
Simulation time 41952095 ps
CPU time 0.75 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 12:39:57 PM PDT 24
Peak memory 203888 kb
Host smart-f72b8b66-1e35-463f-bd30-6e2b5b1bd81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001489399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4001489399
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.102385345
Short name T803
Test name
Test status
Simulation time 38334603 ps
CPU time 0.72 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 203504 kb
Host smart-c7b243e5-54fc-4218-9fef-adf74df1397a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102385345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.102385345
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4021700874
Short name T171
Test name
Test status
Simulation time 1389969175 ps
CPU time 7.36 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:38 PM PDT 24
Peak memory 207288 kb
Host smart-63123f6e-e9a9-4377-b99c-a75de31cabe0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021700874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4021700874
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2441182270
Short name T811
Test name
Test status
Simulation time 1243856263 ps
CPU time 23.73 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:41 PM PDT 24
Peak memory 207120 kb
Host smart-2a1ade24-34c0-43fe-8001-0135eec8cbb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441182270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2441182270
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.185852259
Short name T118
Test name
Test status
Simulation time 77826096 ps
CPU time 1.41 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:19 PM PDT 24
Peak memory 207360 kb
Host smart-9755316b-3133-43c9-b4e7-77211923a766
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185852259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.185852259
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2524442709
Short name T874
Test name
Test status
Simulation time 25547574 ps
CPU time 1.54 seconds
Started Mar 31 12:39:34 PM PDT 24
Finished Mar 31 12:39:36 PM PDT 24
Peak memory 215692 kb
Host smart-1b5c1f54-a49e-423e-928e-378f16a82de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524442709 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2524442709
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2073597605
Short name T158
Test name
Test status
Simulation time 92810993 ps
CPU time 1.4 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:32 PM PDT 24
Peak memory 215536 kb
Host smart-0ffb57d6-9607-4dff-8bcf-33e98a082659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073597605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
073597605
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1469472470
Short name T821
Test name
Test status
Simulation time 36287702 ps
CPU time 0.74 seconds
Started Mar 31 12:39:17 PM PDT 24
Finished Mar 31 12:39:18 PM PDT 24
Peak memory 203592 kb
Host smart-52b8d9b3-cc7e-4689-987a-d607d2ad6feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469472470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
469472470
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1784100107
Short name T151
Test name
Test status
Simulation time 279823797 ps
CPU time 2.28 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 215676 kb
Host smart-1e4c7c7e-85ec-4b80-b08b-3f2e9d5a6bac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784100107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1784100107
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2055339772
Short name T776
Test name
Test status
Simulation time 25888504 ps
CPU time 0.71 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 203916 kb
Host smart-7335d50b-b9f9-4683-8f1e-eed29d7a1583
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055339772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2055339772
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3648744535
Short name T827
Test name
Test status
Simulation time 194312415 ps
CPU time 3.81 seconds
Started Mar 31 12:39:40 PM PDT 24
Finished Mar 31 12:39:44 PM PDT 24
Peak memory 215548 kb
Host smart-c98e44b4-8764-4799-bd74-25ee65b6523d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648744535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3648744535
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.990337663
Short name T143
Test name
Test status
Simulation time 209823770 ps
CPU time 1.68 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 215616 kb
Host smart-7a232d3c-496d-405c-ab1f-5b001d3b4994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990337663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.990337663
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1939882775
Short name T386
Test name
Test status
Simulation time 1145531588 ps
CPU time 16.36 seconds
Started Mar 31 12:39:30 PM PDT 24
Finished Mar 31 12:39:47 PM PDT 24
Peak memory 216028 kb
Host smart-b80cb06e-87d9-4b35-9151-ddd17c99ded9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939882775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1939882775
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2694544457
Short name T179
Test name
Test status
Simulation time 26379550 ps
CPU time 0.72 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 12:39:57 PM PDT 24
Peak memory 203560 kb
Host smart-07412e5d-1fa4-4188-99c9-ee8a8a8e0101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694544457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2694544457
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.788840572
Short name T837
Test name
Test status
Simulation time 36361587 ps
CPU time 0.69 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:39:59 PM PDT 24
Peak memory 203580 kb
Host smart-7d61647c-8fb4-4ba0-8e05-fe83b284875f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788840572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.788840572
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1766008859
Short name T180
Test name
Test status
Simulation time 126652471 ps
CPU time 0.79 seconds
Started Mar 31 12:39:51 PM PDT 24
Finished Mar 31 12:39:52 PM PDT 24
Peak memory 203628 kb
Host smart-a329fed3-2e72-4655-8f95-d8927d511f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766008859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1766008859
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.638638242
Short name T818
Test name
Test status
Simulation time 13272272 ps
CPU time 0.76 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:40:08 PM PDT 24
Peak memory 203880 kb
Host smart-53064801-bc2d-4215-8b99-0fbf40c63fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638638242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.638638242
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3757668517
Short name T844
Test name
Test status
Simulation time 12701520 ps
CPU time 0.76 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:01 PM PDT 24
Peak memory 203656 kb
Host smart-cbc7e69d-1685-4a88-b89a-7d61f3646634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757668517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3757668517
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1486345827
Short name T841
Test name
Test status
Simulation time 21483754 ps
CPU time 0.76 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 203424 kb
Host smart-ae2796ae-c009-40fe-8500-3649a738aee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486345827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1486345827
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1830120605
Short name T797
Test name
Test status
Simulation time 22369366 ps
CPU time 0.73 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:03 PM PDT 24
Peak memory 203592 kb
Host smart-226a0c8c-ff4c-4cfc-8b8c-8c6d8972f0d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830120605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1830120605
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3972472610
Short name T826
Test name
Test status
Simulation time 30229830 ps
CPU time 0.77 seconds
Started Mar 31 12:39:48 PM PDT 24
Finished Mar 31 12:39:49 PM PDT 24
Peak memory 203424 kb
Host smart-486ee0db-bd30-4198-8485-9c8995fe9efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972472610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3972472610
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4138634288
Short name T773
Test name
Test status
Simulation time 56749667 ps
CPU time 0.78 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:39:54 PM PDT 24
Peak memory 203652 kb
Host smart-7cbc5559-64e7-4159-bde1-4ab9cd174ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138634288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4138634288
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2322792837
Short name T824
Test name
Test status
Simulation time 44937951 ps
CPU time 0.72 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:50 PM PDT 24
Peak memory 203488 kb
Host smart-beaa039a-4e8c-4694-b9a6-4c20bb9985fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322792837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2322792837
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2658824859
Short name T147
Test name
Test status
Simulation time 101062488 ps
CPU time 1.74 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:39:51 PM PDT 24
Peak memory 215676 kb
Host smart-6d48f7a1-5353-4d05-a3a3-61337b35546a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658824859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2658824859
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.836243438
Short name T807
Test name
Test status
Simulation time 69766893 ps
CPU time 1.34 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:22 PM PDT 24
Peak memory 215088 kb
Host smart-aae8a433-0d99-4dc7-950e-7637237e4d5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836243438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.836243438
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1363138412
Short name T870
Test name
Test status
Simulation time 53960838 ps
CPU time 0.73 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 203616 kb
Host smart-3834d901-c968-4c1b-b03c-7a6e206c379f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363138412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
363138412
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3984631555
Short name T37
Test name
Test status
Simulation time 50427220 ps
CPU time 1.69 seconds
Started Mar 31 12:39:18 PM PDT 24
Finished Mar 31 12:39:20 PM PDT 24
Peak memory 215364 kb
Host smart-4d20b2f5-ee3a-431b-9117-cd7abb0d8dd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984631555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3984631555
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4289293610
Short name T138
Test name
Test status
Simulation time 129896951 ps
CPU time 3.44 seconds
Started Mar 31 12:39:34 PM PDT 24
Finished Mar 31 12:39:37 PM PDT 24
Peak memory 215696 kb
Host smart-4168aea4-91f1-4a8a-a21d-061107785728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289293610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
289293610
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.327585813
Short name T820
Test name
Test status
Simulation time 2358798696 ps
CPU time 7.78 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:33 PM PDT 24
Peak memory 215692 kb
Host smart-df60afc0-ec35-41a6-9a0d-af59424112f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327585813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.327585813
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.144095885
Short name T879
Test name
Test status
Simulation time 135548136 ps
CPU time 3.89 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 216768 kb
Host smart-0a759068-92aa-4ffa-acfa-0c32e820d7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144095885 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.144095885
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1237081157
Short name T838
Test name
Test status
Simulation time 74353216 ps
CPU time 2.52 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:23 PM PDT 24
Peak memory 214920 kb
Host smart-3e52bf66-7283-469e-9e9a-3703008381b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237081157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
237081157
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3092113271
Short name T790
Test name
Test status
Simulation time 19484508 ps
CPU time 0.69 seconds
Started Mar 31 12:39:21 PM PDT 24
Finished Mar 31 12:39:21 PM PDT 24
Peak memory 204084 kb
Host smart-168b1701-fa36-4994-8ae8-2081662d5194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092113271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
092113271
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1710540690
Short name T165
Test name
Test status
Simulation time 823780491 ps
CPU time 2.69 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:26 PM PDT 24
Peak memory 215556 kb
Host smart-a654fb14-75de-4612-9265-e900d3d6c7c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710540690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1710540690
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1622361456
Short name T862
Test name
Test status
Simulation time 98736235 ps
CPU time 2.89 seconds
Started Mar 31 12:39:19 PM PDT 24
Finished Mar 31 12:39:22 PM PDT 24
Peak memory 215600 kb
Host smart-ce5dbb22-0fb7-485d-8112-c58563695329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622361456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
622361456
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3967617924
Short name T822
Test name
Test status
Simulation time 188051847 ps
CPU time 6.38 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 217356 kb
Host smart-f11d3796-d572-45b2-bdeb-4e694a23119d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967617924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3967617924
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3508806050
Short name T176
Test name
Test status
Simulation time 182152990 ps
CPU time 2.36 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:28 PM PDT 24
Peak memory 216736 kb
Host smart-97bf67c5-d71f-451f-a557-45e85d31999b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508806050 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3508806050
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3043987016
Short name T852
Test name
Test status
Simulation time 326495106 ps
CPU time 2.52 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 215580 kb
Host smart-7c3fc0b5-f025-4994-ba88-1c4d3d8a577c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043987016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
043987016
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1928616776
Short name T812
Test name
Test status
Simulation time 35393024 ps
CPU time 0.67 seconds
Started Mar 31 12:39:26 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 203588 kb
Host smart-d8d9adad-b708-45ae-b897-d558a7f81ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928616776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
928616776
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1667528069
Short name T783
Test name
Test status
Simulation time 59904120 ps
CPU time 3.47 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 215508 kb
Host smart-e2ebec5e-aefa-4ac2-9240-c9dad2429397
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667528069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1667528069
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1056079524
Short name T779
Test name
Test status
Simulation time 50000978 ps
CPU time 1.5 seconds
Started Mar 31 12:39:28 PM PDT 24
Finished Mar 31 12:39:29 PM PDT 24
Peak memory 215540 kb
Host smart-f89e5e2a-e09e-4c45-9946-612a934a43b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056079524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
056079524
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.729085008
Short name T383
Test name
Test status
Simulation time 1145242465 ps
CPU time 6.62 seconds
Started Mar 31 12:39:22 PM PDT 24
Finished Mar 31 12:39:29 PM PDT 24
Peak memory 215448 kb
Host smart-2adb34d5-cc41-4a53-8391-4447de0c1022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729085008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.729085008
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1889443397
Short name T172
Test name
Test status
Simulation time 102127200 ps
CPU time 2.78 seconds
Started Mar 31 12:39:39 PM PDT 24
Finished Mar 31 12:39:42 PM PDT 24
Peak memory 216712 kb
Host smart-a3ecca1b-4761-487d-bfc9-375dc771515b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889443397 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1889443397
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2290520051
Short name T140
Test name
Test status
Simulation time 114185602 ps
CPU time 1.91 seconds
Started Mar 31 12:39:34 PM PDT 24
Finished Mar 31 12:39:36 PM PDT 24
Peak memory 207216 kb
Host smart-74401e66-202b-44b9-bf85-9b649600f40d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290520051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
290520051
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3070165040
Short name T880
Test name
Test status
Simulation time 34042310 ps
CPU time 0.68 seconds
Started Mar 31 12:39:23 PM PDT 24
Finished Mar 31 12:39:24 PM PDT 24
Peak memory 203808 kb
Host smart-5ce1c4a9-d77d-4df9-b7eb-e571bf70e0dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070165040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
070165040
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2585261595
Short name T166
Test name
Test status
Simulation time 64416867 ps
CPU time 3.85 seconds
Started Mar 31 12:39:45 PM PDT 24
Finished Mar 31 12:39:49 PM PDT 24
Peak memory 215492 kb
Host smart-2f830988-d839-4a5c-9b72-367d4b96fdd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585261595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2585261595
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4223908438
Short name T142
Test name
Test status
Simulation time 566396665 ps
CPU time 3.78 seconds
Started Mar 31 12:39:26 PM PDT 24
Finished Mar 31 12:39:30 PM PDT 24
Peak memory 215636 kb
Host smart-070248f1-3120-4254-be3a-5234f316837e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223908438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
223908438
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.214980448
Short name T385
Test name
Test status
Simulation time 1594333956 ps
CPU time 21.57 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:47 PM PDT 24
Peak memory 216488 kb
Host smart-80ac7d20-25a8-4496-9c13-6989d3db4ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214980448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.214980448
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.227177712
Short name T173
Test name
Test status
Simulation time 225931819 ps
CPU time 1.85 seconds
Started Mar 31 12:39:32 PM PDT 24
Finished Mar 31 12:39:34 PM PDT 24
Peak memory 215824 kb
Host smart-2f145028-bb7c-416b-8f0d-6130b409a255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227177712 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.227177712
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2657936519
Short name T153
Test name
Test status
Simulation time 325820741 ps
CPU time 2.34 seconds
Started Mar 31 12:39:25 PM PDT 24
Finished Mar 31 12:39:27 PM PDT 24
Peak memory 207380 kb
Host smart-2d81ea96-5429-4c19-bfbf-2eaf6e2fb264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657936519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
657936519
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2906107374
Short name T858
Test name
Test status
Simulation time 21510774 ps
CPU time 0.74 seconds
Started Mar 31 12:39:24 PM PDT 24
Finished Mar 31 12:39:25 PM PDT 24
Peak memory 203604 kb
Host smart-7165dec5-c9ee-4e1e-bf6c-1e12dd1db549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906107374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
906107374
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2974903278
Short name T785
Test name
Test status
Simulation time 692487760 ps
CPU time 4.13 seconds
Started Mar 31 12:39:28 PM PDT 24
Finished Mar 31 12:39:32 PM PDT 24
Peak memory 215544 kb
Host smart-903ade17-2b1d-47f0-bf12-241e42823795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974903278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2974903278
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.252755623
Short name T127
Test name
Test status
Simulation time 92520626 ps
CPU time 1.64 seconds
Started Mar 31 12:39:31 PM PDT 24
Finished Mar 31 12:39:32 PM PDT 24
Peak memory 215668 kb
Host smart-0d12bf40-aa94-49e6-aede-792dbcf46465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252755623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.252755623
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2784174658
Short name T875
Test name
Test status
Simulation time 554203784 ps
CPU time 7.33 seconds
Started Mar 31 12:39:39 PM PDT 24
Finished Mar 31 12:39:46 PM PDT 24
Peak memory 215592 kb
Host smart-5f649e54-1f28-408b-92e9-0e4b42241fac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784174658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2784174658
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1141444989
Short name T487
Test name
Test status
Simulation time 46068782 ps
CPU time 0.72 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:43:44 PM PDT 24
Peak memory 205692 kb
Host smart-fbde2676-55e7-4c25-bed9-e3779a9b61be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141444989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
141444989
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3519263385
Short name T106
Test name
Test status
Simulation time 734929979 ps
CPU time 2.26 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:43:45 PM PDT 24
Peak memory 218772 kb
Host smart-5cedc52e-d6a4-449d-a7cc-8b6f11f49c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519263385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3519263385
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.714295359
Short name T585
Test name
Test status
Simulation time 21112582 ps
CPU time 0.81 seconds
Started Mar 31 02:43:39 PM PDT 24
Finished Mar 31 02:43:40 PM PDT 24
Peak memory 206800 kb
Host smart-cbcfe963-3e6f-4094-b2cb-5bb596d936b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714295359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.714295359
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2351115368
Short name T631
Test name
Test status
Simulation time 123958864 ps
CPU time 3.52 seconds
Started Mar 31 02:43:39 PM PDT 24
Finished Mar 31 02:43:42 PM PDT 24
Peak memory 224092 kb
Host smart-732f7f29-d79e-4017-adbb-e577cb1e48d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351115368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2351115368
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2812771708
Short name T110
Test name
Test status
Simulation time 19633376660 ps
CPU time 28.62 seconds
Started Mar 31 02:43:39 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 218968 kb
Host smart-aeec2b29-59d7-4b6d-bc4e-db3070a83cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812771708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2812771708
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.108250803
Short name T627
Test name
Test status
Simulation time 92369277 ps
CPU time 1.07 seconds
Started Mar 31 02:43:39 PM PDT 24
Finished Mar 31 02:43:41 PM PDT 24
Peak memory 217900 kb
Host smart-63615949-437d-4748-be3e-184265cc7187
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108250803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.108250803
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1640926649
Short name T217
Test name
Test status
Simulation time 134095975 ps
CPU time 2.53 seconds
Started Mar 31 02:43:38 PM PDT 24
Finished Mar 31 02:43:41 PM PDT 24
Peak memory 222444 kb
Host smart-036d5e8a-28a8-43e0-b171-7f76c3a79e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640926649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1640926649
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2682020506
Short name T526
Test name
Test status
Simulation time 3067545458 ps
CPU time 10.54 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:43:54 PM PDT 24
Peak memory 222644 kb
Host smart-b85c9a45-228b-4356-9a29-15fa07ca6d47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2682020506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2682020506
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1601599216
Short name T613
Test name
Test status
Simulation time 5728108816 ps
CPU time 8.52 seconds
Started Mar 31 02:43:38 PM PDT 24
Finished Mar 31 02:43:47 PM PDT 24
Peak memory 216320 kb
Host smart-12d57d23-ea46-4c90-92a5-085ff589d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601599216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1601599216
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4039874416
Short name T614
Test name
Test status
Simulation time 1340497244 ps
CPU time 8.48 seconds
Started Mar 31 02:43:38 PM PDT 24
Finished Mar 31 02:43:47 PM PDT 24
Peak memory 216296 kb
Host smart-cb941152-9c38-46f2-a613-0db5a9e0a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039874416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4039874416
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3189843754
Short name T760
Test name
Test status
Simulation time 150363435 ps
CPU time 2.44 seconds
Started Mar 31 02:43:40 PM PDT 24
Finished Mar 31 02:43:43 PM PDT 24
Peak memory 216408 kb
Host smart-8a4f25c8-91bb-4f59-b650-2de2ab739913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189843754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3189843754
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3813379384
Short name T557
Test name
Test status
Simulation time 326101000 ps
CPU time 0.84 seconds
Started Mar 31 02:43:39 PM PDT 24
Finished Mar 31 02:43:40 PM PDT 24
Peak memory 205716 kb
Host smart-ce0350ea-4bb9-467c-94f3-f442ea278afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813379384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3813379384
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2425723869
Short name T345
Test name
Test status
Simulation time 41901346455 ps
CPU time 51.21 seconds
Started Mar 31 02:43:40 PM PDT 24
Finished Mar 31 02:44:32 PM PDT 24
Peak memory 238320 kb
Host smart-571bc822-eaaf-47d3-91cd-e2ac0b505e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425723869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2425723869
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2861050436
Short name T57
Test name
Test status
Simulation time 13424078 ps
CPU time 0.78 seconds
Started Mar 31 02:43:52 PM PDT 24
Finished Mar 31 02:43:53 PM PDT 24
Peak memory 205364 kb
Host smart-b008e3d3-3c67-45ce-ae80-8d06abbe4994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861050436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
861050436
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.198150789
Short name T539
Test name
Test status
Simulation time 16339568 ps
CPU time 0.76 seconds
Started Mar 31 02:43:45 PM PDT 24
Finished Mar 31 02:43:46 PM PDT 24
Peak memory 205732 kb
Host smart-66e08bc7-9019-46ce-ba49-6cd906940cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198150789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.198150789
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1693565172
Short name T374
Test name
Test status
Simulation time 729871765 ps
CPU time 19.03 seconds
Started Mar 31 02:43:44 PM PDT 24
Finished Mar 31 02:44:03 PM PDT 24
Peak memory 236604 kb
Host smart-90337e57-2c1f-40a5-b4d9-23ae659ca362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693565172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1693565172
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1210398111
Short name T192
Test name
Test status
Simulation time 7791672504 ps
CPU time 18.22 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:44:01 PM PDT 24
Peak memory 222616 kb
Host smart-5affac40-4b40-4393-867c-722f0db693be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210398111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1210398111
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2487409744
Short name T209
Test name
Test status
Simulation time 402453543 ps
CPU time 5.06 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:43:49 PM PDT 24
Peak memory 222576 kb
Host smart-b16b7990-3b99-442a-a3a7-2cc5fd3141d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487409744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2487409744
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.813711312
Short name T550
Test name
Test status
Simulation time 15536803 ps
CPU time 0.71 seconds
Started Mar 31 02:43:41 PM PDT 24
Finished Mar 31 02:43:42 PM PDT 24
Peak memory 216240 kb
Host smart-f19b5be5-fca1-412f-ad0f-fbe07caecbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813711312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.813711312
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2716995553
Short name T497
Test name
Test status
Simulation time 264054602 ps
CPU time 6.58 seconds
Started Mar 31 02:43:41 PM PDT 24
Finished Mar 31 02:43:47 PM PDT 24
Peak memory 222404 kb
Host smart-c789dce1-eb37-4338-ae0a-5eca7a946fba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2716995553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2716995553
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4070512202
Short name T49
Test name
Test status
Simulation time 134322300 ps
CPU time 1.19 seconds
Started Mar 31 02:43:51 PM PDT 24
Finished Mar 31 02:43:52 PM PDT 24
Peak memory 236020 kb
Host smart-631f0f88-8256-47fa-9b0d-db09f86d150d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070512202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4070512202
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2223595088
Short name T702
Test name
Test status
Simulation time 14146553290 ps
CPU time 22.72 seconds
Started Mar 31 02:43:43 PM PDT 24
Finished Mar 31 02:44:06 PM PDT 24
Peak memory 217296 kb
Host smart-51b6a7c5-e9e4-4def-b128-5c4aeda3039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223595088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2223595088
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3452441906
Short name T533
Test name
Test status
Simulation time 87630599 ps
CPU time 1.29 seconds
Started Mar 31 02:43:42 PM PDT 24
Finished Mar 31 02:43:44 PM PDT 24
Peak memory 216376 kb
Host smart-f7195dfe-0c8d-4b6d-b4e3-5ecaae8a4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452441906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3452441906
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4139289146
Short name T594
Test name
Test status
Simulation time 34064012 ps
CPU time 0.8 seconds
Started Mar 31 02:43:42 PM PDT 24
Finished Mar 31 02:43:43 PM PDT 24
Peak memory 205700 kb
Host smart-83973783-562f-4e1d-b784-52683a5faa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139289146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4139289146
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.65692349
Short name T600
Test name
Test status
Simulation time 58957661 ps
CPU time 0.71 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:44:35 PM PDT 24
Peak memory 204712 kb
Host smart-a64da585-df04-4ff3-925a-e9dc633f8bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65692349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.65692349
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.143528535
Short name T251
Test name
Test status
Simulation time 1612191913 ps
CPU time 10.48 seconds
Started Mar 31 02:44:33 PM PDT 24
Finished Mar 31 02:44:44 PM PDT 24
Peak memory 224596 kb
Host smart-b6e2a235-f99c-4b6a-9514-1743a3b2e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143528535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.143528535
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.824443408
Short name T425
Test name
Test status
Simulation time 25246745 ps
CPU time 0.73 seconds
Started Mar 31 02:44:31 PM PDT 24
Finished Mar 31 02:44:32 PM PDT 24
Peak memory 205408 kb
Host smart-89b3773c-6f5d-41b5-80ce-01c0cd1dca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824443408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.824443408
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1897681891
Short name T323
Test name
Test status
Simulation time 8674386476 ps
CPU time 40.08 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 240252 kb
Host smart-e2aed00c-21e1-4b80-a22b-b575c032b9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897681891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1897681891
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1616255930
Short name T353
Test name
Test status
Simulation time 17558779223 ps
CPU time 40.56 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:45:14 PM PDT 24
Peak memory 234512 kb
Host smart-c1f74a8d-28e9-426a-8548-6b567047d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616255930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1616255930
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1906631433
Short name T537
Test name
Test status
Simulation time 26928984 ps
CPU time 1.08 seconds
Started Mar 31 02:44:27 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 216772 kb
Host smart-cd72c809-7b8d-475d-9161-ea93ecd40731
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906631433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1906631433
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2729894254
Short name T338
Test name
Test status
Simulation time 6327636190 ps
CPU time 7.31 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:44:42 PM PDT 24
Peak memory 218744 kb
Host smart-80f5af9d-4327-41c5-b5dc-af721049a4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729894254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2729894254
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3265913369
Short name T673
Test name
Test status
Simulation time 42920777 ps
CPU time 0.73 seconds
Started Mar 31 02:44:39 PM PDT 24
Finished Mar 31 02:44:40 PM PDT 24
Peak memory 216256 kb
Host smart-9dbb058a-d89f-4534-a7d8-e978e35f93b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265913369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3265913369
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.979830330
Short name T742
Test name
Test status
Simulation time 69435122 ps
CPU time 3.56 seconds
Started Mar 31 02:44:37 PM PDT 24
Finished Mar 31 02:44:41 PM PDT 24
Peak memory 222444 kb
Host smart-9d9c1c40-8811-45c7-bf4a-a28a49493381
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=979830330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.979830330
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2453963530
Short name T686
Test name
Test status
Simulation time 124992569 ps
CPU time 1.2 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:44:36 PM PDT 24
Peak memory 207128 kb
Host smart-839ca193-d64f-423a-bcef-c6bcfda5e6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453963530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2453963530
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2150462630
Short name T571
Test name
Test status
Simulation time 20686382396 ps
CPU time 30.62 seconds
Started Mar 31 02:44:33 PM PDT 24
Finished Mar 31 02:45:04 PM PDT 24
Peak memory 216424 kb
Host smart-9201cef0-23bd-4d44-b867-b098e003eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150462630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2150462630
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.517667975
Short name T502
Test name
Test status
Simulation time 909274689 ps
CPU time 3.25 seconds
Started Mar 31 02:44:36 PM PDT 24
Finished Mar 31 02:44:39 PM PDT 24
Peak memory 216576 kb
Host smart-77de3514-7a9b-4e49-bbf9-026a8e85e991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517667975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.517667975
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1449350610
Short name T402
Test name
Test status
Simulation time 352856654 ps
CPU time 5.18 seconds
Started Mar 31 02:44:36 PM PDT 24
Finished Mar 31 02:44:41 PM PDT 24
Peak memory 216412 kb
Host smart-40002dd1-7f0a-47ce-b0fb-9b7e395eebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449350610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1449350610
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3252350311
Short name T690
Test name
Test status
Simulation time 137229589 ps
CPU time 1.16 seconds
Started Mar 31 02:44:35 PM PDT 24
Finished Mar 31 02:44:36 PM PDT 24
Peak memory 206732 kb
Host smart-a0a15a97-5465-420a-a0b3-cb21612884cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252350311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3252350311
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.311829519
Short name T447
Test name
Test status
Simulation time 120695710 ps
CPU time 0.74 seconds
Started Mar 31 02:44:42 PM PDT 24
Finished Mar 31 02:44:43 PM PDT 24
Peak memory 205676 kb
Host smart-2f8a7cfb-2bb8-4ae6-81c0-f308cc92dbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311829519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.311829519
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1399494590
Short name T548
Test name
Test status
Simulation time 14258358 ps
CPU time 0.78 seconds
Started Mar 31 02:44:39 PM PDT 24
Finished Mar 31 02:44:40 PM PDT 24
Peak memory 206804 kb
Host smart-e2eb1296-73d1-4139-a4c1-e54ff8dec96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399494590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1399494590
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2962799732
Short name T324
Test name
Test status
Simulation time 8256912768 ps
CPU time 58.12 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:45:38 PM PDT 24
Peak memory 238624 kb
Host smart-f1cb9206-75e1-4bbb-8a53-394d4e2193a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962799732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2962799732
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2598204534
Short name T189
Test name
Test status
Simulation time 1675615033 ps
CPU time 20.43 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 217372 kb
Host smart-4b22ef8d-7cf4-4736-9a83-05a714c7e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598204534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2598204534
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.820709381
Short name T297
Test name
Test status
Simulation time 53836450241 ps
CPU time 91.97 seconds
Started Mar 31 02:44:43 PM PDT 24
Finished Mar 31 02:46:15 PM PDT 24
Peak memory 239532 kb
Host smart-77d98b5e-f4fc-4847-9131-ed1967e2c9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820709381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.820709381
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3437118740
Short name T64
Test name
Test status
Simulation time 45242076 ps
CPU time 1.1 seconds
Started Mar 31 02:44:34 PM PDT 24
Finished Mar 31 02:44:35 PM PDT 24
Peak memory 216740 kb
Host smart-66c1b75e-83bd-4477-883d-c6e0458dcd7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437118740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3437118740
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2575376438
Short name T500
Test name
Test status
Simulation time 196034318 ps
CPU time 2.01 seconds
Started Mar 31 02:44:44 PM PDT 24
Finished Mar 31 02:44:46 PM PDT 24
Peak memory 220152 kb
Host smart-42601ed8-8adf-49f6-9a8f-2e56da7ed9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575376438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2575376438
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.2618035763
Short name T765
Test name
Test status
Simulation time 41658462 ps
CPU time 0.71 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:44:41 PM PDT 24
Peak memory 216300 kb
Host smart-f8d8f2bf-c587-4402-bed8-1d8818c1a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618035763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.2618035763
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3934180654
Short name T722
Test name
Test status
Simulation time 894500962 ps
CPU time 10.05 seconds
Started Mar 31 02:44:42 PM PDT 24
Finished Mar 31 02:44:52 PM PDT 24
Peak memory 222348 kb
Host smart-e8aa39b8-29c2-4a03-ac83-0325a8debf18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3934180654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3934180654
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.869071083
Short name T119
Test name
Test status
Simulation time 11610821009 ps
CPU time 17.41 seconds
Started Mar 31 02:44:42 PM PDT 24
Finished Mar 31 02:44:59 PM PDT 24
Peak memory 216416 kb
Host smart-5d879448-9629-46ac-9d97-d8fd1f09b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869071083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.869071083
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3725586392
Short name T602
Test name
Test status
Simulation time 2651689290 ps
CPU time 6.09 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:44:47 PM PDT 24
Peak memory 216336 kb
Host smart-e8b96943-52d4-43b9-9f91-28116640436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725586392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3725586392
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4252788092
Short name T680
Test name
Test status
Simulation time 175016662 ps
CPU time 1.27 seconds
Started Mar 31 02:44:43 PM PDT 24
Finished Mar 31 02:44:45 PM PDT 24
Peak memory 216236 kb
Host smart-1ca31078-b044-4ed2-97c5-5a50090d92ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252788092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4252788092
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1116185000
Short name T580
Test name
Test status
Simulation time 131222940 ps
CPU time 0.88 seconds
Started Mar 31 02:44:42 PM PDT 24
Finished Mar 31 02:44:43 PM PDT 24
Peak memory 205736 kb
Host smart-9125bf96-434d-4dfa-8328-ae2ad1c4bcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116185000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1116185000
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2065387306
Short name T651
Test name
Test status
Simulation time 12687100 ps
CPU time 0.77 seconds
Started Mar 31 02:44:51 PM PDT 24
Finished Mar 31 02:44:52 PM PDT 24
Peak memory 204680 kb
Host smart-1cb05431-6ed1-4a72-ba47-dc5cc9998729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065387306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2065387306
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.367593792
Short name T23
Test name
Test status
Simulation time 6977955310 ps
CPU time 20.53 seconds
Started Mar 31 02:44:49 PM PDT 24
Finished Mar 31 02:45:09 PM PDT 24
Peak memory 224344 kb
Host smart-2ae1c893-fcb0-42b6-9c29-3d72e067cc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367593792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.367593792
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2613759705
Short name T711
Test name
Test status
Simulation time 22165028 ps
CPU time 0.81 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:44:41 PM PDT 24
Peak memory 206512 kb
Host smart-45ed8b76-4ae0-448f-8d8f-6457f4d26580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613759705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2613759705
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2925423056
Short name T10
Test name
Test status
Simulation time 1588162730 ps
CPU time 31.02 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:45:18 PM PDT 24
Peak memory 240784 kb
Host smart-9f1ac62a-9589-41cd-8168-5b2da1f7f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925423056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2925423056
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1324750168
Short name T662
Test name
Test status
Simulation time 15904349104 ps
CPU time 12.79 seconds
Started Mar 31 02:44:51 PM PDT 24
Finished Mar 31 02:45:04 PM PDT 24
Peak memory 218024 kb
Host smart-198c79ca-6675-4fc4-b279-1cc9488e12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324750168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1324750168
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1218886491
Short name T555
Test name
Test status
Simulation time 99148588584 ps
CPU time 183.51 seconds
Started Mar 31 02:44:52 PM PDT 24
Finished Mar 31 02:47:55 PM PDT 24
Peak memory 230348 kb
Host smart-a00bb549-423a-428b-bd6a-ab961d8e3b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218886491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1218886491
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2540237028
Short name T622
Test name
Test status
Simulation time 32368558 ps
CPU time 1.11 seconds
Started Mar 31 02:44:40 PM PDT 24
Finished Mar 31 02:44:41 PM PDT 24
Peak memory 216800 kb
Host smart-74ab1e31-ecde-404c-baaf-28669bb64bb4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540237028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2540237028
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2615693860
Short name T341
Test name
Test status
Simulation time 564298776 ps
CPU time 2.17 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:44:50 PM PDT 24
Peak memory 218524 kb
Host smart-ffc80cea-835d-4f2f-9f5a-4b30b4253713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615693860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2615693860
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2504173977
Short name T637
Test name
Test status
Simulation time 35229320 ps
CPU time 0.72 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:44:42 PM PDT 24
Peak memory 216220 kb
Host smart-e24e6fe6-b5a0-4c23-a681-47420b76464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504173977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2504173977
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3565624487
Short name T683
Test name
Test status
Simulation time 100417855 ps
CPU time 3.99 seconds
Started Mar 31 02:44:51 PM PDT 24
Finished Mar 31 02:44:55 PM PDT 24
Peak memory 222800 kb
Host smart-c17881a1-6bbe-4dff-9119-400c259268fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3565624487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3565624487
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2166951645
Short name T494
Test name
Test status
Simulation time 1289124854 ps
CPU time 4.95 seconds
Started Mar 31 02:44:41 PM PDT 24
Finished Mar 31 02:44:46 PM PDT 24
Peak memory 216328 kb
Host smart-7bf660ce-1ec3-4fb2-8546-0a444fecc815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166951645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2166951645
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4018417842
Short name T535
Test name
Test status
Simulation time 53699541 ps
CPU time 2.3 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:44:49 PM PDT 24
Peak memory 216412 kb
Host smart-dd2c050c-5c09-42d5-81ef-5ec80bdf06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018417842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4018417842
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1081525820
Short name T56
Test name
Test status
Simulation time 51113481 ps
CPU time 0.78 seconds
Started Mar 31 02:44:42 PM PDT 24
Finished Mar 31 02:44:42 PM PDT 24
Peak memory 205736 kb
Host smart-4eb249d9-55eb-41c5-9d0b-d6d238cd49f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081525820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1081525820
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4059255077
Short name T616
Test name
Test status
Simulation time 81878224 ps
CPU time 0.78 seconds
Started Mar 31 02:44:56 PM PDT 24
Finished Mar 31 02:44:57 PM PDT 24
Peak memory 204784 kb
Host smart-7bab9011-0fa4-4acf-bc62-3248dbafa9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059255077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4059255077
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.148282491
Short name T551
Test name
Test status
Simulation time 61910852 ps
CPU time 0.75 seconds
Started Mar 31 02:44:52 PM PDT 24
Finished Mar 31 02:44:53 PM PDT 24
Peak memory 205504 kb
Host smart-93d47e5d-4310-4074-85c2-dfa2d736e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148282491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.148282491
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3822459941
Short name T754
Test name
Test status
Simulation time 5623632144 ps
CPU time 84.92 seconds
Started Mar 31 02:44:49 PM PDT 24
Finished Mar 31 02:46:14 PM PDT 24
Peak memory 249156 kb
Host smart-ce202359-fd5f-4f80-8a6b-f0e5837561e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822459941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3822459941
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1883714018
Short name T114
Test name
Test status
Simulation time 1430560666 ps
CPU time 5.66 seconds
Started Mar 31 02:44:51 PM PDT 24
Finished Mar 31 02:44:57 PM PDT 24
Peak memory 219176 kb
Host smart-12cec4fe-addf-4049-baf8-a6c94b59ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883714018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1883714018
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3135622310
Short name T416
Test name
Test status
Simulation time 59055674 ps
CPU time 0.99 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:44:48 PM PDT 24
Peak memory 218000 kb
Host smart-b73949d4-cbc5-4f3a-8dba-eecd8a90a687
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135622310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3135622310
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2598292209
Short name T343
Test name
Test status
Simulation time 366294053 ps
CPU time 5.82 seconds
Started Mar 31 02:44:48 PM PDT 24
Finished Mar 31 02:44:53 PM PDT 24
Peak memory 222412 kb
Host smart-753f4ade-d0ff-42f6-b675-ba82408efe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598292209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2598292209
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1376523059
Short name T40
Test name
Test status
Simulation time 17281281 ps
CPU time 0.75 seconds
Started Mar 31 02:44:48 PM PDT 24
Finished Mar 31 02:44:48 PM PDT 24
Peak memory 216288 kb
Host smart-aa2db063-a825-41fe-9c5a-716b4ac58305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376523059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1376523059
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2334868250
Short name T188
Test name
Test status
Simulation time 1638621984 ps
CPU time 9.03 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:44:56 PM PDT 24
Peak memory 222276 kb
Host smart-17465bc1-7506-4668-bbd5-650a3f1e7b99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2334868250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2334868250
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.488693540
Short name T520
Test name
Test status
Simulation time 5719773948 ps
CPU time 39.08 seconds
Started Mar 31 02:44:45 PM PDT 24
Finished Mar 31 02:45:24 PM PDT 24
Peak memory 216448 kb
Host smart-2a39788f-42b4-4f6e-bbc1-d7a6c96e6503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488693540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.488693540
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2064309070
Short name T466
Test name
Test status
Simulation time 22482424051 ps
CPU time 15.31 seconds
Started Mar 31 02:44:47 PM PDT 24
Finished Mar 31 02:45:02 PM PDT 24
Peak memory 216392 kb
Host smart-dfdd3086-02fb-40d0-8547-cecfc95527c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064309070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2064309070
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2555570624
Short name T407
Test name
Test status
Simulation time 307418505 ps
CPU time 2.7 seconds
Started Mar 31 02:44:49 PM PDT 24
Finished Mar 31 02:44:52 PM PDT 24
Peak memory 208732 kb
Host smart-af92b217-e82a-489e-850d-792b10abddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555570624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2555570624
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4256554787
Short name T609
Test name
Test status
Simulation time 283465026 ps
CPU time 0.88 seconds
Started Mar 31 02:44:48 PM PDT 24
Finished Mar 31 02:44:49 PM PDT 24
Peak memory 205728 kb
Host smart-233fa487-92b2-4285-9b40-9951d465fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256554787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4256554787
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3436035841
Short name T88
Test name
Test status
Simulation time 2759640371 ps
CPU time 6.15 seconds
Started Mar 31 02:44:52 PM PDT 24
Finished Mar 31 02:44:58 PM PDT 24
Peak memory 223092 kb
Host smart-209645f9-d55e-4af5-a221-6b9a26f13799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436035841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3436035841
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2696364646
Short name T450
Test name
Test status
Simulation time 202376127 ps
CPU time 0.75 seconds
Started Mar 31 02:44:53 PM PDT 24
Finished Mar 31 02:44:54 PM PDT 24
Peak memory 205424 kb
Host smart-a96b0d40-501f-411c-9f07-66a6926eaff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696364646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2696364646
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1713222824
Short name T366
Test name
Test status
Simulation time 6046464828 ps
CPU time 40.92 seconds
Started Mar 31 02:44:53 PM PDT 24
Finished Mar 31 02:45:34 PM PDT 24
Peak memory 236640 kb
Host smart-ae4e8239-df2e-425f-bfe2-db0d1fc8c0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713222824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1713222824
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1294538346
Short name T33
Test name
Test status
Simulation time 92120066 ps
CPU time 1.11 seconds
Started Mar 31 02:44:56 PM PDT 24
Finished Mar 31 02:44:57 PM PDT 24
Peak memory 216816 kb
Host smart-d32dd581-cd17-4a6f-a60b-2915c5194ef4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294538346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1294538346
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3732975894
Short name T182
Test name
Test status
Simulation time 212752659 ps
CPU time 2.71 seconds
Started Mar 31 02:44:56 PM PDT 24
Finished Mar 31 02:45:00 PM PDT 24
Peak memory 221444 kb
Host smart-862b9e8b-ca92-40f5-83ab-23424d86cfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732975894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3732975894
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.4156023961
Short name T750
Test name
Test status
Simulation time 44367476 ps
CPU time 0.77 seconds
Started Mar 31 02:44:57 PM PDT 24
Finished Mar 31 02:44:58 PM PDT 24
Peak memory 216256 kb
Host smart-5dc992eb-cee6-427b-8255-b40f12bfbee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156023961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.4156023961
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2352826441
Short name T430
Test name
Test status
Simulation time 143379696 ps
CPU time 4.45 seconds
Started Mar 31 02:44:56 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 222792 kb
Host smart-0fed5fba-30ce-45e8-a6ac-dcb2f96b043a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352826441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2352826441
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.209814871
Short name T766
Test name
Test status
Simulation time 452928815 ps
CPU time 7.42 seconds
Started Mar 31 02:44:56 PM PDT 24
Finished Mar 31 02:45:03 PM PDT 24
Peak memory 216664 kb
Host smart-7a54a8b6-6038-4edb-81a6-d537661de2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209814871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.209814871
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2275602807
Short name T408
Test name
Test status
Simulation time 104338467 ps
CPU time 1.09 seconds
Started Mar 31 02:44:54 PM PDT 24
Finished Mar 31 02:44:56 PM PDT 24
Peak memory 207072 kb
Host smart-34fef4a8-2626-4a76-b58d-d8cc3bfb02f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275602807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2275602807
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.413083928
Short name T586
Test name
Test status
Simulation time 135268986 ps
CPU time 0.8 seconds
Started Mar 31 02:44:53 PM PDT 24
Finished Mar 31 02:44:54 PM PDT 24
Peak memory 205720 kb
Host smart-8ca490d7-54f6-44ee-87bf-abb826bab769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413083928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.413083928
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2118309211
Short name T413
Test name
Test status
Simulation time 47886450 ps
CPU time 0.73 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 205348 kb
Host smart-474ee5ab-e13a-4622-a0ff-ced5a0b5ba44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118309211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2118309211
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.584186675
Short name T703
Test name
Test status
Simulation time 69658393 ps
CPU time 0.81 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:09 PM PDT 24
Peak memory 206444 kb
Host smart-67796382-324c-4882-aeaa-fa0be2f2efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584186675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.584186675
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_intercept.819822420
Short name T348
Test name
Test status
Simulation time 1604040972 ps
CPU time 3.42 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:03 PM PDT 24
Peak memory 217912 kb
Host smart-33ca341c-8006-4819-b995-d310d2664e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819822420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.819822420
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3350558973
Short name T493
Test name
Test status
Simulation time 3355013801 ps
CPU time 37.4 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:45:36 PM PDT 24
Peak memory 231340 kb
Host smart-464ca3d1-c438-42f6-bfd6-c290526204bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350558973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3350558973
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3614382120
Short name T422
Test name
Test status
Simulation time 15776565 ps
CPU time 1 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:44:59 PM PDT 24
Peak memory 218048 kb
Host smart-4537872a-5570-412f-b942-aef8696a2466
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614382120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3614382120
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2501240301
Short name T727
Test name
Test status
Simulation time 16924148 ps
CPU time 0.75 seconds
Started Mar 31 02:44:59 PM PDT 24
Finished Mar 31 02:45:00 PM PDT 24
Peak memory 216276 kb
Host smart-420cba39-8ce3-40a5-b9b9-71a445aaf0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501240301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2501240301
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2012323846
Short name T148
Test name
Test status
Simulation time 2414583772 ps
CPU time 5.92 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:45:12 PM PDT 24
Peak memory 223040 kb
Host smart-09de2a09-8c68-4f25-9399-6e4617905c76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2012323846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2012323846
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2279097008
Short name T394
Test name
Test status
Simulation time 9182474671 ps
CPU time 26.12 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:34 PM PDT 24
Peak memory 216400 kb
Host smart-e2ea2438-7721-4d30-ad2d-80dc884a344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279097008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2279097008
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.671869587
Short name T669
Test name
Test status
Simulation time 30950424882 ps
CPU time 26.17 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:45:25 PM PDT 24
Peak memory 216380 kb
Host smart-c07d8c53-49b3-4a44-8b12-ce1e43dac91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671869587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.671869587
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1444680914
Short name T640
Test name
Test status
Simulation time 55683190 ps
CPU time 0.95 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 206868 kb
Host smart-148e7015-7539-4b16-a251-84906d738287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444680914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1444680914
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1601870883
Short name T437
Test name
Test status
Simulation time 60385840 ps
CPU time 0.85 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:44:59 PM PDT 24
Peak memory 205744 kb
Host smart-5e297b74-e73b-4ab5-a71b-0eadc789ca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601870883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1601870883
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4110610314
Short name T274
Test name
Test status
Simulation time 710541487 ps
CPU time 10.28 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:10 PM PDT 24
Peak memory 224376 kb
Host smart-d3a532c2-6831-4b76-8f56-4c601f47aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110610314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4110610314
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1229673019
Short name T468
Test name
Test status
Simulation time 70033308 ps
CPU time 0.72 seconds
Started Mar 31 02:45:08 PM PDT 24
Finished Mar 31 02:45:09 PM PDT 24
Peak memory 204812 kb
Host smart-e1b7c163-a2a4-4131-b9e9-96625d28bdcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229673019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1229673019
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1436035659
Short name T595
Test name
Test status
Simulation time 29533558 ps
CPU time 0.77 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:09 PM PDT 24
Peak memory 206792 kb
Host smart-65a98608-57ce-4e3a-91f0-f9ba1347924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436035659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1436035659
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1728976228
Short name T317
Test name
Test status
Simulation time 14178324995 ps
CPU time 94.32 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:46:41 PM PDT 24
Peak memory 253408 kb
Host smart-ec963c6c-3def-4489-a36d-9df5847e0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728976228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1728976228
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.478813098
Short name T301
Test name
Test status
Simulation time 1291522531 ps
CPU time 13.9 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:22 PM PDT 24
Peak memory 237276 kb
Host smart-e0909d80-56b5-4bcd-adcb-f619bc67bdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478813098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.478813098
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3376099591
Short name T772
Test name
Test status
Simulation time 47325139 ps
CPU time 1.05 seconds
Started Mar 31 02:45:01 PM PDT 24
Finished Mar 31 02:45:02 PM PDT 24
Peak memory 218052 kb
Host smart-4b1c8924-1ee6-42bb-bd39-3c1e8b6ea5e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376099591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3376099591
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.190645966
Short name T618
Test name
Test status
Simulation time 18428885 ps
CPU time 0.73 seconds
Started Mar 31 02:44:58 PM PDT 24
Finished Mar 31 02:44:59 PM PDT 24
Peak memory 216236 kb
Host smart-444b360b-a6c3-41e9-9d00-6c27d5e88471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190645966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.190645966
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4036343469
Short name T512
Test name
Test status
Simulation time 8716854251 ps
CPU time 18.26 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:26 PM PDT 24
Peak memory 219176 kb
Host smart-c7a61a87-6fc5-4062-ba07-f4f580b18c92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4036343469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4036343469
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1583118937
Short name T516
Test name
Test status
Simulation time 2629917353 ps
CPU time 45.99 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 216432 kb
Host smart-bac58188-4573-44ed-a296-07e2081d50c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583118937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1583118937
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2469261820
Short name T511
Test name
Test status
Simulation time 3451602032 ps
CPU time 3.93 seconds
Started Mar 31 02:44:57 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 216444 kb
Host smart-dfb25433-2199-4dbc-b9c4-d38971e0bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469261820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2469261820
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1233268231
Short name T482
Test name
Test status
Simulation time 109429807 ps
CPU time 1.14 seconds
Started Mar 31 02:45:00 PM PDT 24
Finished Mar 31 02:45:01 PM PDT 24
Peak memory 206912 kb
Host smart-eff095e2-cb09-4a62-b844-4fa8396fee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233268231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1233268231
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2517333405
Short name T449
Test name
Test status
Simulation time 356961108 ps
CPU time 0.95 seconds
Started Mar 31 02:45:03 PM PDT 24
Finished Mar 31 02:45:05 PM PDT 24
Peak memory 205724 kb
Host smart-6e9f4886-fbb4-42c7-886b-80eee59be3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517333405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2517333405
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.834072772
Short name T564
Test name
Test status
Simulation time 14253738 ps
CPU time 0.72 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:08 PM PDT 24
Peak memory 205276 kb
Host smart-ac2c2192-a826-49df-9549-6903d7f72d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834072772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.834072772
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1849690108
Short name T22
Test name
Test status
Simulation time 26504260 ps
CPU time 0.73 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:08 PM PDT 24
Peak memory 205748 kb
Host smart-f527cd25-1b0c-4953-aaba-a243fad44066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849690108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1849690108
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2835266451
Short name T688
Test name
Test status
Simulation time 4029103170 ps
CPU time 53.32 seconds
Started Mar 31 02:45:08 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 250692 kb
Host smart-c99f1457-062f-4a5e-81b1-fe40aab334c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835266451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2835266451
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3866820167
Short name T547
Test name
Test status
Simulation time 88674537 ps
CPU time 1.11 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:09 PM PDT 24
Peak memory 216748 kb
Host smart-33927161-ce25-4c9c-8f61-5620fab3652d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866820167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3866820167
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1278274588
Short name T441
Test name
Test status
Simulation time 24875426 ps
CPU time 0.74 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:45:07 PM PDT 24
Peak memory 216304 kb
Host smart-d839b6ca-9f28-431a-8b9f-2d279ff5ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278274588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1278274588
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3235103631
Short name T525
Test name
Test status
Simulation time 150018108 ps
CPU time 4.12 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:12 PM PDT 24
Peak memory 218600 kb
Host smart-c2f38925-6357-43b9-bffe-563287952155
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235103631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3235103631
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2751299301
Short name T63
Test name
Test status
Simulation time 58325039722 ps
CPU time 77.11 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:46:25 PM PDT 24
Peak memory 216416 kb
Host smart-02d1038a-1f2b-4330-92ff-ce5effe3de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751299301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2751299301
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.632613162
Short name T521
Test name
Test status
Simulation time 2848436656 ps
CPU time 7 seconds
Started Mar 31 02:45:07 PM PDT 24
Finished Mar 31 02:45:15 PM PDT 24
Peak memory 216380 kb
Host smart-583e0348-c946-41ba-8509-93dc258b6343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632613162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.632613162
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4208432951
Short name T567
Test name
Test status
Simulation time 389058558 ps
CPU time 1.38 seconds
Started Mar 31 02:45:05 PM PDT 24
Finished Mar 31 02:45:08 PM PDT 24
Peak memory 216384 kb
Host smart-f491f95d-5581-496b-bd8c-e5415daeab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208432951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4208432951
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4140603307
Short name T705
Test name
Test status
Simulation time 120436479 ps
CPU time 0.72 seconds
Started Mar 31 02:45:08 PM PDT 24
Finished Mar 31 02:45:10 PM PDT 24
Peak memory 205724 kb
Host smart-a38b2b5a-3999-4fa6-9216-e5b783b7b232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140603307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4140603307
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3217018370
Short name T283
Test name
Test status
Simulation time 9799272108 ps
CPU time 12.27 seconds
Started Mar 31 02:45:06 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 232788 kb
Host smart-2c304e11-cfc5-45b0-b227-2ee3e9299738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217018370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3217018370
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1290397111
Short name T476
Test name
Test status
Simulation time 13913073 ps
CPU time 0.71 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:12 PM PDT 24
Peak memory 204712 kb
Host smart-bb259f55-1834-4674-9f81-55621dfdab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290397111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1290397111
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2451080902
Short name T661
Test name
Test status
Simulation time 26134100 ps
CPU time 0.74 seconds
Started Mar 31 02:45:09 PM PDT 24
Finished Mar 31 02:45:10 PM PDT 24
Peak memory 205440 kb
Host smart-ed3c7619-3e87-4678-a874-6718f0038a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451080902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2451080902
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2744891517
Short name T689
Test name
Test status
Simulation time 98987383500 ps
CPU time 83.98 seconds
Started Mar 31 02:45:14 PM PDT 24
Finished Mar 31 02:46:38 PM PDT 24
Peak memory 250048 kb
Host smart-f9a0e40b-4bd0-4897-863e-397f7a6dedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744891517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2744891517
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3448783453
Short name T496
Test name
Test status
Simulation time 58952580 ps
CPU time 1.04 seconds
Started Mar 31 02:45:11 PM PDT 24
Finished Mar 31 02:45:13 PM PDT 24
Peak memory 216840 kb
Host smart-f0e125a0-895a-4f90-95c1-2c8b46167e2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448783453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3448783453
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1205433808
Short name T242
Test name
Test status
Simulation time 46617625586 ps
CPU time 19.06 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:32 PM PDT 24
Peak memory 234436 kb
Host smart-5669e4c5-4995-444f-8f86-3735d6e89378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205433808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1205433808
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1953899769
Short name T445
Test name
Test status
Simulation time 29876849 ps
CPU time 0.72 seconds
Started Mar 31 02:45:11 PM PDT 24
Finished Mar 31 02:45:11 PM PDT 24
Peak memory 216292 kb
Host smart-105091e9-f200-45f4-b971-5c4ff1b04b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953899769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1953899769
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4190710932
Short name T624
Test name
Test status
Simulation time 4025826368 ps
CPU time 15.01 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:27 PM PDT 24
Peak memory 220840 kb
Host smart-ece9d80a-6537-4bf7-b1c8-2ef81faec535
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4190710932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4190710932
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.298736955
Short name T185
Test name
Test status
Simulation time 5058713588 ps
CPU time 9.71 seconds
Started Mar 31 02:45:15 PM PDT 24
Finished Mar 31 02:45:24 PM PDT 24
Peak memory 216440 kb
Host smart-1b6c08b7-0464-4912-be15-f8f2d71997cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298736955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.298736955
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.413268330
Short name T718
Test name
Test status
Simulation time 14431500056 ps
CPU time 17.3 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:31 PM PDT 24
Peak memory 216436 kb
Host smart-a0bbfbfe-7afb-4343-8cd9-36091228ceba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413268330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.413268330
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2603684115
Short name T641
Test name
Test status
Simulation time 3233265305 ps
CPU time 11.13 seconds
Started Mar 31 02:45:11 PM PDT 24
Finished Mar 31 02:45:23 PM PDT 24
Peak memory 216476 kb
Host smart-8a5235ae-49dd-4251-a1dc-831850bb3ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603684115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2603684115
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1075434822
Short name T719
Test name
Test status
Simulation time 193724855 ps
CPU time 0.9 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:13 PM PDT 24
Peak memory 206580 kb
Host smart-58a22764-4a37-4dec-9660-1f68790af5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075434822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1075434822
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3673834446
Short name T736
Test name
Test status
Simulation time 33767696 ps
CPU time 0.76 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:18 PM PDT 24
Peak memory 204712 kb
Host smart-614d43cb-4239-43ef-a381-eb43f093b6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673834446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3673834446
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2163296463
Short name T660
Test name
Test status
Simulation time 35862986 ps
CPU time 0.78 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:14 PM PDT 24
Peak memory 206436 kb
Host smart-aeb25d54-c1a3-4b3e-8aeb-2c8f8e790d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163296463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2163296463
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3724617653
Short name T741
Test name
Test status
Simulation time 788994004 ps
CPU time 26.35 seconds
Started Mar 31 02:45:18 PM PDT 24
Finished Mar 31 02:45:44 PM PDT 24
Peak memory 256764 kb
Host smart-ae78ed34-36a5-4a2d-988c-7d1ddf4c0fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724617653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3724617653
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1908295880
Short name T184
Test name
Test status
Simulation time 3186175032 ps
CPU time 7.79 seconds
Started Mar 31 02:45:22 PM PDT 24
Finished Mar 31 02:45:30 PM PDT 24
Peak memory 221760 kb
Host smart-863de063-666d-4b3a-94a5-7078a5e2bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908295880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1908295880
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1751011822
Short name T16
Test name
Test status
Simulation time 15633680 ps
CPU time 1.05 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:15 PM PDT 24
Peak memory 216744 kb
Host smart-64511035-e893-436f-a344-5b63679d62fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751011822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1751011822
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3126355019
Short name T281
Test name
Test status
Simulation time 170330153 ps
CPU time 2.96 seconds
Started Mar 31 02:45:11 PM PDT 24
Finished Mar 31 02:45:14 PM PDT 24
Peak memory 221908 kb
Host smart-6b0adc44-1920-46a8-abac-1e25cd28db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126355019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3126355019
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.148669518
Short name T570
Test name
Test status
Simulation time 17958753 ps
CPU time 0.74 seconds
Started Mar 31 02:45:14 PM PDT 24
Finished Mar 31 02:45:15 PM PDT 24
Peak memory 216256 kb
Host smart-ac6c4ab5-bf11-45b5-ba7b-15a4dd83dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148669518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.148669518
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3488842147
Short name T426
Test name
Test status
Simulation time 450327341 ps
CPU time 5.8 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:24 PM PDT 24
Peak memory 222384 kb
Host smart-c28693a8-d3c3-4efa-96dd-29794f429cfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3488842147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3488842147
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.642750736
Short name T577
Test name
Test status
Simulation time 5776844388 ps
CPU time 30.87 seconds
Started Mar 31 02:45:10 PM PDT 24
Finished Mar 31 02:45:42 PM PDT 24
Peak memory 216392 kb
Host smart-a5a89031-f0d0-417d-9f02-8c84289a72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642750736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.642750736
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1588936941
Short name T120
Test name
Test status
Simulation time 17913197345 ps
CPU time 16.1 seconds
Started Mar 31 02:45:13 PM PDT 24
Finished Mar 31 02:45:29 PM PDT 24
Peak memory 216388 kb
Host smart-3748e16b-6d87-40bb-bd29-01dd3262a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588936941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1588936941
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2963076367
Short name T576
Test name
Test status
Simulation time 311372536 ps
CPU time 1.96 seconds
Started Mar 31 02:45:10 PM PDT 24
Finished Mar 31 02:45:13 PM PDT 24
Peak memory 217732 kb
Host smart-986a2e92-f7d9-44b3-b802-0b0878741ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963076367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2963076367
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3332408212
Short name T619
Test name
Test status
Simulation time 458161878 ps
CPU time 1.06 seconds
Started Mar 31 02:45:12 PM PDT 24
Finished Mar 31 02:45:13 PM PDT 24
Peak memory 206784 kb
Host smart-adb0ed6f-ca6c-467e-97ba-8766bae8c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332408212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3332408212
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3950576384
Short name T498
Test name
Test status
Simulation time 39916413 ps
CPU time 0.71 seconds
Started Mar 31 02:43:54 PM PDT 24
Finished Mar 31 02:43:54 PM PDT 24
Peak memory 205296 kb
Host smart-7247690f-5584-47e4-b453-ef48166add99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950576384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
950576384
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2582705173
Short name T717
Test name
Test status
Simulation time 24718371 ps
CPU time 0.76 seconds
Started Mar 31 02:43:51 PM PDT 24
Finished Mar 31 02:43:52 PM PDT 24
Peak memory 206848 kb
Host smart-97bac7f8-aa62-4d5f-96fe-583fb0027d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582705173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2582705173
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2360684040
Short name T314
Test name
Test status
Simulation time 3776249009 ps
CPU time 13.55 seconds
Started Mar 31 02:43:50 PM PDT 24
Finished Mar 31 02:44:05 PM PDT 24
Peak memory 232836 kb
Host smart-a3b8fa66-74a8-4b47-b9c4-8912a2fd3797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360684040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2360684040
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4185425173
Short name T700
Test name
Test status
Simulation time 5431737765 ps
CPU time 43.65 seconds
Started Mar 31 02:43:48 PM PDT 24
Finished Mar 31 02:44:32 PM PDT 24
Peak memory 236692 kb
Host smart-817b3d34-7145-4f34-9c4d-b792cb04aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185425173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4185425173
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3038622499
Short name T532
Test name
Test status
Simulation time 14121949 ps
CPU time 1.03 seconds
Started Mar 31 02:43:50 PM PDT 24
Finished Mar 31 02:43:52 PM PDT 24
Peak memory 216792 kb
Host smart-01e97f40-9bea-44e0-9cca-9c8c9f96419f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038622499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3038622499
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.671793671
Short name T240
Test name
Test status
Simulation time 2506708471 ps
CPU time 10.77 seconds
Started Mar 31 02:43:49 PM PDT 24
Finished Mar 31 02:44:00 PM PDT 24
Peak memory 232820 kb
Host smart-5fceba86-131d-4afd-b690-ed6de1f9360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671793671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.671793671
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2217584865
Short name T41
Test name
Test status
Simulation time 104652262 ps
CPU time 0.75 seconds
Started Mar 31 02:43:49 PM PDT 24
Finished Mar 31 02:43:50 PM PDT 24
Peak memory 216280 kb
Host smart-e25cf1f2-77dc-4bc6-8fe5-cc77ab4394d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217584865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2217584865
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3350228448
Short name T621
Test name
Test status
Simulation time 527187599 ps
CPU time 3.93 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:43:59 PM PDT 24
Peak memory 220120 kb
Host smart-e28e35ee-450a-490a-be5a-e66f517ef8dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3350228448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3350228448
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2151836993
Short name T50
Test name
Test status
Simulation time 79123740 ps
CPU time 1.16 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:43:56 PM PDT 24
Peak memory 235484 kb
Host smart-46b38c18-adb4-4466-8e09-464d96fc9e53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151836993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2151836993
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1329833612
Short name T404
Test name
Test status
Simulation time 40356466753 ps
CPU time 58.23 seconds
Started Mar 31 02:43:48 PM PDT 24
Finished Mar 31 02:44:46 PM PDT 24
Peak memory 216376 kb
Host smart-ab42f110-3a2d-425b-897a-50ac6aa2e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329833612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1329833612
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3273402556
Short name T598
Test name
Test status
Simulation time 1619761182 ps
CPU time 5.6 seconds
Started Mar 31 02:43:50 PM PDT 24
Finished Mar 31 02:43:56 PM PDT 24
Peak memory 216336 kb
Host smart-69ee0c2a-fbcd-41ba-b20e-09e721e7c374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273402556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3273402556
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2849208061
Short name T771
Test name
Test status
Simulation time 2322896957 ps
CPU time 3.57 seconds
Started Mar 31 02:43:50 PM PDT 24
Finished Mar 31 02:43:55 PM PDT 24
Peak memory 216472 kb
Host smart-b89a6dd9-5a82-496a-ba11-ffa45de48077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849208061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2849208061
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2615363472
Short name T652
Test name
Test status
Simulation time 123493979 ps
CPU time 0.84 seconds
Started Mar 31 02:43:50 PM PDT 24
Finished Mar 31 02:43:52 PM PDT 24
Peak memory 205676 kb
Host smart-047a4f21-42e2-4e4a-8ce9-8de8296fffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615363472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2615363472
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.975500782
Short name T655
Test name
Test status
Simulation time 128009503 ps
CPU time 0.73 seconds
Started Mar 31 02:45:24 PM PDT 24
Finished Mar 31 02:45:24 PM PDT 24
Peak memory 205360 kb
Host smart-8e46f5c7-32a7-42b4-97bb-2e1c5241df2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975500782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.975500782
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.52025971
Short name T615
Test name
Test status
Simulation time 46559968 ps
CPU time 0.76 seconds
Started Mar 31 02:45:19 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 206828 kb
Host smart-11f1a852-ca32-4bf8-a125-14766e1cf638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52025971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.52025971
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2920488868
Short name T320
Test name
Test status
Simulation time 677829559 ps
CPU time 21.73 seconds
Started Mar 31 02:45:24 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 251272 kb
Host smart-40857367-1a6b-48e0-bdb6-69dbe80e1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920488868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2920488868
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1801255619
Short name T769
Test name
Test status
Simulation time 624094893 ps
CPU time 3.58 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 223984 kb
Host smart-b6d8a23b-526e-4228-bc8c-0a17a96639ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801255619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1801255619
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1646626161
Short name T746
Test name
Test status
Simulation time 748172437 ps
CPU time 7.76 seconds
Started Mar 31 02:45:19 PM PDT 24
Finished Mar 31 02:45:27 PM PDT 24
Peak memory 223396 kb
Host smart-32281e08-055b-4d13-a7fa-473cc6ea992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646626161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1646626161
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3802053549
Short name T201
Test name
Test status
Simulation time 222805821 ps
CPU time 2.36 seconds
Started Mar 31 02:45:20 PM PDT 24
Finished Mar 31 02:45:23 PM PDT 24
Peak memory 222500 kb
Host smart-c3553fd4-eff0-4240-a28c-6ae66b32da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802053549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3802053549
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.956744176
Short name T759
Test name
Test status
Simulation time 950900554 ps
CPU time 5.73 seconds
Started Mar 31 02:45:25 PM PDT 24
Finished Mar 31 02:45:30 PM PDT 24
Peak memory 222440 kb
Host smart-149ef544-dd08-4b87-b2cd-70d7e43e714e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=956744176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.956744176
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.660523254
Short name T737
Test name
Test status
Simulation time 2101004233 ps
CPU time 16.15 seconds
Started Mar 31 02:45:17 PM PDT 24
Finished Mar 31 02:45:33 PM PDT 24
Peak memory 219412 kb
Host smart-90a530bf-ee03-452e-91a6-e9e0721b0433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660523254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.660523254
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2966756070
Short name T644
Test name
Test status
Simulation time 602355556 ps
CPU time 3.82 seconds
Started Mar 31 02:45:18 PM PDT 24
Finished Mar 31 02:45:22 PM PDT 24
Peak memory 216100 kb
Host smart-4f9bcedf-f893-4e5a-ad71-b3f63ad3486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966756070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2966756070
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3944290626
Short name T645
Test name
Test status
Simulation time 529612338 ps
CPU time 4.26 seconds
Started Mar 31 02:45:16 PM PDT 24
Finished Mar 31 02:45:20 PM PDT 24
Peak memory 216416 kb
Host smart-bcb57130-68df-4dd3-a546-938f3ab96ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944290626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3944290626
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3217423384
Short name T756
Test name
Test status
Simulation time 57184582 ps
CPU time 0.75 seconds
Started Mar 31 02:45:19 PM PDT 24
Finished Mar 31 02:45:19 PM PDT 24
Peak memory 205756 kb
Host smart-f6b5a3d3-e339-49bc-9d45-a203401b736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217423384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3217423384
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1288236450
Short name T659
Test name
Test status
Simulation time 38764319 ps
CPU time 0.7 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:45:32 PM PDT 24
Peak memory 204740 kb
Host smart-0dec2b32-80ca-4471-969a-68530920a60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288236450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1288236450
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3143533314
Short name T483
Test name
Test status
Simulation time 18758391 ps
CPU time 0.78 seconds
Started Mar 31 02:45:25 PM PDT 24
Finished Mar 31 02:45:25 PM PDT 24
Peak memory 205324 kb
Host smart-472f34a3-ad51-44a1-8410-e9bbbb6c186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143533314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3143533314
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1606053223
Short name T309
Test name
Test status
Simulation time 809044094 ps
CPU time 17.47 seconds
Started Mar 31 02:45:30 PM PDT 24
Finished Mar 31 02:45:48 PM PDT 24
Peak memory 232692 kb
Host smart-bf7b232c-81a7-422e-a22b-ca8c06d9096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606053223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1606053223
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.679147968
Short name T295
Test name
Test status
Simulation time 448333048 ps
CPU time 2.14 seconds
Started Mar 31 02:45:26 PM PDT 24
Finished Mar 31 02:45:29 PM PDT 24
Peak memory 218916 kb
Host smart-43581929-073f-40cb-9dcd-495edc20a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679147968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.679147968
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3195666683
Short name T524
Test name
Test status
Simulation time 10859921928 ps
CPU time 27.55 seconds
Started Mar 31 02:45:33 PM PDT 24
Finished Mar 31 02:46:01 PM PDT 24
Peak memory 218756 kb
Host smart-3335709e-4227-41ce-bd80-9941bc709859
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3195666683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3195666683
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3465352539
Short name T706
Test name
Test status
Simulation time 23326654928 ps
CPU time 36.72 seconds
Started Mar 31 02:45:25 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 216464 kb
Host smart-eaff189a-3840-4eff-bdd5-e7dad8155afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465352539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3465352539
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.866394901
Short name T630
Test name
Test status
Simulation time 8122974681 ps
CPU time 25.11 seconds
Started Mar 31 02:45:25 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 216408 kb
Host smart-fa4d351f-8ce5-4a0b-a483-ee71f6598c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866394901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.866394901
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.279510686
Short name T625
Test name
Test status
Simulation time 136942525 ps
CPU time 4.37 seconds
Started Mar 31 02:45:22 PM PDT 24
Finished Mar 31 02:45:27 PM PDT 24
Peak memory 216320 kb
Host smart-ce1aad2f-521a-4a19-9033-863c3257587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279510686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.279510686
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1428331373
Short name T542
Test name
Test status
Simulation time 85136657 ps
CPU time 1.07 seconds
Started Mar 31 02:45:24 PM PDT 24
Finished Mar 31 02:45:26 PM PDT 24
Peak memory 206712 kb
Host smart-3582686b-bba8-42db-9af5-04add4114510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428331373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1428331373
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3290824834
Short name T593
Test name
Test status
Simulation time 751076633 ps
CPU time 3.3 seconds
Started Mar 31 02:45:27 PM PDT 24
Finished Mar 31 02:45:31 PM PDT 24
Peak memory 223376 kb
Host smart-063d7bcd-4450-432e-b440-d8460105f621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290824834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3290824834
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1695691294
Short name T687
Test name
Test status
Simulation time 13108653 ps
CPU time 0.74 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:42 PM PDT 24
Peak memory 205688 kb
Host smart-d7785170-9140-464c-91eb-0b7fe2ceb2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695691294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1695691294
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.74941144
Short name T455
Test name
Test status
Simulation time 104445845 ps
CPU time 0.85 seconds
Started Mar 31 02:45:33 PM PDT 24
Finished Mar 31 02:45:35 PM PDT 24
Peak memory 206728 kb
Host smart-fc490121-2e25-4834-b17a-5d9bba2da66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74941144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.74941144
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_intercept.415726494
Short name T236
Test name
Test status
Simulation time 116858563 ps
CPU time 3.43 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:45:34 PM PDT 24
Peak memory 222284 kb
Host smart-f8510a32-52f7-4e7f-8e68-962f6fa49a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415726494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.415726494
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1250210784
Short name T360
Test name
Test status
Simulation time 3609770747 ps
CPU time 16.69 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:45:49 PM PDT 24
Peak memory 234412 kb
Host smart-8972973a-4a2e-456e-be10-3aa3b44cf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250210784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1250210784
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3059501368
Short name T279
Test name
Test status
Simulation time 858327516 ps
CPU time 7.84 seconds
Started Mar 31 02:45:30 PM PDT 24
Finished Mar 31 02:45:39 PM PDT 24
Peak memory 223956 kb
Host smart-80c0d871-a234-4faa-ad36-98c5166117c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059501368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3059501368
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3870839204
Short name T565
Test name
Test status
Simulation time 867573510 ps
CPU time 10.03 seconds
Started Mar 31 02:45:34 PM PDT 24
Finished Mar 31 02:45:45 PM PDT 24
Peak memory 220492 kb
Host smart-34072696-9bb6-40dd-93ac-392e1596093b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3870839204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3870839204
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1996530143
Short name T752
Test name
Test status
Simulation time 1498156688 ps
CPU time 2.86 seconds
Started Mar 31 02:45:34 PM PDT 24
Finished Mar 31 02:45:37 PM PDT 24
Peak memory 216400 kb
Host smart-a10e6683-665e-467a-8241-8b4095072601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996530143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1996530143
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2744034620
Short name T95
Test name
Test status
Simulation time 2728489841 ps
CPU time 6.47 seconds
Started Mar 31 02:45:31 PM PDT 24
Finished Mar 31 02:45:39 PM PDT 24
Peak memory 216316 kb
Host smart-b0dd14a8-84cd-4589-b26e-c7f37aba9ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744034620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2744034620
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2420459308
Short name T473
Test name
Test status
Simulation time 48753463 ps
CPU time 1.08 seconds
Started Mar 31 02:45:33 PM PDT 24
Finished Mar 31 02:45:36 PM PDT 24
Peak memory 207736 kb
Host smart-bfbf8f57-fd5c-4e7a-a49c-6d6852b33674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420459308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2420459308
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.852732789
Short name T720
Test name
Test status
Simulation time 112048918 ps
CPU time 0.7 seconds
Started Mar 31 02:45:32 PM PDT 24
Finished Mar 31 02:45:34 PM PDT 24
Peak memory 205688 kb
Host smart-99836a07-f841-45bc-9e43-991014345cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852732789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.852732789
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1654770249
Short name T15
Test name
Test status
Simulation time 15589650 ps
CPU time 0.73 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:42 PM PDT 24
Peak memory 205360 kb
Host smart-da293b08-ccd4-4457-be3c-777cb9ec5b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654770249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1654770249
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2072364467
Short name T216
Test name
Test status
Simulation time 1933053423 ps
CPU time 5.66 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:47 PM PDT 24
Peak memory 233704 kb
Host smart-e99ebe9d-8fe1-4aab-a932-b65b8cb0d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072364467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2072364467
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1339699260
Short name T650
Test name
Test status
Simulation time 15770548 ps
CPU time 0.75 seconds
Started Mar 31 02:45:45 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 205708 kb
Host smart-02793876-7d70-4b95-9253-402720d8f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339699260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1339699260
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2094188464
Short name T371
Test name
Test status
Simulation time 1133240709 ps
CPU time 27.51 seconds
Started Mar 31 02:45:41 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 240216 kb
Host smart-47de491a-67e6-4dd1-8325-ea1e80393f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094188464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2094188464
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1203566806
Short name T109
Test name
Test status
Simulation time 536884313 ps
CPU time 5.8 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:47 PM PDT 24
Peak memory 218560 kb
Host smart-c5f47162-ea84-4790-8f13-f3aaa37879d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203566806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1203566806
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.237287240
Short name T428
Test name
Test status
Simulation time 147742935 ps
CPU time 4.79 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 222796 kb
Host smart-7bd56a13-d215-4563-b036-f209a2286d01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=237287240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.237287240
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.422067644
Short name T757
Test name
Test status
Simulation time 5364192540 ps
CPU time 14.75 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:56 PM PDT 24
Peak memory 216428 kb
Host smart-ef3509b8-23cc-435c-bcc1-1d290525b5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422067644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.422067644
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3161765858
Short name T538
Test name
Test status
Simulation time 25662341455 ps
CPU time 21.06 seconds
Started Mar 31 02:45:37 PM PDT 24
Finished Mar 31 02:45:58 PM PDT 24
Peak memory 216348 kb
Host smart-4aea9a7d-75e1-4abb-a206-8d465aa4b421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161765858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3161765858
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2375752366
Short name T65
Test name
Test status
Simulation time 130690349 ps
CPU time 1.1 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:45:43 PM PDT 24
Peak memory 207660 kb
Host smart-805ca49e-5f43-48c9-b49d-8b883320bf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375752366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2375752366
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3785730694
Short name T770
Test name
Test status
Simulation time 186278354 ps
CPU time 0.77 seconds
Started Mar 31 02:45:38 PM PDT 24
Finished Mar 31 02:45:39 PM PDT 24
Peak memory 205728 kb
Host smart-a0441b62-901c-4b65-b7a5-ae391ede3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785730694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3785730694
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2913371414
Short name T486
Test name
Test status
Simulation time 26818079 ps
CPU time 0.72 seconds
Started Mar 31 02:45:46 PM PDT 24
Finished Mar 31 02:45:47 PM PDT 24
Peak memory 204792 kb
Host smart-2e5491f0-6b5e-445d-ba9c-6cf9077c7260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913371414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2913371414
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3823480301
Short name T328
Test name
Test status
Simulation time 108286863 ps
CPU time 2.23 seconds
Started Mar 31 02:45:37 PM PDT 24
Finished Mar 31 02:45:40 PM PDT 24
Peak memory 219988 kb
Host smart-47802c92-cf8e-4a81-b6e6-e5d68c6c92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823480301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3823480301
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2376968030
Short name T457
Test name
Test status
Simulation time 60276751 ps
CPU time 0.8 seconds
Started Mar 31 02:45:37 PM PDT 24
Finished Mar 31 02:45:39 PM PDT 24
Peak memory 206516 kb
Host smart-b1c244b8-831f-4429-9516-d3bcc9f0640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376968030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2376968030
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.107207496
Short name T734
Test name
Test status
Simulation time 1778215980 ps
CPU time 18.43 seconds
Started Mar 31 02:45:40 PM PDT 24
Finished Mar 31 02:46:00 PM PDT 24
Peak memory 250236 kb
Host smart-08124390-4711-42d8-95d7-70dc925e7110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107207496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.107207496
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3515157910
Short name T739
Test name
Test status
Simulation time 2972979647 ps
CPU time 3.69 seconds
Started Mar 31 02:45:39 PM PDT 24
Finished Mar 31 02:45:44 PM PDT 24
Peak memory 222308 kb
Host smart-3ffd85ef-fae0-4ba8-a75d-8f9fc7f18fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515157910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3515157910
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3980887826
Short name T605
Test name
Test status
Simulation time 2509797800 ps
CPU time 16.36 seconds
Started Mar 31 02:45:43 PM PDT 24
Finished Mar 31 02:45:59 PM PDT 24
Peak memory 219068 kb
Host smart-38dc1e7b-c5dc-4a17-8796-ec86cd6c6257
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980887826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3980887826
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3716539040
Short name T724
Test name
Test status
Simulation time 65772243 ps
CPU time 0.96 seconds
Started Mar 31 02:45:50 PM PDT 24
Finished Mar 31 02:45:51 PM PDT 24
Peak memory 206684 kb
Host smart-be847607-3913-425d-81e2-44c5d4d2029f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716539040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3716539040
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2083428393
Short name T541
Test name
Test status
Simulation time 3032307434 ps
CPU time 12.36 seconds
Started Mar 31 02:45:38 PM PDT 24
Finished Mar 31 02:45:51 PM PDT 24
Peak memory 216440 kb
Host smart-24654c06-a907-49f0-b314-08a31989573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083428393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2083428393
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3090947515
Short name T529
Test name
Test status
Simulation time 796721939 ps
CPU time 6.16 seconds
Started Mar 31 02:45:41 PM PDT 24
Finished Mar 31 02:45:49 PM PDT 24
Peak memory 216560 kb
Host smart-1b901400-2b44-4fa4-885d-beca50ddfed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090947515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3090947515
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3207297282
Short name T634
Test name
Test status
Simulation time 102720717 ps
CPU time 1.1 seconds
Started Mar 31 02:45:41 PM PDT 24
Finished Mar 31 02:45:44 PM PDT 24
Peak memory 206748 kb
Host smart-61b4e301-b064-472f-b7b4-0d16e01995a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207297282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3207297282
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2220743300
Short name T452
Test name
Test status
Simulation time 39929652 ps
CPU time 0.7 seconds
Started Mar 31 02:45:49 PM PDT 24
Finished Mar 31 02:45:50 PM PDT 24
Peak memory 204788 kb
Host smart-1f8f56a4-0a65-4fff-8c5f-b6ab27055504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220743300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2220743300
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.415335577
Short name T714
Test name
Test status
Simulation time 14211020 ps
CPU time 0.79 seconds
Started Mar 31 02:45:45 PM PDT 24
Finished Mar 31 02:45:46 PM PDT 24
Peak memory 205488 kb
Host smart-07185062-868d-474b-8b9e-0cf653059517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415335577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.415335577
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1454784313
Short name T318
Test name
Test status
Simulation time 1027900585 ps
CPU time 21.46 seconds
Started Mar 31 02:45:49 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 232744 kb
Host smart-150e43c3-afea-45bd-8d67-184673eb47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454784313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1454784313
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1421442205
Short name T701
Test name
Test status
Simulation time 3405751058 ps
CPU time 9.09 seconds
Started Mar 31 02:45:46 PM PDT 24
Finished Mar 31 02:45:55 PM PDT 24
Peak memory 216884 kb
Host smart-810e984f-33e0-49d3-852c-b58450dbddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421442205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1421442205
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3697667442
Short name T246
Test name
Test status
Simulation time 695177991 ps
CPU time 12.38 seconds
Started Mar 31 02:45:46 PM PDT 24
Finished Mar 31 02:45:58 PM PDT 24
Peak memory 218784 kb
Host smart-f3c8403d-27a4-4261-ba91-58066da80954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697667442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3697667442
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1196134553
Short name T676
Test name
Test status
Simulation time 334113048 ps
CPU time 4.59 seconds
Started Mar 31 02:45:48 PM PDT 24
Finished Mar 31 02:45:52 PM PDT 24
Peak memory 222388 kb
Host smart-3882546d-dac8-4541-9d69-7feae93ac54d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1196134553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1196134553
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.920424194
Short name T395
Test name
Test status
Simulation time 4877628609 ps
CPU time 36.74 seconds
Started Mar 31 02:45:46 PM PDT 24
Finished Mar 31 02:46:23 PM PDT 24
Peak memory 216492 kb
Host smart-8a6a9cf4-cef7-4cca-8ebe-2798a764aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920424194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.920424194
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1369323065
Short name T657
Test name
Test status
Simulation time 2417841747 ps
CPU time 5.83 seconds
Started Mar 31 02:45:50 PM PDT 24
Finished Mar 31 02:45:56 PM PDT 24
Peak memory 216400 kb
Host smart-e5ffe8b1-b22c-4f8f-9168-94f7ca95c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369323065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1369323065
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3404637288
Short name T563
Test name
Test status
Simulation time 2880962887 ps
CPU time 2.57 seconds
Started Mar 31 02:45:47 PM PDT 24
Finished Mar 31 02:45:49 PM PDT 24
Peak memory 216384 kb
Host smart-aa29a8e9-0650-4b53-83b3-f0e1ef34b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404637288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3404637288
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2083107260
Short name T643
Test name
Test status
Simulation time 193992212 ps
CPU time 0.8 seconds
Started Mar 31 02:45:47 PM PDT 24
Finished Mar 31 02:45:48 PM PDT 24
Peak memory 205748 kb
Host smart-88c2a45e-6cd5-4dc6-8316-dfad54ad4af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083107260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2083107260
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2684359616
Short name T433
Test name
Test status
Simulation time 33345282 ps
CPU time 0.7 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:53 PM PDT 24
Peak memory 204780 kb
Host smart-de6e5f4d-40af-4295-aede-04f0c0a81f91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684359616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2684359616
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1856024628
Short name T552
Test name
Test status
Simulation time 48140007 ps
CPU time 0.76 seconds
Started Mar 31 02:45:47 PM PDT 24
Finished Mar 31 02:45:48 PM PDT 24
Peak memory 206840 kb
Host smart-4509a23a-f045-4ba6-8f7d-8755a7ec96a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856024628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1856024628
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1880115927
Short name T322
Test name
Test status
Simulation time 9832587908 ps
CPU time 71.79 seconds
Started Mar 31 02:45:50 PM PDT 24
Finished Mar 31 02:47:02 PM PDT 24
Peak memory 239452 kb
Host smart-2f61274b-b089-4af8-8214-eb836ebf0930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880115927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1880115927
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3481277894
Short name T286
Test name
Test status
Simulation time 139886573 ps
CPU time 4.11 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:57 PM PDT 24
Peak memory 218544 kb
Host smart-886e36df-922d-4ec1-8e6d-f7d7ec894613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481277894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3481277894
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1498515011
Short name T207
Test name
Test status
Simulation time 5356151569 ps
CPU time 9.69 seconds
Started Mar 31 02:45:48 PM PDT 24
Finished Mar 31 02:45:58 PM PDT 24
Peak memory 224592 kb
Host smart-89df82ce-e878-459e-bf29-4b01fdcb1644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498515011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1498515011
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.447776575
Short name T633
Test name
Test status
Simulation time 491209972 ps
CPU time 4.28 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:56 PM PDT 24
Peak memory 222916 kb
Host smart-a446f87f-63d1-4db0-ac99-7560a26ac88d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=447776575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.447776575
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2790135330
Short name T549
Test name
Test status
Simulation time 492122376 ps
CPU time 2.93 seconds
Started Mar 31 02:45:50 PM PDT 24
Finished Mar 31 02:45:53 PM PDT 24
Peak memory 216324 kb
Host smart-e2016f2e-e628-4d1b-9fb7-4e30e5e586e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790135330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2790135330
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1024010409
Short name T61
Test name
Test status
Simulation time 16886653637 ps
CPU time 15.41 seconds
Started Mar 31 02:45:50 PM PDT 24
Finished Mar 31 02:46:05 PM PDT 24
Peak memory 216372 kb
Host smart-b7237075-0d4a-446e-939c-52530366f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024010409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1024010409
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1970102107
Short name T581
Test name
Test status
Simulation time 56974458 ps
CPU time 2.97 seconds
Started Mar 31 02:45:51 PM PDT 24
Finished Mar 31 02:45:54 PM PDT 24
Peak memory 216408 kb
Host smart-7e3adcce-e9a0-4d6f-b81b-2b6b760effdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970102107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1970102107
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2423536482
Short name T546
Test name
Test status
Simulation time 153727219 ps
CPU time 0.97 seconds
Started Mar 31 02:45:51 PM PDT 24
Finished Mar 31 02:45:52 PM PDT 24
Peak memory 205708 kb
Host smart-c2555c4c-f4cc-4de9-9c68-d8357a190763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423536482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2423536482
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2043724725
Short name T196
Test name
Test status
Simulation time 1260707163 ps
CPU time 6.28 seconds
Started Mar 31 02:45:51 PM PDT 24
Finished Mar 31 02:45:57 PM PDT 24
Peak memory 218792 kb
Host smart-16ede1c9-b6ce-4488-a442-530c8678b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043724725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2043724725
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2862908555
Short name T607
Test name
Test status
Simulation time 17310930 ps
CPU time 0.73 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:53 PM PDT 24
Peak memory 205388 kb
Host smart-2e672876-729f-47f2-85bc-408305895732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862908555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2862908555
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3246677777
Short name T678
Test name
Test status
Simulation time 22204518 ps
CPU time 0.87 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:45:54 PM PDT 24
Peak memory 206344 kb
Host smart-5e15af54-a7c1-4a74-a00a-885b9a4444bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246677777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3246677777
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.422778440
Short name T302
Test name
Test status
Simulation time 530660244 ps
CPU time 10.58 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 223456 kb
Host smart-40b484fa-d10e-40c7-8be0-cc6705b50864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422778440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.422778440
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3574620943
Short name T329
Test name
Test status
Simulation time 657408054 ps
CPU time 2.8 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:45:56 PM PDT 24
Peak memory 222592 kb
Host smart-cb15fa6d-78db-4681-851c-dec5e9e386f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574620943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3574620943
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1952777550
Short name T731
Test name
Test status
Simulation time 1787750418 ps
CPU time 10.19 seconds
Started Mar 31 02:45:51 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 222768 kb
Host smart-821e9bfd-e47e-4ef6-8efe-ddcfadd887b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1952777550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1952777550
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.946088625
Short name T55
Test name
Test status
Simulation time 3305218666 ps
CPU time 16.64 seconds
Started Mar 31 02:45:54 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 216492 kb
Host smart-19495ff5-e1a2-4bda-bfff-e90c0681a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946088625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.946088625
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3229469102
Short name T584
Test name
Test status
Simulation time 8905784077 ps
CPU time 10.17 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:46:04 PM PDT 24
Peak memory 216352 kb
Host smart-2922d654-a8a4-4c86-951a-a0551125b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229469102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3229469102
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2676279647
Short name T566
Test name
Test status
Simulation time 257543652 ps
CPU time 2.69 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:45:56 PM PDT 24
Peak memory 216384 kb
Host smart-5bc9f183-ea41-420e-a258-7f3d2c231d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676279647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2676279647
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2548023752
Short name T513
Test name
Test status
Simulation time 76920423 ps
CPU time 0.9 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:45:54 PM PDT 24
Peak memory 205732 kb
Host smart-42349b9b-6e01-47b9-9a37-c3b8f41e9d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548023752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2548023752
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1716590271
Short name T327
Test name
Test status
Simulation time 6419585452 ps
CPU time 22.02 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:46:15 PM PDT 24
Peak memory 219424 kb
Host smart-d2d857e0-ce13-4f99-ad4b-c01523f98bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716590271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1716590271
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3467153697
Short name T579
Test name
Test status
Simulation time 13165393 ps
CPU time 0.72 seconds
Started Mar 31 02:45:59 PM PDT 24
Finished Mar 31 02:46:00 PM PDT 24
Peak memory 205324 kb
Host smart-cc26725a-dcfb-419f-905e-32bf2d0731a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467153697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3467153697
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4136128515
Short name T454
Test name
Test status
Simulation time 37062087 ps
CPU time 0.83 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:53 PM PDT 24
Peak memory 206872 kb
Host smart-361aa97c-8c99-41c5-bb0e-db30b9987a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136128515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4136128515
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1787431100
Short name T740
Test name
Test status
Simulation time 1751950107 ps
CPU time 38.23 seconds
Started Mar 31 02:45:57 PM PDT 24
Finished Mar 31 02:46:35 PM PDT 24
Peak memory 254228 kb
Host smart-225da722-6ffb-4217-a64e-a8dfb1803c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787431100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1787431100
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.896896249
Short name T285
Test name
Test status
Simulation time 245059821 ps
CPU time 6.12 seconds
Started Mar 31 02:46:04 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 224224 kb
Host smart-d08d852c-4b7e-4c41-8bbd-18b8a7171900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896896249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.896896249
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3085041836
Short name T220
Test name
Test status
Simulation time 724849134 ps
CPU time 3.49 seconds
Started Mar 31 02:45:58 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 224256 kb
Host smart-88f15143-0bd3-4e40-b940-b7fb6e935122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085041836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3085041836
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1061623668
Short name T620
Test name
Test status
Simulation time 3654951171 ps
CPU time 9.77 seconds
Started Mar 31 02:45:57 PM PDT 24
Finished Mar 31 02:46:07 PM PDT 24
Peak memory 221288 kb
Host smart-63450980-d602-4069-9d47-8d99df1d2de8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1061623668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1061623668
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3931997814
Short name T410
Test name
Test status
Simulation time 11501780979 ps
CPU time 62.44 seconds
Started Mar 31 02:45:53 PM PDT 24
Finished Mar 31 02:46:55 PM PDT 24
Peak memory 216432 kb
Host smart-596ab943-044a-4c74-8efd-5bc18f35a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931997814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3931997814
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2828194788
Short name T484
Test name
Test status
Simulation time 866381760 ps
CPU time 6.26 seconds
Started Mar 31 02:45:52 PM PDT 24
Finished Mar 31 02:45:58 PM PDT 24
Peak memory 216348 kb
Host smart-543f6204-c2e4-48e0-a769-39825a7c5145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828194788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2828194788
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3327916544
Short name T725
Test name
Test status
Simulation time 742901263 ps
CPU time 1.97 seconds
Started Mar 31 02:46:02 PM PDT 24
Finished Mar 31 02:46:04 PM PDT 24
Peak memory 216344 kb
Host smart-3f6bbfc7-7e9d-4b5f-b856-dba86359370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327916544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3327916544
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1782042084
Short name T658
Test name
Test status
Simulation time 80751783 ps
CPU time 0.97 seconds
Started Mar 31 02:46:04 PM PDT 24
Finished Mar 31 02:46:05 PM PDT 24
Peak memory 205372 kb
Host smart-07f33d93-9f37-4df0-bdd8-df85c0fafb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782042084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1782042084
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.295492219
Short name T421
Test name
Test status
Simulation time 42177903 ps
CPU time 0.71 seconds
Started Mar 31 02:46:09 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 205220 kb
Host smart-e1247fb2-80ce-41e0-b673-32b4aae1b97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295492219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.295492219
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.918046984
Short name T715
Test name
Test status
Simulation time 70551292 ps
CPU time 0.73 seconds
Started Mar 31 02:45:58 PM PDT 24
Finished Mar 31 02:45:59 PM PDT 24
Peak memory 205380 kb
Host smart-3481951d-c09d-4dba-9771-c19e307a2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918046984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.918046984
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2289039605
Short name T183
Test name
Test status
Simulation time 7200447953 ps
CPU time 42.43 seconds
Started Mar 31 02:46:00 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 240972 kb
Host smart-89650376-fdb7-4a29-817c-5957885da8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289039605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2289039605
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3885837303
Short name T350
Test name
Test status
Simulation time 14288315149 ps
CPU time 30.25 seconds
Started Mar 31 02:46:01 PM PDT 24
Finished Mar 31 02:46:31 PM PDT 24
Peak memory 217964 kb
Host smart-6e4ef1de-8ab0-485d-99a0-f0fead9dbf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885837303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3885837303
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2532812258
Short name T270
Test name
Test status
Simulation time 21388437114 ps
CPU time 173.41 seconds
Started Mar 31 02:45:58 PM PDT 24
Finished Mar 31 02:48:52 PM PDT 24
Peak memory 234952 kb
Host smart-255798c2-238f-4c45-8283-5ce9e00e1533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532812258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2532812258
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2691873395
Short name T54
Test name
Test status
Simulation time 63626354999 ps
CPU time 18.14 seconds
Started Mar 31 02:45:58 PM PDT 24
Finished Mar 31 02:46:16 PM PDT 24
Peak memory 222880 kb
Host smart-8e10224f-8ad3-457a-862c-ba68b33962fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691873395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2691873395
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1002615061
Short name T536
Test name
Test status
Simulation time 743180736 ps
CPU time 9.4 seconds
Started Mar 31 02:45:58 PM PDT 24
Finished Mar 31 02:46:07 PM PDT 24
Peak memory 221340 kb
Host smart-10b1a205-794f-4c72-a1da-0725a1ba58d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002615061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1002615061
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1532472065
Short name T758
Test name
Test status
Simulation time 664076730 ps
CPU time 6.13 seconds
Started Mar 31 02:46:01 PM PDT 24
Finished Mar 31 02:46:07 PM PDT 24
Peak memory 216472 kb
Host smart-6cb22b21-8eac-4d37-a838-c686c995dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532472065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1532472065
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2127570945
Short name T62
Test name
Test status
Simulation time 1957823669 ps
CPU time 7.37 seconds
Started Mar 31 02:45:59 PM PDT 24
Finished Mar 31 02:46:06 PM PDT 24
Peak memory 216324 kb
Host smart-7a8f73af-3412-42c5-b455-451c90a8b845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127570945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2127570945
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.520190107
Short name T612
Test name
Test status
Simulation time 82690292 ps
CPU time 1.39 seconds
Started Mar 31 02:45:59 PM PDT 24
Finished Mar 31 02:46:01 PM PDT 24
Peak memory 216224 kb
Host smart-5b9f9246-db0f-4742-b83e-c5cfefcbbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520190107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.520190107
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2810799132
Short name T456
Test name
Test status
Simulation time 76672594 ps
CPU time 0.97 seconds
Started Mar 31 02:46:01 PM PDT 24
Finished Mar 31 02:46:02 PM PDT 24
Peak memory 206728 kb
Host smart-bf03b69f-26fe-4fcb-87f6-c0d0c892a3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810799132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2810799132
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4129207784
Short name T255
Test name
Test status
Simulation time 6220572867 ps
CPU time 10.29 seconds
Started Mar 31 02:45:59 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 230148 kb
Host smart-b599a17b-6398-476a-876a-69aa8a22c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129207784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4129207784
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2329035329
Short name T491
Test name
Test status
Simulation time 12356805 ps
CPU time 0.74 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:01 PM PDT 24
Peak memory 205368 kb
Host smart-7846933c-d6cc-446a-9cd2-75ead320e083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329035329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
329035329
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.814232582
Short name T104
Test name
Test status
Simulation time 344866885 ps
CPU time 4.03 seconds
Started Mar 31 02:43:59 PM PDT 24
Finished Mar 31 02:44:03 PM PDT 24
Peak memory 232524 kb
Host smart-10edbe33-6b24-4a26-aca0-abf210806335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814232582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.814232582
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.204040863
Short name T677
Test name
Test status
Simulation time 33020183 ps
CPU time 0.81 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:43:56 PM PDT 24
Peak memory 206804 kb
Host smart-48fe0840-6574-4e0b-a520-402f6a6209c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204040863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.204040863
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2321930347
Short name T181
Test name
Test status
Simulation time 627855152 ps
CPU time 7.93 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:44:03 PM PDT 24
Peak memory 222992 kb
Host smart-deb20a74-1613-4dda-8ed0-bb390e953e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321930347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2321930347
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3409401950
Short name T414
Test name
Test status
Simulation time 7124657038 ps
CPU time 11.15 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:11 PM PDT 24
Peak memory 218628 kb
Host smart-5ad93bca-54c9-40f0-9bc3-b3c535afc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409401950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3409401950
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.633813091
Short name T578
Test name
Test status
Simulation time 48954264 ps
CPU time 1.05 seconds
Started Mar 31 02:43:54 PM PDT 24
Finished Mar 31 02:43:55 PM PDT 24
Peak memory 216788 kb
Host smart-9a600746-c73f-4964-938e-f253ec37a6b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633813091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.633813091
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1403059724
Short name T665
Test name
Test status
Simulation time 311735547 ps
CPU time 5.08 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:44:00 PM PDT 24
Peak memory 223276 kb
Host smart-605451dd-0ced-46b0-b81d-cbe41ff5711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403059724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1403059724
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2060891052
Short name T510
Test name
Test status
Simulation time 77859747 ps
CPU time 0.78 seconds
Started Mar 31 02:43:56 PM PDT 24
Finished Mar 31 02:43:57 PM PDT 24
Peak memory 216252 kb
Host smart-a9ba8759-e1ad-4a31-ab54-763eec61b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060891052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2060891052
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.899393832
Short name T472
Test name
Test status
Simulation time 751864115 ps
CPU time 3.43 seconds
Started Mar 31 02:43:59 PM PDT 24
Finished Mar 31 02:44:03 PM PDT 24
Peak memory 220416 kb
Host smart-1ee8185d-88b4-4ac2-a1b5-f12f9defe9d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899393832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.899393832
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.600538649
Short name T46
Test name
Test status
Simulation time 84938820 ps
CPU time 1.34 seconds
Started Mar 31 02:44:01 PM PDT 24
Finished Mar 31 02:44:03 PM PDT 24
Peak memory 236008 kb
Host smart-6bacf578-4082-458f-965a-92f322eb0a66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600538649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.600538649
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3029714872
Short name T398
Test name
Test status
Simulation time 4430611501 ps
CPU time 27.26 seconds
Started Mar 31 02:43:56 PM PDT 24
Finished Mar 31 02:44:23 PM PDT 24
Peak memory 216424 kb
Host smart-c2522978-ec32-42cd-802a-4979a42213e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029714872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3029714872
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3392587228
Short name T53
Test name
Test status
Simulation time 945228603 ps
CPU time 6.04 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:44:01 PM PDT 24
Peak memory 216300 kb
Host smart-1bbf6b11-3c4f-4d04-8a41-ebc19087fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392587228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3392587228
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3884210774
Short name T540
Test name
Test status
Simulation time 533382535 ps
CPU time 4.04 seconds
Started Mar 31 02:43:54 PM PDT 24
Finished Mar 31 02:43:58 PM PDT 24
Peak memory 216552 kb
Host smart-ba303d89-4c78-4192-a57d-b7ebb60dcd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884210774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3884210774
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4039406364
Short name T499
Test name
Test status
Simulation time 276826644 ps
CPU time 1.03 seconds
Started Mar 31 02:43:55 PM PDT 24
Finished Mar 31 02:43:57 PM PDT 24
Peak memory 206772 kb
Host smart-0d3a2c30-3e8b-40a7-8a9b-8d5d9535f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039406364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4039406364
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2893853103
Short name T431
Test name
Test status
Simulation time 18233879 ps
CPU time 0.68 seconds
Started Mar 31 02:46:14 PM PDT 24
Finished Mar 31 02:46:15 PM PDT 24
Peak memory 205080 kb
Host smart-1203b99d-008f-44e2-8b6a-66a3630abf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893853103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2893853103
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3195329549
Short name T227
Test name
Test status
Simulation time 1543259691 ps
CPU time 5.48 seconds
Started Mar 31 02:46:07 PM PDT 24
Finished Mar 31 02:46:12 PM PDT 24
Peak memory 217404 kb
Host smart-c73a1942-75a3-448a-a2eb-fbe27e1745fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195329549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3195329549
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2214577131
Short name T726
Test name
Test status
Simulation time 35642001 ps
CPU time 0.78 seconds
Started Mar 31 02:46:07 PM PDT 24
Finished Mar 31 02:46:08 PM PDT 24
Peak memory 206504 kb
Host smart-0d7c07c2-ea6e-48e3-8ff4-d8c88ec8d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214577131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2214577131
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2249289217
Short name T368
Test name
Test status
Simulation time 424052382 ps
CPU time 11.84 seconds
Started Mar 31 02:46:03 PM PDT 24
Finished Mar 31 02:46:15 PM PDT 24
Peak memory 240956 kb
Host smart-efd31920-0262-4e40-9fd4-bb1996116402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249289217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2249289217
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1611703753
Short name T342
Test name
Test status
Simulation time 344025857 ps
CPU time 5.59 seconds
Started Mar 31 02:46:04 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 216636 kb
Host smart-9cb8cde0-e144-403f-aa42-cfe5c97423dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611703753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1611703753
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3821083557
Short name T265
Test name
Test status
Simulation time 8716038072 ps
CPU time 19.3 seconds
Started Mar 31 02:46:07 PM PDT 24
Finished Mar 31 02:46:27 PM PDT 24
Peak memory 218564 kb
Host smart-e873f3a5-8762-4f82-8c46-997da13eca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821083557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3821083557
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4151435122
Short name T461
Test name
Test status
Simulation time 119430773 ps
CPU time 4.96 seconds
Started Mar 31 02:46:04 PM PDT 24
Finished Mar 31 02:46:09 PM PDT 24
Peak memory 222748 kb
Host smart-94357b08-f408-4d5c-a037-96936b68ff3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4151435122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4151435122
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.758941965
Short name T399
Test name
Test status
Simulation time 3394917716 ps
CPU time 20.68 seconds
Started Mar 31 02:46:06 PM PDT 24
Finished Mar 31 02:46:27 PM PDT 24
Peak memory 216476 kb
Host smart-eb08c544-8717-4a02-8d5a-ee36ff9204c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758941965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.758941965
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.45558245
Short name T592
Test name
Test status
Simulation time 1943604304 ps
CPU time 4.96 seconds
Started Mar 31 02:46:06 PM PDT 24
Finished Mar 31 02:46:11 PM PDT 24
Peak memory 216308 kb
Host smart-d179e168-8ba6-4301-87c4-ddb80c712378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45558245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.45558245
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.661891248
Short name T467
Test name
Test status
Simulation time 308876364 ps
CPU time 2.08 seconds
Started Mar 31 02:46:08 PM PDT 24
Finished Mar 31 02:46:10 PM PDT 24
Peak memory 216600 kb
Host smart-23f093b4-8755-4984-a7ed-b98312e19a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661891248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.661891248
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2327183310
Short name T121
Test name
Test status
Simulation time 105942154 ps
CPU time 0.77 seconds
Started Mar 31 02:46:05 PM PDT 24
Finished Mar 31 02:46:06 PM PDT 24
Peak memory 205680 kb
Host smart-b31978d5-93ed-4349-b602-235b634ee628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327183310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2327183310
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1976415902
Short name T642
Test name
Test status
Simulation time 13314559 ps
CPU time 0.75 seconds
Started Mar 31 02:46:18 PM PDT 24
Finished Mar 31 02:46:19 PM PDT 24
Peak memory 205300 kb
Host smart-d50695ca-7877-4295-b6ef-03387b0958d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976415902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1976415902
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1330331573
Short name T234
Test name
Test status
Simulation time 332473332 ps
CPU time 5.11 seconds
Started Mar 31 02:46:10 PM PDT 24
Finished Mar 31 02:46:16 PM PDT 24
Peak memory 219004 kb
Host smart-01b4e283-ab61-4554-8977-e5e6ebc087ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330331573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1330331573
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.382643752
Short name T656
Test name
Test status
Simulation time 64404191 ps
CPU time 0.76 seconds
Started Mar 31 02:46:10 PM PDT 24
Finished Mar 31 02:46:11 PM PDT 24
Peak memory 206340 kb
Host smart-0777ca11-c6f7-4506-990b-e4075b9ca446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382643752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.382643752
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.675003584
Short name T313
Test name
Test status
Simulation time 250746733 ps
CPU time 8.77 seconds
Started Mar 31 02:46:15 PM PDT 24
Finished Mar 31 02:46:23 PM PDT 24
Peak memory 232776 kb
Host smart-c415a2dd-76ff-4dd7-a367-efb5cf0b3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675003584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.675003584
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2798850535
Short name T354
Test name
Test status
Simulation time 533286316 ps
CPU time 5.31 seconds
Started Mar 31 02:46:12 PM PDT 24
Finished Mar 31 02:46:17 PM PDT 24
Peak memory 234208 kb
Host smart-ffb1ae8e-4a70-473a-94ed-2143e6959d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798850535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2798850535
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2455347215
Short name T168
Test name
Test status
Simulation time 117665118 ps
CPU time 3.8 seconds
Started Mar 31 02:46:15 PM PDT 24
Finished Mar 31 02:46:19 PM PDT 24
Peak memory 220620 kb
Host smart-0e4d0cb3-16b6-4a65-8282-526852956a87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2455347215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2455347215
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4014935748
Short name T670
Test name
Test status
Simulation time 3465366399 ps
CPU time 28.12 seconds
Started Mar 31 02:46:14 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 220660 kb
Host smart-d4acb06f-6913-4ef8-9860-209b305c7dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014935748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4014935748
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2115247985
Short name T682
Test name
Test status
Simulation time 727385239 ps
CPU time 4.75 seconds
Started Mar 31 02:46:10 PM PDT 24
Finished Mar 31 02:46:15 PM PDT 24
Peak memory 216276 kb
Host smart-389aff58-d8e5-4c7c-be47-859a29be4b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115247985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2115247985
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3946108649
Short name T573
Test name
Test status
Simulation time 76688294 ps
CPU time 1.24 seconds
Started Mar 31 02:46:15 PM PDT 24
Finished Mar 31 02:46:16 PM PDT 24
Peak memory 207960 kb
Host smart-0f8de422-cfac-4c9a-8288-913354f97a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946108649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3946108649
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2465811721
Short name T553
Test name
Test status
Simulation time 267234957 ps
CPU time 1 seconds
Started Mar 31 02:46:11 PM PDT 24
Finished Mar 31 02:46:12 PM PDT 24
Peak memory 206752 kb
Host smart-4bd689ea-f058-4a08-affb-3c7b87d33a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465811721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2465811721
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3299192778
Short name T26
Test name
Test status
Simulation time 1972792101 ps
CPU time 10.03 seconds
Started Mar 31 02:46:11 PM PDT 24
Finished Mar 31 02:46:21 PM PDT 24
Peak memory 234720 kb
Host smart-bf64af50-a088-41a4-af58-0b39a44d90f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299192778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3299192778
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.402626221
Short name T477
Test name
Test status
Simulation time 34497647 ps
CPU time 0.64 seconds
Started Mar 31 02:46:22 PM PDT 24
Finished Mar 31 02:46:22 PM PDT 24
Peak memory 204772 kb
Host smart-c0f71690-be90-459e-a166-1d26ed8942f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402626221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.402626221
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1151376924
Short name T444
Test name
Test status
Simulation time 23771505 ps
CPU time 0.74 seconds
Started Mar 31 02:46:16 PM PDT 24
Finished Mar 31 02:46:17 PM PDT 24
Peak memory 205476 kb
Host smart-95d6a84d-d6d7-4a28-ad26-b031b07d665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151376924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1151376924
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.91551953
Short name T99
Test name
Test status
Simulation time 2793319634 ps
CPU time 21.23 seconds
Started Mar 31 02:46:17 PM PDT 24
Finished Mar 31 02:46:38 PM PDT 24
Peak memory 238504 kb
Host smart-8926d83b-2be9-4ddb-943c-3f714be2a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91551953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.91551953
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2312862787
Short name T253
Test name
Test status
Simulation time 353221266 ps
CPU time 3.52 seconds
Started Mar 31 02:46:18 PM PDT 24
Finished Mar 31 02:46:22 PM PDT 24
Peak memory 216836 kb
Host smart-d712235f-1f05-44b8-9c8e-c47caf21cdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312862787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2312862787
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1629162533
Short name T257
Test name
Test status
Simulation time 5924384643 ps
CPU time 18.84 seconds
Started Mar 31 02:46:19 PM PDT 24
Finished Mar 31 02:46:37 PM PDT 24
Peak memory 234316 kb
Host smart-c026a77e-29ef-409c-8c2f-644c910dade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629162533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1629162533
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2594890658
Short name T333
Test name
Test status
Simulation time 15967247091 ps
CPU time 16.57 seconds
Started Mar 31 02:46:17 PM PDT 24
Finished Mar 31 02:46:34 PM PDT 24
Peak memory 222596 kb
Host smart-420e354b-7fb6-4fa3-8726-e7fdf7a83ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594890658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2594890658
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.905686560
Short name T11
Test name
Test status
Simulation time 2219432915 ps
CPU time 6.81 seconds
Started Mar 31 02:46:15 PM PDT 24
Finished Mar 31 02:46:22 PM PDT 24
Peak memory 222840 kb
Host smart-230f9312-bc6f-48d0-b3fd-505d66b8f8ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905686560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.905686560
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1018484196
Short name T177
Test name
Test status
Simulation time 248357807 ps
CPU time 1.18 seconds
Started Mar 31 02:46:26 PM PDT 24
Finished Mar 31 02:46:28 PM PDT 24
Peak memory 206868 kb
Host smart-8538b865-d7e9-4bee-800e-9b4dcc49481b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018484196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1018484196
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1653109337
Short name T639
Test name
Test status
Simulation time 316998812 ps
CPU time 2.78 seconds
Started Mar 31 02:46:16 PM PDT 24
Finished Mar 31 02:46:19 PM PDT 24
Peak memory 216308 kb
Host smart-c7a925d9-4b28-4aef-891d-2b808a8898a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653109337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1653109337
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3065673343
Short name T733
Test name
Test status
Simulation time 327572701 ps
CPU time 4.15 seconds
Started Mar 31 02:46:17 PM PDT 24
Finished Mar 31 02:46:22 PM PDT 24
Peak memory 216392 kb
Host smart-8f84e42f-bd45-4254-9397-23fc4f676a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065673343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3065673343
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1732024792
Short name T632
Test name
Test status
Simulation time 156346372 ps
CPU time 1.01 seconds
Started Mar 31 02:46:16 PM PDT 24
Finished Mar 31 02:46:17 PM PDT 24
Peak memory 206728 kb
Host smart-7703b650-45ca-48ce-bbc7-3dbad86ba8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732024792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1732024792
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1838235380
Short name T582
Test name
Test status
Simulation time 50511192 ps
CPU time 0.72 seconds
Started Mar 31 02:46:23 PM PDT 24
Finished Mar 31 02:46:24 PM PDT 24
Peak memory 204760 kb
Host smart-3ffa654f-0bd5-4398-ad35-abeb8901cb82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838235380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1838235380
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3445681701
Short name T508
Test name
Test status
Simulation time 17572145 ps
CPU time 0.84 seconds
Started Mar 31 02:46:27 PM PDT 24
Finished Mar 31 02:46:28 PM PDT 24
Peak memory 205420 kb
Host smart-02946c01-a5a1-4cae-bb77-4eaf1e88cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445681701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3445681701
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3044820229
Short name T123
Test name
Test status
Simulation time 120845838 ps
CPU time 3.88 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:32 PM PDT 24
Peak memory 223828 kb
Host smart-a1a42434-b01c-405a-891a-8ec75573e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044820229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3044820229
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.774556768
Short name T339
Test name
Test status
Simulation time 2856076599 ps
CPU time 5.22 seconds
Started Mar 31 02:46:30 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 223048 kb
Host smart-24604632-4e22-40c7-9021-e6a58446bf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774556768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.774556768
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.879886876
Short name T554
Test name
Test status
Simulation time 15592816132 ps
CPU time 12.96 seconds
Started Mar 31 02:46:22 PM PDT 24
Finished Mar 31 02:46:35 PM PDT 24
Peak memory 222816 kb
Host smart-efb259e6-1044-4cd6-8802-0ab931e5e37e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=879886876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.879886876
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2082775417
Short name T406
Test name
Test status
Simulation time 3653422739 ps
CPU time 6.03 seconds
Started Mar 31 02:46:30 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 216400 kb
Host smart-1306a26f-de8e-4f98-8393-f64f416b80e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082775417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2082775417
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.934131489
Short name T748
Test name
Test status
Simulation time 1755264759 ps
CPU time 4.04 seconds
Started Mar 31 02:46:22 PM PDT 24
Finished Mar 31 02:46:26 PM PDT 24
Peak memory 216392 kb
Host smart-7f37d233-2be9-4487-b573-69750167e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934131489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.934131489
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.292305099
Short name T509
Test name
Test status
Simulation time 55298560 ps
CPU time 0.74 seconds
Started Mar 31 02:46:30 PM PDT 24
Finished Mar 31 02:46:31 PM PDT 24
Peak memory 205752 kb
Host smart-0edbd80c-6183-47d7-bae5-c4a21aaabb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292305099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.292305099
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1554051755
Short name T611
Test name
Test status
Simulation time 136173476 ps
CPU time 1.13 seconds
Started Mar 31 02:46:23 PM PDT 24
Finished Mar 31 02:46:24 PM PDT 24
Peak memory 206712 kb
Host smart-6b07ac50-da2c-4d60-bb65-ead331532344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554051755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1554051755
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.440877538
Short name T82
Test name
Test status
Simulation time 9238361057 ps
CPU time 23.81 seconds
Started Mar 31 02:46:23 PM PDT 24
Finished Mar 31 02:46:47 PM PDT 24
Peak memory 222588 kb
Host smart-deb0ff48-6957-46ff-9232-b0305ad525c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440877538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.440877538
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3230839891
Short name T534
Test name
Test status
Simulation time 61894352 ps
CPU time 0.74 seconds
Started Mar 31 02:46:33 PM PDT 24
Finished Mar 31 02:46:34 PM PDT 24
Peak memory 204812 kb
Host smart-796d012a-0689-4500-89c0-9c83400f4adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230839891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3230839891
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.344091295
Short name T732
Test name
Test status
Simulation time 19346447 ps
CPU time 0.8 seconds
Started Mar 31 02:46:21 PM PDT 24
Finished Mar 31 02:46:22 PM PDT 24
Peak memory 206516 kb
Host smart-9d437055-ebac-4c2b-a3a3-030dc72c4097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344091295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.344091295
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2131263054
Short name T316
Test name
Test status
Simulation time 3776638773 ps
CPU time 55.14 seconds
Started Mar 31 02:46:26 PM PDT 24
Finished Mar 31 02:47:21 PM PDT 24
Peak memory 224604 kb
Host smart-ccc9aeb8-59cd-443d-8bb3-333741f04d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131263054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2131263054
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3731009071
Short name T256
Test name
Test status
Simulation time 930606612 ps
CPU time 4.63 seconds
Started Mar 31 02:46:26 PM PDT 24
Finished Mar 31 02:46:31 PM PDT 24
Peak memory 217000 kb
Host smart-4723f4e3-f669-4c22-8183-1587766f2dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731009071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3731009071
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.968848394
Short name T247
Test name
Test status
Simulation time 1993075026 ps
CPU time 5.06 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:33 PM PDT 24
Peak memory 216816 kb
Host smart-d3b4fb02-e4ac-4309-be45-61f6639cdfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968848394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.968848394
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1492517275
Short name T674
Test name
Test status
Simulation time 521506307 ps
CPU time 8.97 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:38 PM PDT 24
Peak memory 221392 kb
Host smart-8be9b182-d507-4c89-b5c2-5a164e31ea2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1492517275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1492517275
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2476987567
Short name T390
Test name
Test status
Simulation time 101688739365 ps
CPU time 60.79 seconds
Started Mar 31 02:46:24 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 216420 kb
Host smart-49897247-7f8e-48c6-8f24-b06a3b143a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476987567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2476987567
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.870998061
Short name T418
Test name
Test status
Simulation time 3551872951 ps
CPU time 4.86 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:33 PM PDT 24
Peak memory 216372 kb
Host smart-fcd6fafc-c0b7-47b7-ab92-a0f7b8fdca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870998061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.870998061
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3925979978
Short name T753
Test name
Test status
Simulation time 339742842 ps
CPU time 1.54 seconds
Started Mar 31 02:46:27 PM PDT 24
Finished Mar 31 02:46:29 PM PDT 24
Peak memory 216316 kb
Host smart-24d7727b-2b9e-4d03-ab5d-d86af82ccf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925979978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3925979978
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1028009064
Short name T638
Test name
Test status
Simulation time 95001905 ps
CPU time 0.92 seconds
Started Mar 31 02:46:24 PM PDT 24
Finished Mar 31 02:46:25 PM PDT 24
Peak memory 205720 kb
Host smart-d36a49ac-b9c9-452e-85d5-2126b87821ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028009064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1028009064
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3165709073
Short name T747
Test name
Test status
Simulation time 26105823 ps
CPU time 0.76 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:35 PM PDT 24
Peak memory 205380 kb
Host smart-71562f2f-db76-4e8d-b7e9-3054ecb98586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165709073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3165709073
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1626374361
Short name T492
Test name
Test status
Simulation time 845028994 ps
CPU time 3 seconds
Started Mar 31 02:46:29 PM PDT 24
Finished Mar 31 02:46:32 PM PDT 24
Peak memory 218648 kb
Host smart-cf751ced-e99b-43d7-b5d1-b7f2beecef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626374361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1626374361
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3652678585
Short name T704
Test name
Test status
Simulation time 17446546 ps
CPU time 0.78 seconds
Started Mar 31 02:46:31 PM PDT 24
Finished Mar 31 02:46:32 PM PDT 24
Peak memory 206480 kb
Host smart-86321094-690c-4a97-8756-082971bf89cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652678585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3652678585
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.230568359
Short name T518
Test name
Test status
Simulation time 16541181372 ps
CPU time 48.8 seconds
Started Mar 31 02:46:27 PM PDT 24
Finished Mar 31 02:47:16 PM PDT 24
Peak memory 232860 kb
Host smart-750656a7-cb13-4a5c-a94f-29742e9c1d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230568359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.230568359
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.164110669
Short name T248
Test name
Test status
Simulation time 435395320 ps
CPU time 3.49 seconds
Started Mar 31 02:46:32 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 222988 kb
Host smart-9bc9bcac-d882-4e6f-8e09-b206b93ffa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164110669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.164110669
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2979772002
Short name T45
Test name
Test status
Simulation time 9963420441 ps
CPU time 47.6 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:47:16 PM PDT 24
Peak memory 217056 kb
Host smart-91375366-c4b9-402e-a9a0-3b0aee11e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979772002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2979772002
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2552512017
Short name T90
Test name
Test status
Simulation time 141418789 ps
CPU time 2.77 seconds
Started Mar 31 02:46:32 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 222672 kb
Host smart-50d08fb9-b187-4aa7-a2e4-58c1cba5db0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552512017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2552512017
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1993511090
Short name T58
Test name
Test status
Simulation time 1314949875 ps
CPU time 12.11 seconds
Started Mar 31 02:46:30 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 222060 kb
Host smart-9b8bf638-cb97-45e2-bb5b-b44bf1cfe97f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1993511090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1993511090
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1350195697
Short name T68
Test name
Test status
Simulation time 21029256798 ps
CPU time 51.47 seconds
Started Mar 31 02:46:29 PM PDT 24
Finished Mar 31 02:47:21 PM PDT 24
Peak memory 216412 kb
Host smart-dac6a477-9fb1-47b5-b70c-185a4a56e28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350195697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1350195697
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3121775574
Short name T709
Test name
Test status
Simulation time 38389326478 ps
CPU time 23.54 seconds
Started Mar 31 02:46:27 PM PDT 24
Finished Mar 31 02:46:50 PM PDT 24
Peak memory 216312 kb
Host smart-4431846c-cf1f-4340-ae5e-091ed17a8ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121775574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3121775574
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.64343456
Short name T647
Test name
Test status
Simulation time 58512130 ps
CPU time 3.37 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:31 PM PDT 24
Peak memory 216436 kb
Host smart-9c34e69b-7c8a-4add-95dd-314f537ce0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64343456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.64343456
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3993552796
Short name T675
Test name
Test status
Simulation time 514898119 ps
CPU time 0.97 seconds
Started Mar 31 02:46:28 PM PDT 24
Finished Mar 31 02:46:29 PM PDT 24
Peak memory 206780 kb
Host smart-5dc33970-2fcf-4d58-89cf-e13fd1875ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993552796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3993552796
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1524229511
Short name T434
Test name
Test status
Simulation time 38060112 ps
CPU time 0.7 seconds
Started Mar 31 02:46:36 PM PDT 24
Finished Mar 31 02:46:37 PM PDT 24
Peak memory 204712 kb
Host smart-57bd9e26-772e-4373-9c4e-cfc81b1de314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524229511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1524229511
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.280028290
Short name T14
Test name
Test status
Simulation time 98372145 ps
CPU time 0.83 seconds
Started Mar 31 02:46:30 PM PDT 24
Finished Mar 31 02:46:31 PM PDT 24
Peak memory 206504 kb
Host smart-c363fbce-5aa2-49bb-8314-3436437228a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280028290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.280028290
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.742524015
Short name T321
Test name
Test status
Simulation time 3050698427 ps
CPU time 32.37 seconds
Started Mar 31 02:46:35 PM PDT 24
Finished Mar 31 02:47:08 PM PDT 24
Peak memory 232836 kb
Host smart-eeb97560-b28a-4845-a341-eeb9751cd6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742524015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.742524015
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2825942502
Short name T128
Test name
Test status
Simulation time 1908066206 ps
CPU time 7.79 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 224316 kb
Host smart-d845a100-ba88-42a1-8858-7d2a209f7b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825942502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2825942502
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1590932664
Short name T424
Test name
Test status
Simulation time 12535695139 ps
CPU time 33.56 seconds
Started Mar 31 02:46:33 PM PDT 24
Finished Mar 31 02:47:07 PM PDT 24
Peak memory 235140 kb
Host smart-9309b6fe-fdca-487c-a6a5-015522342f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590932664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1590932664
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1854812437
Short name T365
Test name
Test status
Simulation time 259043568 ps
CPU time 2.57 seconds
Started Mar 31 02:46:40 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 216792 kb
Host smart-03c5b4ad-f186-495d-b9c5-b9be56abd970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854812437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1854812437
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.4268171369
Short name T267
Test name
Test status
Simulation time 33115640 ps
CPU time 2.14 seconds
Started Mar 31 02:46:37 PM PDT 24
Finished Mar 31 02:46:40 PM PDT 24
Peak memory 218512 kb
Host smart-ea1b1d29-f78a-4cb0-80f1-72362926e3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268171369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4268171369
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1220424870
Short name T490
Test name
Test status
Simulation time 1355478498 ps
CPU time 9.49 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:44 PM PDT 24
Peak memory 218724 kb
Host smart-d0c278eb-837b-47d2-83dd-bed7166c3b2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1220424870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1220424870
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.910635517
Short name T583
Test name
Test status
Simulation time 110213229 ps
CPU time 1.02 seconds
Started Mar 31 02:46:40 PM PDT 24
Finished Mar 31 02:46:41 PM PDT 24
Peak memory 206804 kb
Host smart-7c8e07c8-dabe-4939-8050-0611a85fa919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910635517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.910635517
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2251947293
Short name T391
Test name
Test status
Simulation time 9416096216 ps
CPU time 14.17 seconds
Started Mar 31 02:46:31 PM PDT 24
Finished Mar 31 02:46:45 PM PDT 24
Peak memory 216404 kb
Host smart-61924910-b271-4b02-aa9c-4979ca290858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251947293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2251947293
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1998817824
Short name T479
Test name
Test status
Simulation time 14084545836 ps
CPU time 12.46 seconds
Started Mar 31 02:46:31 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 216380 kb
Host smart-9d1ece87-2073-41a3-b76d-6007f22bcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998817824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1998817824
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3723752556
Short name T601
Test name
Test status
Simulation time 1040635849 ps
CPU time 3.49 seconds
Started Mar 31 02:46:39 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 216408 kb
Host smart-b12bcb69-b01f-40b4-b8bc-b4c5f9a4d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723752556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3723752556
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3878047207
Short name T489
Test name
Test status
Simulation time 71550736 ps
CPU time 0.9 seconds
Started Mar 31 02:46:35 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 205744 kb
Host smart-f205eec1-aedc-4532-85a3-02522dd4bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878047207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3878047207
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1891939369
Short name T233
Test name
Test status
Simulation time 360751659 ps
CPU time 4.24 seconds
Started Mar 31 02:46:37 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 216352 kb
Host smart-3d28a356-2576-49c9-922a-4ec9edebc767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891939369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1891939369
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.617618557
Short name T488
Test name
Test status
Simulation time 15472376 ps
CPU time 0.69 seconds
Started Mar 31 02:46:40 PM PDT 24
Finished Mar 31 02:46:41 PM PDT 24
Peak memory 205332 kb
Host smart-481d420b-bb46-4ca5-9873-e99cd494ac97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617618557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.617618557
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1214783086
Short name T17
Test name
Test status
Simulation time 13455838 ps
CPU time 0.8 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 206448 kb
Host smart-226b0dfd-149b-4654-9b0c-d833f26d1c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214783086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1214783086
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1051914509
Short name T89
Test name
Test status
Simulation time 2316843900 ps
CPU time 46.78 seconds
Started Mar 31 02:46:39 PM PDT 24
Finished Mar 31 02:47:26 PM PDT 24
Peak memory 232864 kb
Host smart-f192183c-1503-472d-968a-ac33d0701bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051914509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1051914509
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2413748622
Short name T252
Test name
Test status
Simulation time 4323941944 ps
CPU time 7.07 seconds
Started Mar 31 02:46:36 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 218596 kb
Host smart-94f50685-7208-4338-a8f6-bd9b3b9237ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413748622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2413748622
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1377472969
Short name T43
Test name
Test status
Simulation time 28249369122 ps
CPU time 68.93 seconds
Started Mar 31 02:46:33 PM PDT 24
Finished Mar 31 02:47:42 PM PDT 24
Peak memory 229620 kb
Host smart-c6a8181c-d48a-431f-ae74-35daa8997350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377472969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1377472969
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2338118503
Short name T218
Test name
Test status
Simulation time 2686646263 ps
CPU time 8.45 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 234028 kb
Host smart-e89951e5-d0d5-4be3-a669-44261112ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338118503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2338118503
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.790122277
Short name T373
Test name
Test status
Simulation time 42020576703 ps
CPU time 25.86 seconds
Started Mar 31 02:46:39 PM PDT 24
Finished Mar 31 02:47:05 PM PDT 24
Peak memory 230036 kb
Host smart-843fc009-58bb-4f58-8e58-9ae465dda71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790122277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.790122277
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.715758051
Short name T443
Test name
Test status
Simulation time 1575449451 ps
CPU time 9.13 seconds
Started Mar 31 02:46:41 PM PDT 24
Finished Mar 31 02:46:51 PM PDT 24
Peak memory 219192 kb
Host smart-79e90025-11c5-4a64-b3bd-5573e119197d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715758051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.715758051
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3507369477
Short name T561
Test name
Test status
Simulation time 71636882 ps
CPU time 1.26 seconds
Started Mar 31 02:46:42 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 206876 kb
Host smart-ffcbd3fa-2bb0-4339-8313-2cada10d2999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507369477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3507369477
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.353713559
Short name T405
Test name
Test status
Simulation time 6186306902 ps
CPU time 33.42 seconds
Started Mar 31 02:46:33 PM PDT 24
Finished Mar 31 02:47:06 PM PDT 24
Peak memory 216376 kb
Host smart-53f0a4ef-a2f2-4091-baa6-ef528a444f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353713559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.353713559
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2999351335
Short name T523
Test name
Test status
Simulation time 4155445561 ps
CPU time 6.65 seconds
Started Mar 31 02:46:37 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 216352 kb
Host smart-38052e02-88b5-4d1f-ae5e-6889d89a444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999351335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2999351335
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1914218963
Short name T735
Test name
Test status
Simulation time 250138042 ps
CPU time 1.69 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:36 PM PDT 24
Peak memory 216380 kb
Host smart-dee87a32-0be4-4671-a311-a6bcf03cfecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914218963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1914218963
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1612350118
Short name T515
Test name
Test status
Simulation time 38629381 ps
CPU time 0.84 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:35 PM PDT 24
Peak memory 205700 kb
Host smart-e8d75d7a-fdaf-48eb-8983-25bd261e3bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612350118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1612350118
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1230045117
Short name T266
Test name
Test status
Simulation time 11784628943 ps
CPU time 10.4 seconds
Started Mar 31 02:46:34 PM PDT 24
Finished Mar 31 02:46:45 PM PDT 24
Peak memory 219492 kb
Host smart-3dcc882b-9c02-47fe-99f9-25484ab992c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230045117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1230045117
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1484612431
Short name T663
Test name
Test status
Simulation time 21378803 ps
CPU time 0.73 seconds
Started Mar 31 02:46:47 PM PDT 24
Finished Mar 31 02:46:47 PM PDT 24
Peak memory 204800 kb
Host smart-23b538c8-69c9-4761-a793-9113ed94f79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484612431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1484612431
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3688810083
Short name T590
Test name
Test status
Simulation time 766970947 ps
CPU time 2.89 seconds
Started Mar 31 02:46:42 PM PDT 24
Finished Mar 31 02:46:45 PM PDT 24
Peak memory 223136 kb
Host smart-e5edd17c-fcc9-40b9-a0e4-ed1b673df543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688810083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3688810083
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2196656593
Short name T429
Test name
Test status
Simulation time 137128331 ps
CPU time 0.76 seconds
Started Mar 31 02:46:41 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 206508 kb
Host smart-0b51c774-b522-4be4-a68d-11fc198b6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196656593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2196656593
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1889042018
Short name T107
Test name
Test status
Simulation time 874902993 ps
CPU time 14.88 seconds
Started Mar 31 02:46:42 PM PDT 24
Finished Mar 31 02:46:57 PM PDT 24
Peak memory 219200 kb
Host smart-b5b62bdc-b147-4bde-9b42-909c32b7cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889042018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1889042018
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3837342306
Short name T556
Test name
Test status
Simulation time 3743392133 ps
CPU time 19.99 seconds
Started Mar 31 02:46:47 PM PDT 24
Finished Mar 31 02:47:08 PM PDT 24
Peak memory 221428 kb
Host smart-05a0655a-5cb8-459a-b5ed-f88327976412
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3837342306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3837342306
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3067388940
Short name T672
Test name
Test status
Simulation time 45450109705 ps
CPU time 58.39 seconds
Started Mar 31 02:46:39 PM PDT 24
Finished Mar 31 02:47:38 PM PDT 24
Peak memory 216476 kb
Host smart-c680315e-4de7-4a02-a82a-db86a8292960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067388940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3067388940
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2216855863
Short name T684
Test name
Test status
Simulation time 10046661137 ps
CPU time 7.02 seconds
Started Mar 31 02:46:41 PM PDT 24
Finished Mar 31 02:46:49 PM PDT 24
Peak memory 216432 kb
Host smart-5bdc2e4b-0b3a-4ad4-9632-e12ff6ce97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216855863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2216855863
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3458787968
Short name T401
Test name
Test status
Simulation time 438584686 ps
CPU time 1.71 seconds
Started Mar 31 02:46:41 PM PDT 24
Finished Mar 31 02:46:43 PM PDT 24
Peak memory 216384 kb
Host smart-cdbc66ab-e5f8-4b6b-805a-46ef00cd428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458787968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3458787968
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2007651149
Short name T692
Test name
Test status
Simulation time 69760539 ps
CPU time 0.87 seconds
Started Mar 31 02:46:40 PM PDT 24
Finished Mar 31 02:46:42 PM PDT 24
Peak memory 206772 kb
Host smart-e5bdaef7-d4a2-465e-8df3-36e50e8d5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007651149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2007651149
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1941612859
Short name T666
Test name
Test status
Simulation time 46543487 ps
CPU time 0.75 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:46:57 PM PDT 24
Peak memory 204772 kb
Host smart-33acbf7b-711b-4f97-9f1c-f3092beaa295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941612859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1941612859
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.516394046
Short name T432
Test name
Test status
Simulation time 52253268 ps
CPU time 0.8 seconds
Started Mar 31 02:46:48 PM PDT 24
Finished Mar 31 02:46:49 PM PDT 24
Peak memory 206372 kb
Host smart-1abc4dcf-b999-4939-a9d9-0b0cff5882fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516394046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.516394046
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1945032273
Short name T653
Test name
Test status
Simulation time 847580909 ps
CPU time 5.55 seconds
Started Mar 31 02:46:49 PM PDT 24
Finished Mar 31 02:46:55 PM PDT 24
Peak memory 232832 kb
Host smart-e3d831f4-235b-482b-8051-fbac2de67f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945032273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1945032273
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2867693721
Short name T340
Test name
Test status
Simulation time 99961025132 ps
CPU time 86.3 seconds
Started Mar 31 02:46:47 PM PDT 24
Finished Mar 31 02:48:13 PM PDT 24
Peak memory 239000 kb
Host smart-3e5faaa6-7bef-4aa2-9d82-7bde353e9535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867693721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2867693721
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3094245443
Short name T767
Test name
Test status
Simulation time 7333927825 ps
CPU time 10.42 seconds
Started Mar 31 02:46:48 PM PDT 24
Finished Mar 31 02:46:58 PM PDT 24
Peak memory 220472 kb
Host smart-1fe1efc9-dbc4-42b8-af4a-d7afe35b8dd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3094245443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3094245443
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2747910035
Short name T696
Test name
Test status
Simulation time 24354180582 ps
CPU time 16.15 seconds
Started Mar 31 02:46:52 PM PDT 24
Finished Mar 31 02:47:08 PM PDT 24
Peak memory 216208 kb
Host smart-cdb72748-1503-4c25-a050-5b9210a44c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747910035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2747910035
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.650909585
Short name T617
Test name
Test status
Simulation time 1033084159 ps
CPU time 8.96 seconds
Started Mar 31 02:46:49 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 216468 kb
Host smart-9ad73fea-f596-4b14-af91-71f042dfa2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650909585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.650909585
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.686672851
Short name T451
Test name
Test status
Simulation time 20634374 ps
CPU time 0.76 seconds
Started Mar 31 02:46:49 PM PDT 24
Finished Mar 31 02:46:50 PM PDT 24
Peak memory 205724 kb
Host smart-fed2273e-0a5a-4590-9d11-5362e154c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686672851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.686672851
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2565623400
Short name T278
Test name
Test status
Simulation time 29226775560 ps
CPU time 23.37 seconds
Started Mar 31 02:46:48 PM PDT 24
Finished Mar 31 02:47:12 PM PDT 24
Peak memory 223888 kb
Host smart-65c708e4-b46d-4e76-9bd3-cb9a5273f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565623400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2565623400
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2831630694
Short name T574
Test name
Test status
Simulation time 85136074 ps
CPU time 0.71 seconds
Started Mar 31 02:44:07 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 204788 kb
Host smart-d316ae08-b145-4d1f-bf51-fa49db5fc9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831630694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
831630694
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.174249388
Short name T103
Test name
Test status
Simulation time 130904557 ps
CPU time 2.7 seconds
Started Mar 31 02:44:08 PM PDT 24
Finished Mar 31 02:44:12 PM PDT 24
Peak memory 216996 kb
Host smart-5674a284-beb4-48d8-9db3-3004d1369139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174249388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.174249388
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.847951261
Short name T608
Test name
Test status
Simulation time 64153364 ps
CPU time 0.79 seconds
Started Mar 31 02:44:01 PM PDT 24
Finished Mar 31 02:44:02 PM PDT 24
Peak memory 206792 kb
Host smart-8b1546fc-6e92-4414-97c4-dcb437b16f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847951261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.847951261
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.386209253
Short name T113
Test name
Test status
Simulation time 1379644052 ps
CPU time 7.72 seconds
Started Mar 31 02:43:59 PM PDT 24
Finished Mar 31 02:44:07 PM PDT 24
Peak memory 224080 kb
Host smart-680e1e84-8ac1-4ba9-a8bd-61d92191883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386209253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.386209253
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2644429041
Short name T199
Test name
Test status
Simulation time 1163836016 ps
CPU time 6.55 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:13 PM PDT 24
Peak memory 232832 kb
Host smart-0e1ba347-4ccd-4d20-9c68-bc06349b4807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644429041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2644429041
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1801696399
Short name T464
Test name
Test status
Simulation time 92832986 ps
CPU time 1.02 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:01 PM PDT 24
Peak memory 218084 kb
Host smart-7835aadb-ada2-49c7-b61d-bc38a18d5e7d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801696399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1801696399
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1527638832
Short name T685
Test name
Test status
Simulation time 17596365 ps
CPU time 0.77 seconds
Started Mar 31 02:44:01 PM PDT 24
Finished Mar 31 02:44:02 PM PDT 24
Peak memory 216272 kb
Host smart-92adef21-ce4e-4fb7-a906-4d0a14f5a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527638832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1527638832
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1063473062
Short name T699
Test name
Test status
Simulation time 1701542558 ps
CPU time 14.68 seconds
Started Mar 31 02:44:05 PM PDT 24
Finished Mar 31 02:44:21 PM PDT 24
Peak memory 222596 kb
Host smart-318ec8d4-ebe4-49d7-97e6-dbba1df7750b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1063473062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1063473062
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1571334934
Short name T47
Test name
Test status
Simulation time 332704246 ps
CPU time 1.21 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 235580 kb
Host smart-0fe80187-9119-4188-a7cf-d08faa94a8d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571334934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1571334934
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1588038591
Short name T514
Test name
Test status
Simulation time 43652613544 ps
CPU time 16.44 seconds
Started Mar 31 02:44:01 PM PDT 24
Finished Mar 31 02:44:18 PM PDT 24
Peak memory 216420 kb
Host smart-edb8778c-45f5-4f97-966d-2d4b5d396df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588038591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1588038591
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3221064086
Short name T92
Test name
Test status
Simulation time 749698484 ps
CPU time 4.94 seconds
Started Mar 31 02:44:00 PM PDT 24
Finished Mar 31 02:44:06 PM PDT 24
Peak memory 216612 kb
Host smart-329ca223-df26-4de2-80aa-ec50bc31d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221064086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3221064086
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1111941038
Short name T629
Test name
Test status
Simulation time 70406818 ps
CPU time 0.92 seconds
Started Mar 31 02:43:59 PM PDT 24
Finished Mar 31 02:44:00 PM PDT 24
Peak memory 205728 kb
Host smart-7f90588b-5e90-4578-806a-9a1da919a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111941038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1111941038
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2856873680
Short name T708
Test name
Test status
Simulation time 39467537 ps
CPU time 0.73 seconds
Started Mar 31 02:46:59 PM PDT 24
Finished Mar 31 02:47:00 PM PDT 24
Peak memory 205316 kb
Host smart-b4027511-1b69-4bbb-b22e-3bd479bcb358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856873680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2856873680
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3208048597
Short name T453
Test name
Test status
Simulation time 19650155 ps
CPU time 0.77 seconds
Started Mar 31 02:46:54 PM PDT 24
Finished Mar 31 02:46:54 PM PDT 24
Peak memory 206492 kb
Host smart-14f92ea0-a099-4b0a-80f5-36753bc894f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208048597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3208048597
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.397034492
Short name T367
Test name
Test status
Simulation time 1001972742 ps
CPU time 17.25 seconds
Started Mar 31 02:46:53 PM PDT 24
Finished Mar 31 02:47:10 PM PDT 24
Peak memory 232844 kb
Host smart-9d28283f-00d4-474c-8ed5-6bf758dceb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397034492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.397034492
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1405663649
Short name T604
Test name
Test status
Simulation time 11431651320 ps
CPU time 35.67 seconds
Started Mar 31 02:46:55 PM PDT 24
Finished Mar 31 02:47:31 PM PDT 24
Peak memory 224112 kb
Host smart-6f5f1325-a53b-4a33-bcd1-b1e0b7767b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405663649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1405663649
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.681242610
Short name T273
Test name
Test status
Simulation time 460577447 ps
CPU time 5.05 seconds
Started Mar 31 02:46:54 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 222916 kb
Host smart-956de138-458c-4564-97ea-75d916e84284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681242610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.681242610
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2366162351
Short name T559
Test name
Test status
Simulation time 213740755 ps
CPU time 5.31 seconds
Started Mar 31 02:46:52 PM PDT 24
Finished Mar 31 02:46:58 PM PDT 24
Peak memory 222824 kb
Host smart-81c4b5bf-d72d-43d2-a330-a6d648d4ef84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2366162351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2366162351
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.888020372
Short name T623
Test name
Test status
Simulation time 6659188182 ps
CPU time 14.68 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:47:12 PM PDT 24
Peak memory 216396 kb
Host smart-be9e247d-47bc-43ff-8d94-5a0f86225491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888020372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.888020372
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2451361083
Short name T599
Test name
Test status
Simulation time 189301320 ps
CPU time 1.07 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:46:58 PM PDT 24
Peak memory 208024 kb
Host smart-11710463-a5ca-4e74-b5c7-9632266da5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451361083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2451361083
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.579763989
Short name T755
Test name
Test status
Simulation time 23075813 ps
CPU time 0.82 seconds
Started Mar 31 02:46:53 PM PDT 24
Finished Mar 31 02:46:54 PM PDT 24
Peak memory 205716 kb
Host smart-e7c3653e-c12e-4241-8895-12ded8e0e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579763989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.579763989
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3519508041
Short name T503
Test name
Test status
Simulation time 63806077 ps
CPU time 0.77 seconds
Started Mar 31 02:46:59 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 205404 kb
Host smart-102f83e9-8271-4cd4-b425-cf8bb56a0440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519508041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3519508041
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2178796616
Short name T480
Test name
Test status
Simulation time 253822907 ps
CPU time 0.78 seconds
Started Mar 31 02:46:52 PM PDT 24
Finished Mar 31 02:46:53 PM PDT 24
Peak memory 206744 kb
Host smart-0d228db8-e76d-4a12-893a-b4e1413840ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178796616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2178796616
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.797123405
Short name T504
Test name
Test status
Simulation time 31688635099 ps
CPU time 56.5 seconds
Started Mar 31 02:47:00 PM PDT 24
Finished Mar 31 02:47:57 PM PDT 24
Peak memory 233832 kb
Host smart-9cd3a193-50e0-41c8-a4b2-633a9c7b4a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797123405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.797123405
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.558750174
Short name T287
Test name
Test status
Simulation time 5278783342 ps
CPU time 25.2 seconds
Started Mar 31 02:46:58 PM PDT 24
Finished Mar 31 02:47:24 PM PDT 24
Peak memory 234996 kb
Host smart-b826990e-40fd-4555-94c1-8ad40b7fedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558750174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.558750174
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.805657871
Short name T332
Test name
Test status
Simulation time 228470607 ps
CPU time 5.13 seconds
Started Mar 31 02:47:03 PM PDT 24
Finished Mar 31 02:47:10 PM PDT 24
Peak memory 222800 kb
Host smart-c6ae7a01-0b05-4f88-b2e6-e6a202eda85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805657871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.805657871
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1772892551
Short name T469
Test name
Test status
Simulation time 4930850507 ps
CPU time 26.63 seconds
Started Mar 31 02:47:01 PM PDT 24
Finished Mar 31 02:47:28 PM PDT 24
Peak memory 220752 kb
Host smart-ddad7388-2985-4b21-86ad-8e44999fa197
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772892551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1772892551
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.193940405
Short name T387
Test name
Test status
Simulation time 30403565387 ps
CPU time 54.37 seconds
Started Mar 31 02:46:55 PM PDT 24
Finished Mar 31 02:47:49 PM PDT 24
Peak memory 216828 kb
Host smart-7a6af5d9-42c0-419e-805a-bc92c2a1872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193940405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.193940405
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2452301566
Short name T591
Test name
Test status
Simulation time 1138958931 ps
CPU time 4.2 seconds
Started Mar 31 02:46:59 PM PDT 24
Finished Mar 31 02:47:04 PM PDT 24
Peak memory 216228 kb
Host smart-b40dddc6-b9a6-4b6f-8ff0-92abd0568dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452301566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2452301566
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3413597014
Short name T763
Test name
Test status
Simulation time 38842110 ps
CPU time 0.98 seconds
Started Mar 31 02:46:58 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 207972 kb
Host smart-51699e35-2244-4eab-ab96-acf0e61698d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413597014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3413597014
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3639869261
Short name T596
Test name
Test status
Simulation time 158981700 ps
CPU time 1.07 seconds
Started Mar 31 02:46:57 PM PDT 24
Finished Mar 31 02:46:59 PM PDT 24
Peak memory 206684 kb
Host smart-cfc5687c-42a3-44a4-a82b-f9ae1bcd2b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639869261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3639869261
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2438866383
Short name T471
Test name
Test status
Simulation time 107269273 ps
CPU time 0.75 seconds
Started Mar 31 02:47:05 PM PDT 24
Finished Mar 31 02:47:07 PM PDT 24
Peak memory 205304 kb
Host smart-dde8c33d-863b-4630-b778-2ff23fc1e9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438866383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2438866383
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2723723356
Short name T575
Test name
Test status
Simulation time 20318172 ps
CPU time 0.83 seconds
Started Mar 31 02:46:59 PM PDT 24
Finished Mar 31 02:47:00 PM PDT 24
Peak memory 206496 kb
Host smart-c03ae97a-80b7-4e81-83fa-8a46f0a0a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723723356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2723723356
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2246489397
Short name T325
Test name
Test status
Simulation time 5633751802 ps
CPU time 27.12 seconds
Started Mar 31 02:47:05 PM PDT 24
Finished Mar 31 02:47:33 PM PDT 24
Peak memory 241056 kb
Host smart-fc150181-373b-4db7-8359-18624ea86761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246489397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2246489397
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3548348005
Short name T98
Test name
Test status
Simulation time 839239983 ps
CPU time 11.75 seconds
Started Mar 31 02:47:09 PM PDT 24
Finished Mar 31 02:47:22 PM PDT 24
Peak memory 224136 kb
Host smart-a2b54bdb-24f3-4e69-a1df-67ce2c3158be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548348005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3548348005
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1566310369
Short name T334
Test name
Test status
Simulation time 30008031487 ps
CPU time 19.75 seconds
Started Mar 31 02:47:04 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 216820 kb
Host smart-5b476960-7497-422a-bf62-b73676b178e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566310369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1566310369
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1757943257
Short name T427
Test name
Test status
Simulation time 193977055 ps
CPU time 4.39 seconds
Started Mar 31 02:47:06 PM PDT 24
Finished Mar 31 02:47:11 PM PDT 24
Peak memory 219916 kb
Host smart-f78b25c4-4cd1-4469-99bc-11a38d071b41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1757943257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1757943257
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.183041835
Short name T388
Test name
Test status
Simulation time 18320001550 ps
CPU time 59.1 seconds
Started Mar 31 02:47:00 PM PDT 24
Finished Mar 31 02:48:00 PM PDT 24
Peak memory 216388 kb
Host smart-32c20cb8-c2e8-4ebb-901c-d1d2558d019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183041835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.183041835
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3473054655
Short name T420
Test name
Test status
Simulation time 35586510404 ps
CPU time 12.76 seconds
Started Mar 31 02:47:03 PM PDT 24
Finished Mar 31 02:47:17 PM PDT 24
Peak memory 216432 kb
Host smart-97b48447-a2a4-4eb6-939d-7ca86b94cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473054655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3473054655
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1010581150
Short name T517
Test name
Test status
Simulation time 1133847329 ps
CPU time 4.1 seconds
Started Mar 31 02:47:06 PM PDT 24
Finished Mar 31 02:47:10 PM PDT 24
Peak memory 216312 kb
Host smart-1f010ca5-7c93-469f-821c-58e270b74f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010581150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1010581150
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3315849225
Short name T667
Test name
Test status
Simulation time 89398758 ps
CPU time 0.8 seconds
Started Mar 31 02:47:00 PM PDT 24
Finished Mar 31 02:47:01 PM PDT 24
Peak memory 205684 kb
Host smart-bb820703-1960-4e4b-b7f5-3097cf5b866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315849225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3315849225
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3143874554
Short name T203
Test name
Test status
Simulation time 252070865 ps
CPU time 2.66 seconds
Started Mar 31 02:47:07 PM PDT 24
Finished Mar 31 02:47:10 PM PDT 24
Peak memory 222116 kb
Host smart-ee298bf8-1844-4edf-827a-5815a4bc1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143874554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3143874554
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2186080135
Short name T506
Test name
Test status
Simulation time 31692101 ps
CPU time 0.7 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:13 PM PDT 24
Peak memory 204788 kb
Host smart-5c5f6022-d150-4ee8-a683-4a5f911aa1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186080135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2186080135
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2256658197
Short name T211
Test name
Test status
Simulation time 1734704374 ps
CPU time 18.88 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:47:33 PM PDT 24
Peak memory 223016 kb
Host smart-3d2a3b0b-5b8e-499d-b1bc-1f44457d8ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256658197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2256658197
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.617564243
Short name T626
Test name
Test status
Simulation time 188100327 ps
CPU time 0.85 seconds
Started Mar 31 02:47:08 PM PDT 24
Finished Mar 31 02:47:09 PM PDT 24
Peak memory 206492 kb
Host smart-05fa9868-1fcf-47c7-8747-1313ecc9669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617564243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.617564243
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4066865004
Short name T311
Test name
Test status
Simulation time 65375631108 ps
CPU time 95.81 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:48:49 PM PDT 24
Peak memory 249316 kb
Host smart-6bacd750-0885-40a6-9ecc-58fb95657ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066865004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4066865004
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2902224506
Short name T228
Test name
Test status
Simulation time 86009305573 ps
CPU time 69.48 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:48:23 PM PDT 24
Peak memory 222820 kb
Host smart-fc0ad13d-0316-4d0e-8dbc-8ee1b5a2ba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902224506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2902224506
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2568870066
Short name T606
Test name
Test status
Simulation time 652635040 ps
CPU time 5.9 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:18 PM PDT 24
Peak memory 220112 kb
Host smart-7e381231-f5fc-4e19-9974-ccb0e0ac94de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568870066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2568870066
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2752951075
Short name T38
Test name
Test status
Simulation time 44274015 ps
CPU time 1.04 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:13 PM PDT 24
Peak memory 206796 kb
Host smart-7f408249-edf1-4932-b592-00dcd328048d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752951075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2752951075
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1039305355
Short name T761
Test name
Test status
Simulation time 3567568047 ps
CPU time 31.79 seconds
Started Mar 31 02:47:04 PM PDT 24
Finished Mar 31 02:47:37 PM PDT 24
Peak memory 216424 kb
Host smart-a2017075-912b-4329-9d91-88be18aa46c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039305355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1039305355
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3263495158
Short name T419
Test name
Test status
Simulation time 4338184232 ps
CPU time 3.76 seconds
Started Mar 31 02:47:05 PM PDT 24
Finished Mar 31 02:47:09 PM PDT 24
Peak memory 216404 kb
Host smart-84c4a66e-e47c-4c2d-90a3-d15b4b953dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263495158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3263495158
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2773894370
Short name T67
Test name
Test status
Simulation time 281427723 ps
CPU time 1.41 seconds
Started Mar 31 02:47:14 PM PDT 24
Finished Mar 31 02:47:16 PM PDT 24
Peak memory 208252 kb
Host smart-196b9370-bf6e-4842-8e64-2719128da06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773894370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2773894370
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1469179522
Short name T587
Test name
Test status
Simulation time 46726253 ps
CPU time 0.97 seconds
Started Mar 31 02:47:05 PM PDT 24
Finished Mar 31 02:47:07 PM PDT 24
Peak memory 206724 kb
Host smart-92a2e89e-f39c-4d20-ba14-c5586afd6564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469179522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1469179522
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1952855608
Short name T264
Test name
Test status
Simulation time 325405268 ps
CPU time 3.33 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:15 PM PDT 24
Peak memory 218984 kb
Host smart-fb26faa2-af1c-4b58-ad9a-2d5b741c9ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952855608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1952855608
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.162658652
Short name T415
Test name
Test status
Simulation time 13647950 ps
CPU time 0.73 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:12 PM PDT 24
Peak memory 205364 kb
Host smart-6b6655a5-1938-4f95-9a07-49f7d009061b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162658652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.162658652
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1779266152
Short name T721
Test name
Test status
Simulation time 1439751352 ps
CPU time 13.83 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:27 PM PDT 24
Peak memory 216684 kb
Host smart-f4b7178e-cb38-423a-b6ea-6cdddc0db0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779266152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1779266152
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1223835624
Short name T505
Test name
Test status
Simulation time 14513717 ps
CPU time 0.73 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:12 PM PDT 24
Peak memory 205716 kb
Host smart-1b01497c-ac46-495a-a3df-338d40dd553e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223835624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1223835624
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.169335704
Short name T372
Test name
Test status
Simulation time 299615252 ps
CPU time 11.61 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 240956 kb
Host smart-93e6cc34-792e-4119-8e74-08d62a794463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169335704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.169335704
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4258587730
Short name T335
Test name
Test status
Simulation time 19167225526 ps
CPU time 39.55 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:51 PM PDT 24
Peak memory 232808 kb
Host smart-ecc5dc9a-ecb2-4c5e-9bb9-99bfcd184486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258587730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4258587730
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2882985443
Short name T288
Test name
Test status
Simulation time 9709580768 ps
CPU time 33.47 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:47:47 PM PDT 24
Peak memory 218748 kb
Host smart-1fc595cc-ee25-48ea-bd53-e33b815e2e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882985443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2882985443
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2275002194
Short name T275
Test name
Test status
Simulation time 2391644501 ps
CPU time 5.97 seconds
Started Mar 31 02:47:13 PM PDT 24
Finished Mar 31 02:47:20 PM PDT 24
Peak memory 224584 kb
Host smart-869b32d0-dd8e-4937-a890-6121ee27276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275002194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2275002194
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2234742487
Short name T276
Test name
Test status
Simulation time 51617983541 ps
CPU time 11.07 seconds
Started Mar 31 02:47:15 PM PDT 24
Finished Mar 31 02:47:27 PM PDT 24
Peak memory 218452 kb
Host smart-19837537-41b7-4c34-8f08-d4989b5943a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234742487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2234742487
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.488992840
Short name T635
Test name
Test status
Simulation time 3640978760 ps
CPU time 10.71 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:23 PM PDT 24
Peak memory 222916 kb
Host smart-7c6a69f5-64c3-4588-9dab-8d2439fdbe4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488992840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.488992840
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1175249268
Short name T375
Test name
Test status
Simulation time 71413206 ps
CPU time 1.27 seconds
Started Mar 31 02:47:14 PM PDT 24
Finished Mar 31 02:47:15 PM PDT 24
Peak memory 207124 kb
Host smart-2453d50a-514f-4a3d-b5bf-bfc9f5019836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175249268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1175249268
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2795557065
Short name T712
Test name
Test status
Simulation time 3559440473 ps
CPU time 20.37 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:32 PM PDT 24
Peak memory 216428 kb
Host smart-cb625589-2942-47a5-89e8-bf49bb6ed3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795557065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2795557065
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2841750424
Short name T664
Test name
Test status
Simulation time 6431593164 ps
CPU time 21.34 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:33 PM PDT 24
Peak memory 216392 kb
Host smart-0581e6f7-43aa-4dc0-83e2-1fc4aa3e127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841750424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2841750424
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2273902999
Short name T768
Test name
Test status
Simulation time 125247470 ps
CPU time 1.36 seconds
Started Mar 31 02:47:11 PM PDT 24
Finished Mar 31 02:47:13 PM PDT 24
Peak memory 208020 kb
Host smart-7ebc76c4-956d-4ff6-a5f1-27f452de73fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273902999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2273902999
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2609874517
Short name T59
Test name
Test status
Simulation time 103679374 ps
CPU time 0.76 seconds
Started Mar 31 02:47:12 PM PDT 24
Finished Mar 31 02:47:13 PM PDT 24
Peak memory 205736 kb
Host smart-496777e3-bfcd-4faf-ab65-5ead30bc1779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609874517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2609874517
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1647702437
Short name T423
Test name
Test status
Simulation time 13174262 ps
CPU time 0.74 seconds
Started Mar 31 02:47:22 PM PDT 24
Finished Mar 31 02:47:23 PM PDT 24
Peak memory 205344 kb
Host smart-68c93af7-952c-445c-9fbd-9196a12f6626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647702437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1647702437
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2133933290
Short name T743
Test name
Test status
Simulation time 1494383074 ps
CPU time 5.48 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 222412 kb
Host smart-e18d71bb-6b7b-42c7-90d1-15d307e3bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133933290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2133933290
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1153789368
Short name T749
Test name
Test status
Simulation time 19621675 ps
CPU time 0.73 seconds
Started Mar 31 02:47:19 PM PDT 24
Finished Mar 31 02:47:19 PM PDT 24
Peak memory 206836 kb
Host smart-7cb84f9f-5733-4c9a-8ef0-f481a9433d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153789368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1153789368
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1295231626
Short name T485
Test name
Test status
Simulation time 8662870346 ps
CPU time 111.62 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:49:11 PM PDT 24
Peak memory 252468 kb
Host smart-fa1aef8e-1b4c-44dc-bdb5-68dcf3c43f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295231626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1295231626
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1404720326
Short name T260
Test name
Test status
Simulation time 540224438 ps
CPU time 7.41 seconds
Started Mar 31 02:47:21 PM PDT 24
Finished Mar 31 02:47:28 PM PDT 24
Peak memory 221332 kb
Host smart-960591f3-c661-4dbe-8dd5-a740626ef5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404720326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1404720326
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2276569647
Short name T671
Test name
Test status
Simulation time 2938452982 ps
CPU time 25.17 seconds
Started Mar 31 02:47:21 PM PDT 24
Finished Mar 31 02:47:46 PM PDT 24
Peak memory 232824 kb
Host smart-6ff9b843-8b4c-4ab2-80b8-1a714bb7b702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276569647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2276569647
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.500539945
Short name T359
Test name
Test status
Simulation time 6824225964 ps
CPU time 16.47 seconds
Started Mar 31 02:47:22 PM PDT 24
Finished Mar 31 02:47:38 PM PDT 24
Peak memory 218856 kb
Host smart-5859639a-507d-4d97-82c0-e3ff481f7d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500539945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.500539945
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.317792027
Short name T206
Test name
Test status
Simulation time 8312495713 ps
CPU time 9.27 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:29 PM PDT 24
Peak memory 223032 kb
Host smart-761c24a6-1767-452c-9276-93ecec9d3237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317792027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.317792027
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2966079031
Short name T679
Test name
Test status
Simulation time 195744869 ps
CPU time 3.93 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:24 PM PDT 24
Peak memory 220352 kb
Host smart-a468693f-b883-40eb-ba67-5bbde5e26a8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2966079031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2966079031
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2888550986
Short name T448
Test name
Test status
Simulation time 406357383 ps
CPU time 1.95 seconds
Started Mar 31 02:47:23 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 207004 kb
Host smart-397287e3-cf25-4fd1-916c-d57993ccd518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888550986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2888550986
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3053627700
Short name T716
Test name
Test status
Simulation time 48645430 ps
CPU time 0.93 seconds
Started Mar 31 02:47:21 PM PDT 24
Finished Mar 31 02:47:22 PM PDT 24
Peak memory 207084 kb
Host smart-ddc32781-3054-4b51-bbbf-2da3aa15ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053627700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3053627700
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.27986621
Short name T442
Test name
Test status
Simulation time 204177997 ps
CPU time 1.02 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:21 PM PDT 24
Peak memory 206668 kb
Host smart-d718e259-7fec-4f25-b83e-6b149f6b08d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27986621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.27986621
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.145388612
Short name T649
Test name
Test status
Simulation time 13096665 ps
CPU time 0.72 seconds
Started Mar 31 02:47:24 PM PDT 24
Finished Mar 31 02:47:25 PM PDT 24
Peak memory 204712 kb
Host smart-c02e0e0e-53c0-4f20-b14c-01514af27085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145388612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.145388612
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.218227483
Short name T560
Test name
Test status
Simulation time 280172383 ps
CPU time 0.76 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:21 PM PDT 24
Peak memory 206468 kb
Host smart-d279b6b6-0e69-49d2-80cd-d56543c46083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218227483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.218227483
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3771187639
Short name T751
Test name
Test status
Simulation time 31768334849 ps
CPU time 63.37 seconds
Started Mar 31 02:47:21 PM PDT 24
Finished Mar 31 02:48:24 PM PDT 24
Peak memory 234952 kb
Host smart-32566682-50a2-44ca-8028-0aa578b03ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771187639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3771187639
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1676203921
Short name T738
Test name
Test status
Simulation time 4333741980 ps
CPU time 13.95 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:47:34 PM PDT 24
Peak memory 217416 kb
Host smart-eed19adc-2f27-44ca-9f85-2880c8bcb422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676203921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1676203921
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2282284979
Short name T8
Test name
Test status
Simulation time 9547736740 ps
CPU time 83.1 seconds
Started Mar 31 02:47:20 PM PDT 24
Finished Mar 31 02:48:43 PM PDT 24
Peak memory 220580 kb
Host smart-6180457f-3a8d-4968-93b6-da2b1d9bcf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282284979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2282284979
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3888010153
Short name T291
Test name
Test status
Simulation time 2244704115 ps
CPU time 9 seconds
Started Mar 31 02:47:18 PM PDT 24
Finished Mar 31 02:47:27 PM PDT 24
Peak memory 240488 kb
Host smart-79d17523-f324-4f53-8e5e-44ff61a6ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888010153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3888010153
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1636104443
Short name T710
Test name
Test status
Simulation time 868372255 ps
CPU time 10.73 seconds
Started Mar 31 02:47:21 PM PDT 24
Finished Mar 31 02:47:32 PM PDT 24
Peak memory 222884 kb
Host smart-6ab3f970-880e-4b74-845f-7474bd4ad3f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636104443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1636104443
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3662388550
Short name T610
Test name
Test status
Simulation time 102901187 ps
CPU time 1.02 seconds
Started Mar 31 02:47:26 PM PDT 24
Finished Mar 31 02:47:27 PM PDT 24
Peak memory 206804 kb
Host smart-dd56fc05-6c9a-4707-a036-2a800b75285e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662388550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3662388550
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3384131346
Short name T723
Test name
Test status
Simulation time 2668198678 ps
CPU time 13.79 seconds
Started Mar 31 02:47:18 PM PDT 24
Finished Mar 31 02:47:32 PM PDT 24
Peak memory 216448 kb
Host smart-f870c54f-f17d-43df-83c9-35577ffdf9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384131346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3384131346
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2265545126
Short name T544
Test name
Test status
Simulation time 2849105086 ps
CPU time 13.25 seconds
Started Mar 31 02:47:18 PM PDT 24
Finished Mar 31 02:47:31 PM PDT 24
Peak memory 216452 kb
Host smart-3726b886-a5e2-4a63-a6a2-afae6b426fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265545126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2265545126
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1004457909
Short name T409
Test name
Test status
Simulation time 22707147 ps
CPU time 1.16 seconds
Started Mar 31 02:47:19 PM PDT 24
Finished Mar 31 02:47:20 PM PDT 24
Peak memory 208476 kb
Host smart-a4436dca-8f2c-43a4-a8c3-193d703ad054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004457909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1004457909
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3999333895
Short name T528
Test name
Test status
Simulation time 15392305 ps
CPU time 0.71 seconds
Started Mar 31 02:47:19 PM PDT 24
Finished Mar 31 02:47:20 PM PDT 24
Peak memory 205676 kb
Host smart-3fc791dc-84dc-4b77-b0ca-e4c531db10d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999333895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3999333895
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.469160215
Short name T646
Test name
Test status
Simulation time 36881895 ps
CPU time 0.71 seconds
Started Mar 31 02:47:37 PM PDT 24
Finished Mar 31 02:47:37 PM PDT 24
Peak memory 205348 kb
Host smart-2c373788-3868-45c3-b3f4-82b86c8f5b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469160215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.469160215
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3674187689
Short name T475
Test name
Test status
Simulation time 290799595 ps
CPU time 3 seconds
Started Mar 31 02:47:30 PM PDT 24
Finished Mar 31 02:47:33 PM PDT 24
Peak memory 218044 kb
Host smart-aa1c583b-4781-4e54-b460-9f1860c2556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674187689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3674187689
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1005241029
Short name T572
Test name
Test status
Simulation time 21799752 ps
CPU time 0.79 seconds
Started Mar 31 02:47:25 PM PDT 24
Finished Mar 31 02:47:26 PM PDT 24
Peak memory 206520 kb
Host smart-4ef691ba-a463-4fc3-8573-5009c24deba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005241029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1005241029
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2171977782
Short name T310
Test name
Test status
Simulation time 1124900314 ps
CPU time 16.87 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:51 PM PDT 24
Peak memory 241008 kb
Host smart-0f2c4597-6b84-4fa2-a26d-32b3421c2dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171977782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2171977782
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.512183393
Short name T93
Test name
Test status
Simulation time 1672658263 ps
CPU time 3.2 seconds
Started Mar 31 02:47:28 PM PDT 24
Finished Mar 31 02:47:31 PM PDT 24
Peak memory 222316 kb
Host smart-62703d9f-3e75-4fb1-81ae-e0b7d1fc5002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512183393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.512183393
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1955937815
Short name T76
Test name
Test status
Simulation time 1862331797 ps
CPU time 6.01 seconds
Started Mar 31 02:47:27 PM PDT 24
Finished Mar 31 02:47:33 PM PDT 24
Peak memory 216784 kb
Host smart-b055d4b8-e8b7-4e77-8310-1c4ca01605ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955937815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1955937815
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1099874761
Short name T465
Test name
Test status
Simulation time 191519279 ps
CPU time 3.64 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:38 PM PDT 24
Peak memory 220228 kb
Host smart-a4b5fae5-1301-451a-bdde-1274d9663db4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1099874761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1099874761
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.465324499
Short name T32
Test name
Test status
Simulation time 33873385 ps
CPU time 0.82 seconds
Started Mar 31 02:47:33 PM PDT 24
Finished Mar 31 02:47:34 PM PDT 24
Peak memory 205680 kb
Host smart-731394bb-511c-4ddc-9761-22a898b172d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465324499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.465324499
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1714967010
Short name T589
Test name
Test status
Simulation time 6864864142 ps
CPU time 34.05 seconds
Started Mar 31 02:47:26 PM PDT 24
Finished Mar 31 02:48:00 PM PDT 24
Peak memory 216436 kb
Host smart-bf5ab832-fd2d-464f-b14e-15d6f6982b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714967010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1714967010
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1711857779
Short name T417
Test name
Test status
Simulation time 621683004 ps
CPU time 3.33 seconds
Started Mar 31 02:47:27 PM PDT 24
Finished Mar 31 02:47:30 PM PDT 24
Peak memory 216328 kb
Host smart-f6c472de-bb86-4f50-aa9f-6a37be954b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711857779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1711857779
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2152856704
Short name T460
Test name
Test status
Simulation time 190551039 ps
CPU time 0.93 seconds
Started Mar 31 02:47:28 PM PDT 24
Finished Mar 31 02:47:29 PM PDT 24
Peak memory 207764 kb
Host smart-0fdb4289-ceae-4711-8f90-eedffe2c2003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152856704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2152856704
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2406257960
Short name T728
Test name
Test status
Simulation time 42639484 ps
CPU time 0.87 seconds
Started Mar 31 02:47:26 PM PDT 24
Finished Mar 31 02:47:27 PM PDT 24
Peak memory 206724 kb
Host smart-e274cc3a-f49c-4de4-90f7-2d7747b8a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406257960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2406257960
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2041619826
Short name T713
Test name
Test status
Simulation time 65911439 ps
CPU time 0.76 seconds
Started Mar 31 02:47:43 PM PDT 24
Finished Mar 31 02:47:44 PM PDT 24
Peak memory 205628 kb
Host smart-0ff9bd6d-c0b6-4984-acca-6c36ca2cd842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041619826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2041619826
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1651717527
Short name T458
Test name
Test status
Simulation time 32969277 ps
CPU time 0.76 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:35 PM PDT 24
Peak memory 205456 kb
Host smart-4780a526-5d41-4bc0-9ace-9396d32ba342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651717527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1651717527
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2508796043
Short name T694
Test name
Test status
Simulation time 11964162572 ps
CPU time 44 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:48:18 PM PDT 24
Peak memory 237572 kb
Host smart-27e7626f-363b-4fe2-b844-6ba7c78cee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508796043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2508796043
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1857561110
Short name T306
Test name
Test status
Simulation time 18359607106 ps
CPU time 35.75 seconds
Started Mar 31 02:47:33 PM PDT 24
Finished Mar 31 02:48:09 PM PDT 24
Peak memory 232808 kb
Host smart-432b0609-3c3a-4986-b390-43dd35aebc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857561110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1857561110
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4098413549
Short name T352
Test name
Test status
Simulation time 1152121403 ps
CPU time 2.57 seconds
Started Mar 31 02:47:37 PM PDT 24
Finished Mar 31 02:47:40 PM PDT 24
Peak memory 218608 kb
Host smart-e1e3b0b1-b83c-426f-97a5-5b2e2db9dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098413549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4098413549
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2651302355
Short name T588
Test name
Test status
Simulation time 906287977 ps
CPU time 5.16 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:40 PM PDT 24
Peak memory 222760 kb
Host smart-03aea5cb-0ba9-40d0-8c99-5d7d6323f1bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2651302355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2651302355
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3028298705
Short name T403
Test name
Test status
Simulation time 31612842225 ps
CPU time 48.08 seconds
Started Mar 31 02:47:36 PM PDT 24
Finished Mar 31 02:48:24 PM PDT 24
Peak memory 216416 kb
Host smart-d3a8fcae-25f9-4cce-89a1-da052af3b386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028298705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3028298705
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.437666117
Short name T21
Test name
Test status
Simulation time 966460911 ps
CPU time 1.39 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:36 PM PDT 24
Peak memory 206840 kb
Host smart-9880ac5a-c2d8-458d-96d3-d1ba95bf49e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437666117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.437666117
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.904364472
Short name T438
Test name
Test status
Simulation time 232522565 ps
CPU time 1.63 seconds
Started Mar 31 02:47:35 PM PDT 24
Finished Mar 31 02:47:37 PM PDT 24
Peak memory 216436 kb
Host smart-36e0716c-6221-4ea3-b8e7-3390457e28d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904364472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.904364472
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2382772256
Short name T668
Test name
Test status
Simulation time 48183284 ps
CPU time 0.7 seconds
Started Mar 31 02:47:34 PM PDT 24
Finished Mar 31 02:47:34 PM PDT 24
Peak memory 205708 kb
Host smart-13007000-0c09-4e78-906b-f97c0ae5a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382772256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2382772256
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1226189699
Short name T277
Test name
Test status
Simulation time 25041791374 ps
CPU time 22.09 seconds
Started Mar 31 02:47:32 PM PDT 24
Finished Mar 31 02:47:55 PM PDT 24
Peak memory 236372 kb
Host smart-77404214-d3b8-4bad-8c82-585b2cee1268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226189699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1226189699
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.201761438
Short name T30
Test name
Test status
Simulation time 13673889 ps
CPU time 0.72 seconds
Started Mar 31 02:47:45 PM PDT 24
Finished Mar 31 02:47:45 PM PDT 24
Peak memory 205356 kb
Host smart-547e30e7-0311-46ee-b918-37c4e870e059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201761438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.201761438
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3872325255
Short name T707
Test name
Test status
Simulation time 190104594 ps
CPU time 0.8 seconds
Started Mar 31 02:47:39 PM PDT 24
Finished Mar 31 02:47:40 PM PDT 24
Peak memory 206472 kb
Host smart-dd80f8bb-2e71-4e82-9b6c-4b58617a78ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872325255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3872325255
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.832103267
Short name T6
Test name
Test status
Simulation time 442939178 ps
CPU time 7.35 seconds
Started Mar 31 02:47:41 PM PDT 24
Finished Mar 31 02:47:49 PM PDT 24
Peak memory 218896 kb
Host smart-bbf35251-2911-4691-85f7-b0c99ab6e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832103267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.832103267
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.410134582
Short name T3
Test name
Test status
Simulation time 1836286908 ps
CPU time 18.91 seconds
Started Mar 31 02:47:46 PM PDT 24
Finished Mar 31 02:48:05 PM PDT 24
Peak memory 219640 kb
Host smart-cdffcb6d-2ea5-419b-93b3-2ce3d2a28fae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=410134582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.410134582
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2664458063
Short name T654
Test name
Test status
Simulation time 8366984028 ps
CPU time 17.73 seconds
Started Mar 31 02:47:42 PM PDT 24
Finished Mar 31 02:48:00 PM PDT 24
Peak memory 216432 kb
Host smart-af924266-b6d4-49ef-8c05-238ec6c81f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664458063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2664458063
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1840254467
Short name T436
Test name
Test status
Simulation time 86699062529 ps
CPU time 16.75 seconds
Started Mar 31 02:47:40 PM PDT 24
Finished Mar 31 02:47:57 PM PDT 24
Peak memory 216384 kb
Host smart-848345f4-18cf-40df-997f-f9d6be9c0eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840254467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1840254467
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.444219935
Short name T531
Test name
Test status
Simulation time 236637641 ps
CPU time 2.49 seconds
Started Mar 31 02:47:41 PM PDT 24
Finished Mar 31 02:47:43 PM PDT 24
Peak memory 216396 kb
Host smart-8610615b-a353-4bf9-a8ea-64125df845f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444219935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.444219935
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.771999579
Short name T543
Test name
Test status
Simulation time 134754423 ps
CPU time 1.09 seconds
Started Mar 31 02:47:40 PM PDT 24
Finished Mar 31 02:47:41 PM PDT 24
Peak memory 206736 kb
Host smart-bc4c85fd-1c50-4159-b2ee-9567f4aba737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771999579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.771999579
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.431575626
Short name T628
Test name
Test status
Simulation time 48100967 ps
CPU time 0.75 seconds
Started Mar 31 02:44:12 PM PDT 24
Finished Mar 31 02:44:13 PM PDT 24
Peak memory 205280 kb
Host smart-ef4aebea-2a07-4328-bb69-d7a27d15090e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431575626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.431575626
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.321663891
Short name T28
Test name
Test status
Simulation time 969802521 ps
CPU time 10.01 seconds
Started Mar 31 02:44:13 PM PDT 24
Finished Mar 31 02:44:23 PM PDT 24
Peak memory 218684 kb
Host smart-bf64adb2-ca47-48be-b670-7e0df18911d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321663891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.321663891
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3358832349
Short name T693
Test name
Test status
Simulation time 49092651 ps
CPU time 0.74 seconds
Started Mar 31 02:44:07 PM PDT 24
Finished Mar 31 02:44:09 PM PDT 24
Peak memory 205336 kb
Host smart-95ab1118-ca4d-4169-aac7-2230cf8fa5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358832349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3358832349
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3195405068
Short name T235
Test name
Test status
Simulation time 448731929 ps
CPU time 2.83 seconds
Started Mar 31 02:44:13 PM PDT 24
Finished Mar 31 02:44:16 PM PDT 24
Peak memory 216832 kb
Host smart-81b88f87-0c7e-4c69-8d90-3f1f8b2478f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195405068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3195405068
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.726708803
Short name T298
Test name
Test status
Simulation time 2007351242 ps
CPU time 35.61 seconds
Started Mar 31 02:44:11 PM PDT 24
Finished Mar 31 02:44:47 PM PDT 24
Peak memory 223732 kb
Host smart-ccc0479e-1166-48a1-a6a5-2cfbc1036bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726708803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.726708803
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2721755692
Short name T562
Test name
Test status
Simulation time 86416816 ps
CPU time 1.02 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 218036 kb
Host smart-e5d79f6b-4f1d-439d-a660-31056b4e4943
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721755692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2721755692
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2562177761
Short name T222
Test name
Test status
Simulation time 6944721342 ps
CPU time 17.13 seconds
Started Mar 31 02:44:11 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 221836 kb
Host smart-8142fce4-f0a8-40cc-bc96-acfdcc15ebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562177761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2562177761
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.15576472
Short name T597
Test name
Test status
Simulation time 42702216 ps
CPU time 0.71 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 216316 kb
Host smart-6bd36ad4-1cab-41ce-ab44-ea4df76b1bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15576472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.15576472
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.283330188
Short name T170
Test name
Test status
Simulation time 1744415825 ps
CPU time 8.19 seconds
Started Mar 31 02:44:14 PM PDT 24
Finished Mar 31 02:44:22 PM PDT 24
Peak memory 219080 kb
Host smart-3e454915-5c8c-47ec-8a4a-64595c429985
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=283330188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.283330188
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3600425889
Short name T400
Test name
Test status
Simulation time 68758122928 ps
CPU time 60.79 seconds
Started Mar 31 02:44:09 PM PDT 24
Finished Mar 31 02:45:11 PM PDT 24
Peak memory 216536 kb
Host smart-4c6e4829-8e23-44e7-a5b6-bd07f40608eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600425889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3600425889
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3581255350
Short name T603
Test name
Test status
Simulation time 2283803821 ps
CPU time 12.31 seconds
Started Mar 31 02:44:07 PM PDT 24
Finished Mar 31 02:44:20 PM PDT 24
Peak memory 216404 kb
Host smart-693ed44b-948f-42cf-aa78-b95bd8be2826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581255350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3581255350
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.473546620
Short name T411
Test name
Test status
Simulation time 285294889 ps
CPU time 10.46 seconds
Started Mar 31 02:44:05 PM PDT 24
Finished Mar 31 02:44:16 PM PDT 24
Peak memory 216592 kb
Host smart-20c9b487-1a48-4fe7-8cc0-8c8e64442cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473546620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.473546620
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3283150407
Short name T507
Test name
Test status
Simulation time 43146600 ps
CPU time 0.68 seconds
Started Mar 31 02:44:06 PM PDT 24
Finished Mar 31 02:44:08 PM PDT 24
Peak memory 205668 kb
Host smart-bdd62eae-1a0b-444b-b70a-ab9507c53524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283150407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3283150407
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.472671274
Short name T213
Test name
Test status
Simulation time 1476174078 ps
CPU time 7.37 seconds
Started Mar 31 02:44:14 PM PDT 24
Finished Mar 31 02:44:21 PM PDT 24
Peak memory 220872 kb
Host smart-35076f6e-3b34-43e1-a136-75d982ff55bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472671274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.472671274
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2425877186
Short name T527
Test name
Test status
Simulation time 102684345 ps
CPU time 0.7 seconds
Started Mar 31 02:44:21 PM PDT 24
Finished Mar 31 02:44:22 PM PDT 24
Peak memory 204632 kb
Host smart-3963a765-bc38-411a-92d4-14a3e91076c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425877186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
425877186
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2137261632
Short name T269
Test name
Test status
Simulation time 51776473 ps
CPU time 2.61 seconds
Started Mar 31 02:44:15 PM PDT 24
Finished Mar 31 02:44:18 PM PDT 24
Peak memory 222904 kb
Host smart-ad955e93-2cc1-4c05-a42a-72bec11cb609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137261632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2137261632
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3157435699
Short name T412
Test name
Test status
Simulation time 52697383 ps
CPU time 0.76 seconds
Started Mar 31 02:44:12 PM PDT 24
Finished Mar 31 02:44:13 PM PDT 24
Peak memory 205788 kb
Host smart-94dc7de7-87ac-4d2a-aa5d-9f338ef1b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157435699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3157435699
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1592079835
Short name T691
Test name
Test status
Simulation time 5541793937 ps
CPU time 76.72 seconds
Started Mar 31 02:44:15 PM PDT 24
Finished Mar 31 02:45:32 PM PDT 24
Peak memory 232660 kb
Host smart-ec17df3b-372a-4b71-b8fd-b923344d7bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592079835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1592079835
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3718926205
Short name T44
Test name
Test status
Simulation time 269048173 ps
CPU time 6.41 seconds
Started Mar 31 02:44:14 PM PDT 24
Finished Mar 31 02:44:21 PM PDT 24
Peak memory 221840 kb
Host smart-ae59bead-6b44-40e8-b99b-3378c699a900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718926205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3718926205
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4037300772
Short name T330
Test name
Test status
Simulation time 36483480479 ps
CPU time 74.12 seconds
Started Mar 31 02:44:12 PM PDT 24
Finished Mar 31 02:45:26 PM PDT 24
Peak memory 224028 kb
Host smart-7be71461-9f5a-4edf-9279-46b388f36e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037300772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4037300772
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2039884845
Short name T636
Test name
Test status
Simulation time 53251227 ps
CPU time 1.04 seconds
Started Mar 31 02:44:13 PM PDT 24
Finished Mar 31 02:44:15 PM PDT 24
Peak memory 216740 kb
Host smart-cb5e3bd4-79ae-485f-9ba2-0930fa94139b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039884845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2039884845
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.350777709
Short name T91
Test name
Test status
Simulation time 1578031840 ps
CPU time 4.03 seconds
Started Mar 31 02:44:11 PM PDT 24
Finished Mar 31 02:44:15 PM PDT 24
Peak memory 218544 kb
Host smart-d31b1e36-c47a-4433-96bd-68da6804bc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350777709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
350777709
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1434551199
Short name T307
Test name
Test status
Simulation time 4227122282 ps
CPU time 14.55 seconds
Started Mar 31 02:44:13 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 236128 kb
Host smart-79cd1b5d-61d2-4b38-9fa9-c5cb2038bd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434551199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1434551199
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3031882480
Short name T695
Test name
Test status
Simulation time 41323653 ps
CPU time 0.74 seconds
Started Mar 31 02:44:12 PM PDT 24
Finished Mar 31 02:44:13 PM PDT 24
Peak memory 216220 kb
Host smart-08ff9214-0278-4d38-a07e-544652b67b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031882480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3031882480
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1639539601
Short name T762
Test name
Test status
Simulation time 2349341150 ps
CPU time 6.82 seconds
Started Mar 31 02:44:16 PM PDT 24
Finished Mar 31 02:44:23 PM PDT 24
Peak memory 219372 kb
Host smart-cfc484e0-fe7d-48ce-98d9-5a98ee29c885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1639539601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1639539601
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1014313542
Short name T20
Test name
Test status
Simulation time 4502856479 ps
CPU time 16.72 seconds
Started Mar 31 02:44:10 PM PDT 24
Finished Mar 31 02:44:27 PM PDT 24
Peak memory 216488 kb
Host smart-10c9a36d-6f37-491a-a1a3-aa0a7dc87968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014313542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1014313542
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2693925873
Short name T440
Test name
Test status
Simulation time 2258164569 ps
CPU time 11.59 seconds
Started Mar 31 02:44:13 PM PDT 24
Finished Mar 31 02:44:25 PM PDT 24
Peak memory 216440 kb
Host smart-1feb11b5-f12b-45ee-abcb-912e8ccd7a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693925873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2693925873
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.749565221
Short name T744
Test name
Test status
Simulation time 171258258 ps
CPU time 2.97 seconds
Started Mar 31 02:44:14 PM PDT 24
Finished Mar 31 02:44:17 PM PDT 24
Peak memory 216612 kb
Host smart-a9e244fa-412a-46bd-9d2f-8caff08fa506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749565221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.749565221
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1746798247
Short name T745
Test name
Test status
Simulation time 29330595 ps
CPU time 0.78 seconds
Started Mar 31 02:44:12 PM PDT 24
Finished Mar 31 02:44:13 PM PDT 24
Peak memory 205696 kb
Host smart-b3b61117-191c-40b8-8ec9-a451bed8c3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746798247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1746798247
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3163038927
Short name T346
Test name
Test status
Simulation time 16041853615 ps
CPU time 49.06 seconds
Started Mar 31 02:44:17 PM PDT 24
Finished Mar 31 02:45:06 PM PDT 24
Peak memory 232892 kb
Host smart-f66c507b-a4e1-4f34-8e55-ef2899dd5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163038927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3163038927
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4231334661
Short name T474
Test name
Test status
Simulation time 10545316 ps
CPU time 0.71 seconds
Started Mar 31 02:44:21 PM PDT 24
Finished Mar 31 02:44:22 PM PDT 24
Peak memory 205392 kb
Host smart-9e641d32-cb0e-4ee6-8f54-5d88455d4b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231334661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
231334661
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3669386938
Short name T225
Test name
Test status
Simulation time 479270594 ps
CPU time 4.2 seconds
Started Mar 31 02:44:21 PM PDT 24
Finished Mar 31 02:44:25 PM PDT 24
Peak memory 232356 kb
Host smart-bfe717ca-32f2-4556-824c-f9d02abcd1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669386938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3669386938
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3119921879
Short name T558
Test name
Test status
Simulation time 28609878 ps
CPU time 0.8 seconds
Started Mar 31 02:44:16 PM PDT 24
Finished Mar 31 02:44:17 PM PDT 24
Peak memory 206820 kb
Host smart-b8f899f2-8a36-4d78-a344-f716eaeb0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119921879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3119921879
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2657079575
Short name T569
Test name
Test status
Simulation time 7890781076 ps
CPU time 93.09 seconds
Started Mar 31 02:44:15 PM PDT 24
Finished Mar 31 02:45:49 PM PDT 24
Peak memory 249284 kb
Host smart-abf9e0e9-d315-4298-abcd-ab7f437346fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657079575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2657079575
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3627965260
Short name T478
Test name
Test status
Simulation time 559807509 ps
CPU time 4.49 seconds
Started Mar 31 02:44:18 PM PDT 24
Finished Mar 31 02:44:23 PM PDT 24
Peak memory 216664 kb
Host smart-421219b8-6834-4e16-8e7a-b0e4a4e2a54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627965260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3627965260
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.422486099
Short name T249
Test name
Test status
Simulation time 1635281808 ps
CPU time 16.03 seconds
Started Mar 31 02:44:17 PM PDT 24
Finished Mar 31 02:44:34 PM PDT 24
Peak memory 235284 kb
Host smart-91c4374d-05a0-4c37-a4b9-bfdcaf326362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422486099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.422486099
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.176254708
Short name T186
Test name
Test status
Simulation time 17149777 ps
CPU time 1.06 seconds
Started Mar 31 02:44:18 PM PDT 24
Finished Mar 31 02:44:19 PM PDT 24
Peak memory 216836 kb
Host smart-6bb8d9a8-065e-4c57-ac27-580e4a4d7c27
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176254708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.176254708
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.963167699
Short name T364
Test name
Test status
Simulation time 5061987400 ps
CPU time 17.02 seconds
Started Mar 31 02:44:17 PM PDT 24
Finished Mar 31 02:44:35 PM PDT 24
Peak memory 219008 kb
Host smart-377ad408-f7d8-4ec1-a1e6-a13f7de67086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963167699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
963167699
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1054710334
Short name T356
Test name
Test status
Simulation time 2108537405 ps
CPU time 10.64 seconds
Started Mar 31 02:44:18 PM PDT 24
Finished Mar 31 02:44:29 PM PDT 24
Peak memory 222664 kb
Host smart-a789b909-fd0a-4d7e-83a1-d8b399d5850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054710334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1054710334
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.995493835
Short name T522
Test name
Test status
Simulation time 46417956 ps
CPU time 0.74 seconds
Started Mar 31 02:44:19 PM PDT 24
Finished Mar 31 02:44:20 PM PDT 24
Peak memory 216276 kb
Host smart-cfaa0897-1cec-4762-90e8-8de440ec9d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995493835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.995493835
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1508583811
Short name T568
Test name
Test status
Simulation time 1585337253 ps
CPU time 8.12 seconds
Started Mar 31 02:44:25 PM PDT 24
Finished Mar 31 02:44:33 PM PDT 24
Peak memory 218644 kb
Host smart-cd46fe37-2f2a-4ccb-bb76-6b58fd5f9272
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508583811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1508583811
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2575251157
Short name T697
Test name
Test status
Simulation time 4690991065 ps
CPU time 23.05 seconds
Started Mar 31 02:44:17 PM PDT 24
Finished Mar 31 02:44:40 PM PDT 24
Peak memory 216476 kb
Host smart-2cd219ca-3ef0-4752-b078-3ef01e1b37d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575251157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2575251157
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1117950987
Short name T462
Test name
Test status
Simulation time 1473045432 ps
CPU time 2.65 seconds
Started Mar 31 02:44:23 PM PDT 24
Finished Mar 31 02:44:25 PM PDT 24
Peak memory 216192 kb
Host smart-25b18701-1606-41bd-81fb-6a369c0a1673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117950987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1117950987
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4133515653
Short name T470
Test name
Test status
Simulation time 1039575799 ps
CPU time 3.16 seconds
Started Mar 31 02:44:18 PM PDT 24
Finished Mar 31 02:44:21 PM PDT 24
Peak memory 216412 kb
Host smart-37d7e6e4-0368-4d2d-b454-4681db62d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133515653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4133515653
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2799640207
Short name T19
Test name
Test status
Simulation time 54798209 ps
CPU time 0.77 seconds
Started Mar 31 02:44:17 PM PDT 24
Finished Mar 31 02:44:18 PM PDT 24
Peak memory 205652 kb
Host smart-023f2910-90f5-4b29-ac1c-1055d5edba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799640207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2799640207
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3155030021
Short name T439
Test name
Test status
Simulation time 21212294 ps
CPU time 0.72 seconds
Started Mar 31 02:44:24 PM PDT 24
Finished Mar 31 02:44:25 PM PDT 24
Peak memory 205672 kb
Host smart-76170ed9-30de-4041-8b8e-4e5f90b5e602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155030021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
155030021
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.41398317
Short name T681
Test name
Test status
Simulation time 38696698 ps
CPU time 0.81 seconds
Started Mar 31 02:44:24 PM PDT 24
Finished Mar 31 02:44:25 PM PDT 24
Peak memory 206788 kb
Host smart-db844cf2-31c2-4b16-bdbf-aa3a8a840774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41398317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.41398317
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3062208044
Short name T764
Test name
Test status
Simulation time 7366986035 ps
CPU time 97.57 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:46:00 PM PDT 24
Peak memory 232828 kb
Host smart-155da992-d710-4755-acd4-1807726236c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062208044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3062208044
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3188844864
Short name T190
Test name
Test status
Simulation time 334378016 ps
CPU time 5.25 seconds
Started Mar 31 02:44:24 PM PDT 24
Finished Mar 31 02:44:29 PM PDT 24
Peak memory 232364 kb
Host smart-550b7c32-1d57-478d-b75a-e9530d30213e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188844864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3188844864
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1279947097
Short name T730
Test name
Test status
Simulation time 2920774616 ps
CPU time 34.48 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:56 PM PDT 24
Peak memory 239152 kb
Host smart-060a8a21-0bf7-42a6-973b-7701816d0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279947097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1279947097
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2289986550
Short name T519
Test name
Test status
Simulation time 26540607 ps
CPU time 1.06 seconds
Started Mar 31 02:44:23 PM PDT 24
Finished Mar 31 02:44:24 PM PDT 24
Peak memory 218048 kb
Host smart-604acccc-126b-47cc-a403-0899b5a91d27
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289986550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2289986550
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.951967987
Short name T74
Test name
Test status
Simulation time 7929450409 ps
CPU time 5.89 seconds
Started Mar 31 02:44:25 PM PDT 24
Finished Mar 31 02:44:31 PM PDT 24
Peak memory 219112 kb
Host smart-c84d8136-da7b-4299-b00e-5e24cf8da63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951967987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
951967987
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3174167654
Short name T289
Test name
Test status
Simulation time 2174865645 ps
CPU time 7.08 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:29 PM PDT 24
Peak memory 232864 kb
Host smart-b05e3e01-56d2-4172-9a29-14d31628c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174167654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3174167654
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1162653779
Short name T648
Test name
Test status
Simulation time 18429222 ps
CPU time 0.78 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:23 PM PDT 24
Peak memory 216300 kb
Host smart-3d590b46-6824-47e6-91a0-0429b1c7d975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162653779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1162653779
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1870430266
Short name T495
Test name
Test status
Simulation time 557421749 ps
CPU time 5.53 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:27 PM PDT 24
Peak memory 220000 kb
Host smart-451e6499-a9c9-460b-825d-f100b7f59fe8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1870430266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1870430266
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1121216846
Short name T389
Test name
Test status
Simulation time 1907394686 ps
CPU time 19.12 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:42 PM PDT 24
Peak memory 216412 kb
Host smart-fd381859-36b6-4388-b5be-79d3e2b63609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121216846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1121216846
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1346587251
Short name T698
Test name
Test status
Simulation time 2469686307 ps
CPU time 5.04 seconds
Started Mar 31 02:44:21 PM PDT 24
Finished Mar 31 02:44:27 PM PDT 24
Peak memory 216344 kb
Host smart-9e33ab98-214d-4bd7-ad73-bd7e76c6eaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346587251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1346587251
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.921733347
Short name T530
Test name
Test status
Simulation time 38354786 ps
CPU time 0.74 seconds
Started Mar 31 02:44:22 PM PDT 24
Finished Mar 31 02:44:22 PM PDT 24
Peak memory 205748 kb
Host smart-03361585-581a-4ae0-bc94-270a53e6dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921733347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.921733347
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3739893197
Short name T501
Test name
Test status
Simulation time 60116553 ps
CPU time 0.93 seconds
Started Mar 31 02:44:21 PM PDT 24
Finished Mar 31 02:44:22 PM PDT 24
Peak memory 205720 kb
Host smart-20ed074d-afd7-4c22-8696-49e745263222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739893197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3739893197
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.373681735
Short name T459
Test name
Test status
Simulation time 14823837 ps
CPU time 0.73 seconds
Started Mar 31 02:44:27 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 205356 kb
Host smart-ec3e4fea-9043-4643-9333-af4cc5b24bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373681735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.373681735
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.423345836
Short name T463
Test name
Test status
Simulation time 32933178 ps
CPU time 0.78 seconds
Started Mar 31 02:44:28 PM PDT 24
Finished Mar 31 02:44:29 PM PDT 24
Peak memory 206804 kb
Host smart-58fb37b2-a93a-47c7-a8ae-9c81e4627375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423345836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.423345836
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3766950148
Short name T319
Test name
Test status
Simulation time 481127845 ps
CPU time 18.15 seconds
Started Mar 31 02:44:32 PM PDT 24
Finished Mar 31 02:44:50 PM PDT 24
Peak memory 249084 kb
Host smart-50a58d06-c61e-4381-bdf0-3a339762fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766950148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3766950148
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3697755438
Short name T545
Test name
Test status
Simulation time 21718505 ps
CPU time 1.02 seconds
Started Mar 31 02:44:27 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 216768 kb
Host smart-ebafdf05-ad05-469e-aa78-823873bc2725
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697755438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3697755438
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3285867410
Short name T446
Test name
Test status
Simulation time 16252480 ps
CPU time 0.77 seconds
Started Mar 31 02:44:27 PM PDT 24
Finished Mar 31 02:44:28 PM PDT 24
Peak memory 216280 kb
Host smart-f36f62c1-50ff-40cb-b7a5-1f62ac41fa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285867410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3285867410
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4201950299
Short name T167
Test name
Test status
Simulation time 1253533786 ps
CPU time 10.07 seconds
Started Mar 31 02:44:28 PM PDT 24
Finished Mar 31 02:44:38 PM PDT 24
Peak memory 218804 kb
Host smart-32a288e6-5d30-4ff9-88e1-ae452de90910
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201950299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4201950299
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1612699056
Short name T18
Test name
Test status
Simulation time 45026788 ps
CPU time 1 seconds
Started Mar 31 02:44:31 PM PDT 24
Finished Mar 31 02:44:32 PM PDT 24
Peak memory 207076 kb
Host smart-fed74fb8-5852-432f-a32b-4b8013c9ebd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612699056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1612699056
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2673590983
Short name T435
Test name
Test status
Simulation time 718702924 ps
CPU time 2.72 seconds
Started Mar 31 02:44:31 PM PDT 24
Finished Mar 31 02:44:34 PM PDT 24
Peak memory 216376 kb
Host smart-34bdf1ae-5e00-4ef5-a943-d67937f4bae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673590983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2673590983
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3941725861
Short name T481
Test name
Test status
Simulation time 1028603197 ps
CPU time 5.75 seconds
Started Mar 31 02:44:26 PM PDT 24
Finished Mar 31 02:44:32 PM PDT 24
Peak memory 216164 kb
Host smart-ef7d54d5-8a75-4b76-aeab-9fc085fc7544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941725861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3941725861
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3594510252
Short name T12
Test name
Test status
Simulation time 1121810599 ps
CPU time 8.86 seconds
Started Mar 31 02:44:29 PM PDT 24
Finished Mar 31 02:44:38 PM PDT 24
Peak memory 216392 kb
Host smart-f0828f74-e304-4cf6-9505-626475e9bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594510252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3594510252
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2926414349
Short name T729
Test name
Test status
Simulation time 108206721 ps
CPU time 0.75 seconds
Started Mar 31 02:44:30 PM PDT 24
Finished Mar 31 02:44:31 PM PDT 24
Peak memory 205736 kb
Host smart-ed3bc1e7-1646-4804-b960-a7fb9a1573f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926414349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2926414349
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3297247977
Short name T296
Test name
Test status
Simulation time 3738182019 ps
CPU time 9.05 seconds
Started Mar 31 02:44:29 PM PDT 24
Finished Mar 31 02:44:38 PM PDT 24
Peak memory 224664 kb
Host smart-9441b01d-06f4-430b-bcfa-08ce35b6e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297247977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3297247977
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%