Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1309662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1440811

1

T1

1

T2

907

T3

934

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2076822	1			T1	1		T2	9		T3	97
values[0x0]	336133	1			T2	489		T3	464		T6	124
values[0x1]	337518	1			T2	413		T3	419		T6	125

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	983591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1766882

1

T1

1

T2

908

T3

944

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15762	1			T3	1		T6	3		T4	15
valid_sources[0x01]	10397	1			T3	3		T5	130		T7	131
valid_sources[0x02]	7889	1			T3	3		T6	1		T4	3
valid_sources[0x03]	10901	1			T3	1		T6	2		T5	162
valid_sources[0x04]	9570	1			T3	1		T5	137		T8	4
valid_sources[0x05]	13564	1			T3	3		T6	3		T5	141
valid_sources[0x06]	8448	1			T3	2		T6	1		T4	2
valid_sources[0x07]	8496	1			T3	6		T4	2		T16	2
valid_sources[0x08]	8287	1			T6	1		T16	2		T5	126
valid_sources[0x09]	8685	1			T3	4		T4	17		T5	158
valid_sources[0x0a]	7284	1			T3	4		T5	120		T8	6
valid_sources[0x0b]	8770	1			T3	1		T6	3		T5	129
valid_sources[0x0c]	7991	1			T3	3		T6	1		T4	4
valid_sources[0x0d]	9466	1			T6	4		T4	37		T5	132
valid_sources[0x0e]	8810	1			T3	4		T6	1		T5	157
valid_sources[0x0f]	10203	1			T3	6		T4	13		T5	146
valid_sources[0x10]	9263	1			T3	2		T6	2		T4	8
valid_sources[0x11]	9205	1			T3	4		T5	148		T15	50
valid_sources[0x12]	43237	1			T3	2		T16	1		T5	128
valid_sources[0x13]	9262	1			T3	5		T6	2		T4	2
valid_sources[0x14]	9746	1			T3	4		T6	3		T5	121
valid_sources[0x15]	10323	1			T3	10		T4	3		T5	188
valid_sources[0x16]	10538	1			T3	5		T5	132		T8	2
valid_sources[0x17]	8106	1			T3	2		T6	3		T5	138
valid_sources[0x18]	8463	1			T3	7		T5	140		T8	6
valid_sources[0x19]	10102	1			T3	3		T6	1		T5	129
valid_sources[0x1a]	7818	1			T3	5		T6	3		T5	130
valid_sources[0x1b]	7932	1			T3	4		T6	1		T16	1
valid_sources[0x1c]	9764	1			T3	6		T4	9		T5	131
valid_sources[0x1d]	7780	1			T3	3		T6	2		T5	146
valid_sources[0x1e]	8073	1			T3	3		T6	2		T5	176
valid_sources[0x1f]	13203	1			T3	3		T4	2		T5	154
valid_sources[0x20]	8285	1			T3	1		T4	8		T5	174
valid_sources[0x21]	7825	1			T3	6		T6	1		T5	156
valid_sources[0x22]	8239	1			T3	2		T6	1		T5	157
valid_sources[0x23]	10593	1			T3	7		T6	1		T16	2
valid_sources[0x24]	9254	1			T3	5		T6	1		T5	193
valid_sources[0x25]	8613	1			T3	1		T6	3		T4	1
valid_sources[0x26]	12700	1			T3	4		T6	3		T5	116
valid_sources[0x27]	8560	1			T3	1		T6	2		T4	1
valid_sources[0x28]	11409	1			T3	6		T6	2		T16	1
valid_sources[0x29]	7939	1			T3	1		T6	1		T5	132
valid_sources[0x2a]	9463	1			T3	1		T5	88		T7	451
valid_sources[0x2b]	8210	1			T3	2		T6	4		T4	6
valid_sources[0x2c]	9842	1			T3	6		T6	2		T5	148
valid_sources[0x2d]	12128	1			T3	5		T5	130		T7	323
valid_sources[0x2e]	9133	1			T3	6		T5	145		T8	1
valid_sources[0x2f]	10078	1			T3	2		T6	1		T4	20
valid_sources[0x30]	7794	1			T3	2		T6	2		T4	18
valid_sources[0x31]	8834	1			T3	4		T5	177		T8	7
valid_sources[0x32]	8598	1			T3	3		T6	1		T4	3
valid_sources[0x33]	21044	1			T3	5		T6	1		T4	22
valid_sources[0x34]	9246	1			T3	7		T5	135		T8	1
valid_sources[0x35]	7999	1			T3	4		T6	1		T4	10
valid_sources[0x36]	9890	1			T3	1		T6	3		T4	3
valid_sources[0x37]	11775	1			T3	6		T5	149		T8	2
valid_sources[0x38]	10575	1			T3	4		T6	3		T5	133
valid_sources[0x39]	11279	1			T3	6		T5	165		T8	4
valid_sources[0x3a]	8778	1			T3	3		T6	2		T4	63
valid_sources[0x3b]	8691	1			T3	2		T5	137		T8	9
valid_sources[0x3c]	9498	1			T3	10		T5	148		T8	5
valid_sources[0x3d]	8816	1			T3	2		T4	1		T5	127
valid_sources[0x3e]	12786	1			T3	5		T6	1		T4	6
valid_sources[0x3f]	8680	1			T3	2		T6	2		T5	120
valid_sources[0x40]	15822	1			T3	4		T5	152		T8	1
valid_sources[0x41]	8344	1			T3	1		T4	25		T5	148
valid_sources[0x42]	63044	1			T3	2		T4	12		T5	158
valid_sources[0x43]	9457	1			T3	1		T6	2		T4	13
valid_sources[0x44]	9083	1			T3	5		T6	1		T4	7
valid_sources[0x45]	8358	1			T3	2		T5	137		T8	1
valid_sources[0x46]	14118	1			T3	11		T6	1		T5	128
valid_sources[0x47]	15752	1			T3	3		T6	2		T4	2
valid_sources[0x48]	22216	1			T3	1		T5	135		T7	188
valid_sources[0x49]	11504	1			T3	4		T4	43		T5	140
valid_sources[0x4a]	11766	1			T3	5		T6	1		T4	29
valid_sources[0x4b]	10329	1			T3	5		T6	2		T4	9
valid_sources[0x4c]	9412	1			T3	4		T6	1		T5	106
valid_sources[0x4d]	8594	1			T3	2		T4	9		T5	139
valid_sources[0x4e]	8456	1			T3	10		T6	3		T4	12
valid_sources[0x4f]	7789	1			T3	4		T6	1		T4	22
valid_sources[0x50]	26618	1			T3	2		T4	13		T16	2
valid_sources[0x51]	7584	1			T3	5		T5	156		T8	6
valid_sources[0x52]	10109	1			T3	3		T6	1		T4	7
valid_sources[0x53]	8706	1			T3	3		T4	1		T5	178
valid_sources[0x54]	9616	1			T3	12		T5	164		T8	6
valid_sources[0x55]	9478	1			T3	3		T6	1		T4	2
valid_sources[0x56]	8852	1			T3	5		T5	125		T8	2
valid_sources[0x57]	8250	1			T3	7		T6	3		T4	1
valid_sources[0x58]	10126	1			T3	2		T6	2		T5	128
valid_sources[0x59]	10394	1			T3	4		T5	152		T8	9
valid_sources[0x5a]	7983	1			T3	3		T6	2		T4	3
valid_sources[0x5b]	10013	1			T3	5		T4	10		T5	137
valid_sources[0x5c]	8591	1			T5	164		T8	4		T15	81
valid_sources[0x5d]	8995	1			T3	8		T4	11		T16	1
valid_sources[0x5e]	8276	1			T3	4		T6	1		T4	6
valid_sources[0x5f]	8683	1			T3	3		T5	138		T8	4
valid_sources[0x60]	9691	1			T3	6		T4	2		T16	2
valid_sources[0x61]	11563	1			T2	460		T3	2		T5	120
valid_sources[0x62]	10158	1			T3	2		T4	7		T5	146
valid_sources[0x63]	8606	1			T3	3		T5	139		T8	3
valid_sources[0x64]	8583	1			T3	1		T4	7		T5	147
valid_sources[0x65]	8618	1			T3	4		T4	10		T5	158
valid_sources[0x66]	9083	1			T3	4		T6	3		T16	2
valid_sources[0x67]	9584	1			T3	3		T6	1		T5	126
valid_sources[0x68]	8055	1			T6	1		T5	117		T8	1
valid_sources[0x69]	9965	1			T3	3		T6	1		T4	7
valid_sources[0x6a]	7860	1			T3	5		T6	3		T5	125
valid_sources[0x6b]	10097	1			T3	1		T6	1		T4	1
valid_sources[0x6c]	8051	1			T3	5		T6	1		T4	2
valid_sources[0x6d]	9559	1			T3	4		T6	1		T5	111
valid_sources[0x6e]	9366	1			T3	2		T16	1		T5	141
valid_sources[0x6f]	13062	1			T2	451		T3	3		T6	1
valid_sources[0x70]	9672	1			T3	3		T6	1		T4	1
valid_sources[0x71]	9146	1			T3	2		T4	11		T5	161
valid_sources[0x72]	8335	1			T3	6		T6	1		T5	153
valid_sources[0x73]	10249	1			T3	4		T5	138		T8	3
valid_sources[0x74]	14908	1			T3	5		T6	1		T4	17
valid_sources[0x75]	8808	1			T3	9		T6	1		T4	53
valid_sources[0x76]	8236	1			T3	1		T6	1		T4	11
valid_sources[0x77]	10136	1			T3	6		T4	49		T5	122
valid_sources[0x78]	7736	1			T3	1		T4	1		T5	128
valid_sources[0x79]	22413	1			T3	6		T5	123		T8	2
valid_sources[0x7a]	11545	1			T3	1		T6	3		T5	156
valid_sources[0x7b]	9167	1			T3	2		T5	114		T8	12
valid_sources[0x7c]	9312	1			T3	4		T6	1		T5	155
valid_sources[0x7d]	9444	1			T3	2		T16	1		T5	119
valid_sources[0x7e]	8376	1			T3	1		T5	138		T8	3
valid_sources[0x7f]	9759	1			T3	4		T5	159		T8	14
valid_sources[0x80]	10686	1			T3	5		T5	141		T8	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

832065

1

T1

1

T2

7

T3

53

values[0x0]

all_enables

biggest_size

307580

1

T2

488

T3

463

T6

102

values[0x1]

all_enables

biggest_size

301166

1

T2

412

T3

418

T6

105