Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1334020

1

T2

4

T3

46

T6

43

full_word

1440200

1

T1

1

T2

907

T3

934

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2773790	1			T1	1		T2	911		T3	980
auto[TlIntgErrCmd]	150	1			T121	1		T122	7		T364	5
auto[TlIntgErrData]	144	1			T35	4		T121	2		T122	12
auto[TlIntgErrBoth]	136	1			T35	6		T121	7		T122	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2078918

1

T1

1

T2

9

T3

97

auto[1]

695302

1

T2

902

T3

883

T6

249

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1246500	1			T2	2		T3	44		T6	1
auto[TlIntgErrNone]	partial	auto[1]	87129	1			T2	2		T3	2		T6	42
auto[TlIntgErrNone]	full_word	auto[0]	832225	1			T1	1		T2	7		T3	53
auto[TlIntgErrNone]	full_word	auto[1]	607936	1			T2	900		T3	881		T6	207
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T122	2		T157	4		T368	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T121	1		T122	4		T364	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T122	1		T368	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T159	2		T369	1		T370	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T35	3		T121	2		T122	5
auto[TlIntgErrData]	partial	auto[1]	61	1			T35	1		T122	6		T364	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T122	1		T172	2		T369	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T368	1		T131	1		T371	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T35	2		T121	1		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	78	1			T35	4		T121	6		T122	7
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T122	1		T368	1		T159	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T368	1		T131	1		T369	1