Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	100.00	70.37			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	55.51	86.36	44.44			60.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
55.51	86.36

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T17
1	0	Covered	T15,T17,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T13,T14
1	0	Unreachable
1	1	Covered	T14,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
55.51	44.44

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T17,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T17
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	188621531	151007471	0	0
CheckNGreaterZero_A	2085	2085	0	0
GntImpliesReady_A	188621531	684291	0	0
GntImpliesValid_A	188621531	684291	0	0
GrantKnown_A	188621531	151007471	0	0
IdxKnown_A	188621531	151007471	0	0
IndexIsCorrect_A	188621531	684291	0	0
LockArbDecision_A	188621531	0	0	0
NoReadyValidNoGrant_A	188621531	0	0	0
ReadyAndValidImplyGrant_A	188621531	684291	0	0
ReqAndReadyImplyGrant_A	188621531	684291	0	0
ReqImpliesValid_A	188621531	684291	0	0
ReqStaysHighUntilGranted0_M	188621531	0	0	0
RoundRobin_A	188621531	0	0	695
ValidKnown_A	188621531	151007471	0	0
gen_data_port_assertion.DataFlow_A	188621531	684291	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	151007471	0	0
T1	4762	3924	0	0
T2	276924	276272	0	0
T3	19311	19221	0	0
T4	47343	34624	0	0
T5	1092694	957321	0	0
T6	199454	114443	0	0
T7	511819	286399	0	0
T8	62188	41772	0	0
T9	17016	17016	0	0
T10	18006	18006	0	0
T11	0	20758	0	0
T13	6200	5233	0	0
T14	1088	544	0	0
T15	310220	146944	0	0
T16	1044	993	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2085	2085	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T13	3	3	0	0
T16	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	151007471	0	0
T1	4762	3924	0	0
T2	276924	276272	0	0
T3	19311	19221	0	0
T4	47343	34624	0	0
T5	1092694	957321	0	0
T6	199454	114443	0	0
T7	511819	286399	0	0
T8	62188	41772	0	0
T9	17016	17016	0	0
T10	18006	18006	0	0
T11	0	20758	0	0
T13	6200	5233	0	0
T14	1088	544	0	0
T15	310220	146944	0	0
T16	1044	993	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	151007471	0	0
T1	4762	3924	0	0
T2	276924	276272	0	0
T3	19311	19221	0	0
T4	47343	34624	0	0
T5	1092694	957321	0	0
T6	199454	114443	0	0
T7	511819	286399	0	0
T8	62188	41772	0	0
T9	17016	17016	0	0
T10	18006	18006	0	0
T11	0	20758	0	0
T13	6200	5233	0	0
T14	1088	544	0	0
T15	310220	146944	0	0
T16	1044	993	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	0	0	695

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	151007471	0	0
T1	4762	3924	0	0
T2	276924	276272	0	0
T3	19311	19221	0	0
T4	47343	34624	0	0
T5	1092694	957321	0	0
T6	199454	114443	0	0
T7	511819	286399	0	0
T8	62188	41772	0	0
T9	17016	17016	0	0
T10	18006	18006	0	0
T11	0	20758	0	0
T13	6200	5233	0	0
T14	1088	544	0	0
T15	310220	146944	0	0
T16	1044	993	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188621531	684291	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	17016	832	0	0
T10	18006	832	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T13	4826	0	0	0
T14	5269	74	0	0
T15	155110	10334	0	0
T16	1044	0	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	19	86.36
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	3	75.00
ALWAYS	124	4	3	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	0	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	1	50.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	36998022	23384503	0	0
CheckNGreaterZero_A	695	695	0	0
GntImpliesReady_A	36998022	0	0	0
GntImpliesValid_A	36998022	0	0	0
GrantKnown_A	36998022	23384503	0	0
IdxKnown_A	36998022	23384503	0	0
IndexIsCorrect_A	36998022	0	0	0
LockArbDecision_A	36998022	0	0	0
NoReadyValidNoGrant_A	36998022	0	0	0
ReadyAndValidImplyGrant_A	36998022	0	0	0
ReqAndReadyImplyGrant_A	36998022	0	0	0
ReqImpliesValid_A	36998022	0	0	0
ReqStaysHighUntilGranted0_M	36998022	0	0	0
RoundRobin_A	36998022	0	0	0
ValidKnown_A	36998022	23384503	0	0
gen_data_port_assertion.DataFlow_A	36998022	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	23384503	0	0
T2	135436	134838	0	0
T3	12320	12320	0	0
T4	12648	12648	0	0
T5	135079	134856	0	0
T6	80774	0	0	0
T7	225050	224774	0	0
T8	20364	20364	0	0
T9	0	17016	0	0
T10	0	18006	0	0
T11	0	20758	0	0
T12	0	248014	0	0
T13	687	0	0	0
T14	544	0	0	0
T15	155110	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695	695	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	23384503	0	0
T2	135436	134838	0	0
T3	12320	12320	0	0
T4	12648	12648	0	0
T5	135079	134856	0	0
T6	80774	0	0	0
T7	225050	224774	0	0
T8	20364	20364	0	0
T9	0	17016	0	0
T10	0	18006	0	0
T11	0	20758	0	0
T12	0	248014	0	0
T13	687	0	0	0
T14	544	0	0	0
T15	155110	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	23384503	0	0
T2	135436	134838	0	0
T3	12320	12320	0	0
T4	12648	12648	0	0
T5	135079	134856	0	0
T6	80774	0	0	0
T7	225050	224774	0	0
T8	20364	20364	0	0
T9	0	17016	0	0
T10	0	18006	0	0
T11	0	20758	0	0
T12	0	248014	0	0
T13	687	0	0	0
T14	544	0	0	0
T15	155110	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	23384503	0	0
T2	135436	134838	0	0
T3	12320	12320	0	0
T4	12648	12648	0	0
T5	135079	134856	0	0
T6	80774	0	0	0
T7	225050	224774	0	0
T8	20364	20364	0	0
T9	0	17016	0	0
T10	0	18006	0	0
T11	0	20758	0	0
T12	0	248014	0	0
T13	687	0	0	0
T14	544	0	0	0
T15	155110	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T17
1	0	Covered	T15,T17,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T13,T14
1	0	Unreachable
1	1	Covered	T14,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T14,T15,T17
0	0	1	Unreachable
0	0	0	Covered	T6,T13,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	36998022	13059711	0	0
CheckNGreaterZero_A	695	695	0	0
GntImpliesReady_A	36998022	229127	0	0
GntImpliesValid_A	36998022	229127	0	0
GrantKnown_A	36998022	13059711	0	0
IdxKnown_A	36998022	13059711	0	0
IndexIsCorrect_A	36998022	229127	0	0
LockArbDecision_A	36998022	0	0	0
NoReadyValidNoGrant_A	36998022	0	0	0
ReadyAndValidImplyGrant_A	36998022	229127	0	0
ReqAndReadyImplyGrant_A	36998022	229127	0	0
ReqImpliesValid_A	36998022	229127	0	0
ReqStaysHighUntilGranted0_M	36998022	0	0	0
RoundRobin_A	36998022	0	0	0
ValidKnown_A	36998022	13059711	0	0
gen_data_port_assertion.DataFlow_A	36998022	229127	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	13059711	0	0
T4	12648	0	0	0
T5	135079	0	0	0
T6	80774	76616	0	0
T7	225050	0	0	0
T8	20364	0	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T13	687	504	0	0
T14	544	544	0	0
T15	155110	146944	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695	695	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	13059711	0	0
T4	12648	0	0	0
T5	135079	0	0	0
T6	80774	76616	0	0
T7	225050	0	0	0
T8	20364	0	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T13	687	504	0	0
T14	544	544	0	0
T15	155110	146944	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	13059711	0	0
T4	12648	0	0	0
T5	135079	0	0	0
T6	80774	76616	0	0
T7	225050	0	0	0
T8	20364	0	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T13	687	504	0	0
T14	544	544	0	0
T15	155110	146944	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	13059711	0	0
T4	12648	0	0	0
T5	135079	0	0	0
T6	80774	76616	0	0
T7	225050	0	0	0
T8	20364	0	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T13	687	504	0	0
T14	544	544	0	0
T15	155110	146944	0	0
T17	0	5520	0	0
T18	0	56720	0	0
T20	0	288	0	0
T52	0	3776	0	0
T53	0	14480	0	0
T54	0	109560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36998022	229127	0	0
T9	17016	0	0	0
T10	18006	0	0	0
T11	20758	0	0	0
T12	249404	0	0	0
T14	544	58	0	0
T15	155110	6911	0	0
T17	0	366	0	0
T18	0	2250	0	0
T44	41904	0	0	0
T52	0	306	0	0
T53	0	492	0	0
T54	0	4899	0	0
T55	0	7565	0	0
T56	0	7074	0	0
T57	4208	0	0	0
T58	63946	0	0	0
T59	0	6019	0	0
T61	143031	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T17,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T17
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	114625487	114563257	0	0
CheckNGreaterZero_A	695	695	0	0
GntImpliesReady_A	114625487	455164	0	0
GntImpliesValid_A	114625487	455164	0	0
GrantKnown_A	114625487	114563257	0	0
IdxKnown_A	114625487	114563257	0	0
IndexIsCorrect_A	114625487	455164	0	0
LockArbDecision_A	114625487	0	0	0
NoReadyValidNoGrant_A	114625487	0	0	0
ReadyAndValidImplyGrant_A	114625487	455164	0	0
ReqAndReadyImplyGrant_A	114625487	455164	0	0
ReqImpliesValid_A	114625487	455164	0	0
ReqStaysHighUntilGranted0_M	114625487	0	0	0
RoundRobin_A	114625487	0	0	695
ValidKnown_A	114625487	114563257	0	0
gen_data_port_assertion.DataFlow_A	114625487	455164	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	114563257	0	0
T1	4762	3924	0	0
T2	141488	141434	0	0
T3	6991	6901	0	0
T4	22047	21976	0	0
T5	822536	822465	0	0
T6	37906	37827	0	0
T7	61719	61625	0	0
T8	21460	21408	0	0
T13	4826	4729	0	0
T16	1044	993	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695	695	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	114563257	0	0
T1	4762	3924	0	0
T2	141488	141434	0	0
T3	6991	6901	0	0
T4	22047	21976	0	0
T5	822536	822465	0	0
T6	37906	37827	0	0
T7	61719	61625	0	0
T8	21460	21408	0	0
T13	4826	4729	0	0
T16	1044	993	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	114563257	0	0
T1	4762	3924	0	0
T2	141488	141434	0	0
T3	6991	6901	0	0
T4	22047	21976	0	0
T5	822536	822465	0	0
T6	37906	37827	0	0
T7	61719	61625	0	0
T8	21460	21408	0	0
T13	4826	4729	0	0
T16	1044	993	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	0	0	695

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	114563257	0	0
T1	4762	3924	0	0
T2	141488	141434	0	0
T3	6991	6901	0	0
T4	22047	21976	0	0
T5	822536	822465	0	0
T6	37906	37827	0	0
T7	61719	61625	0	0
T8	21460	21408	0	0
T13	4826	4729	0	0
T16	1044	993	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114625487	455164	0	0
T2	141488	832	0	0
T3	6991	832	0	0
T4	22047	832	0	0
T5	822536	832	0	0
T6	37906	0	0	0
T7	61719	1600	0	0
T8	21460	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	4826	0	0	0
T14	4725	16	0	0
T15	0	3423	0	0
T16	1044	0	0	0