Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.05 97.56 92.93 98.61 80.85 95.95 90.92 87.54


Total test records in report: 870
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T368 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.370161276 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:52 PM PDT 24 878288540 ps
T770 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2940979357 Apr 02 12:29:43 PM PDT 24 Apr 02 12:29:44 PM PDT 24 17912801 ps
T771 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1664673969 Apr 02 12:29:43 PM PDT 24 Apr 02 12:29:46 PM PDT 24 26393743 ps
T772 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1619602920 Apr 02 12:29:20 PM PDT 24 Apr 02 12:29:21 PM PDT 24 28701308 ps
T159 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3169317605 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:58 PM PDT 24 3943837984 ps
T773 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.694858870 Apr 02 12:29:32 PM PDT 24 Apr 02 12:29:32 PM PDT 24 10745165 ps
T774 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1293121659 Apr 02 12:29:31 PM PDT 24 Apr 02 12:29:32 PM PDT 24 21181950 ps
T775 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1975488600 Apr 02 12:29:34 PM PDT 24 Apr 02 12:29:35 PM PDT 24 16685699 ps
T776 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3911823327 Apr 02 12:30:01 PM PDT 24 Apr 02 12:30:01 PM PDT 24 50682625 ps
T777 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3101158061 Apr 02 12:29:42 PM PDT 24 Apr 02 12:29:43 PM PDT 24 21700351 ps
T778 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.332650067 Apr 02 12:29:41 PM PDT 24 Apr 02 12:29:47 PM PDT 24 19434886 ps
T144 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3422384798 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:37 PM PDT 24 608645601 ps
T779 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3175404735 Apr 02 12:29:44 PM PDT 24 Apr 02 12:29:45 PM PDT 24 16790996 ps
T780 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3449197702 Apr 02 12:29:41 PM PDT 24 Apr 02 12:29:45 PM PDT 24 194451439 ps
T781 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3844236509 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:41 PM PDT 24 40611942 ps
T782 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.958432984 Apr 02 12:28:57 PM PDT 24 Apr 02 12:29:12 PM PDT 24 1208922312 ps
T783 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.447910670 Apr 02 12:29:41 PM PDT 24 Apr 02 12:29:42 PM PDT 24 22916142 ps
T172 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4269337436 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:45 PM PDT 24 311224116 ps
T131 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2041958182 Apr 02 12:29:30 PM PDT 24 Apr 02 12:29:48 PM PDT 24 1201715907 ps
T784 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.74465781 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:29 PM PDT 24 13864029 ps
T145 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1447073908 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:37 PM PDT 24 166169809 ps
T100 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1989565089 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:22 PM PDT 24 20018179 ps
T369 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2847595151 Apr 02 12:29:32 PM PDT 24 Apr 02 12:29:49 PM PDT 24 594565511 ps
T371 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.991219724 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:33 PM PDT 24 1188689125 ps
T785 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4150695962 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:29 PM PDT 24 12124381 ps
T146 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1408987483 Apr 02 12:29:22 PM PDT 24 Apr 02 12:29:23 PM PDT 24 18346043 ps
T786 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.483086924 Apr 02 12:29:41 PM PDT 24 Apr 02 12:29:54 PM PDT 24 88242104 ps
T787 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.154854171 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:39 PM PDT 24 46299805 ps
T147 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1621152181 Apr 02 12:29:28 PM PDT 24 Apr 02 12:29:29 PM PDT 24 18775080 ps
T788 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2157177017 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:28 PM PDT 24 47168964 ps
T789 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4191525284 Apr 02 12:28:56 PM PDT 24 Apr 02 12:28:58 PM PDT 24 219666213 ps
T790 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3794377162 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:36 PM PDT 24 14293755 ps
T791 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1881566593 Apr 02 12:29:27 PM PDT 24 Apr 02 12:29:32 PM PDT 24 3051554365 ps
T132 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3335876446 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:35 PM PDT 24 319399441 ps
T792 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1735744900 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:26 PM PDT 24 213922702 ps
T793 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.124495373 Apr 02 12:29:27 PM PDT 24 Apr 02 12:29:29 PM PDT 24 66589259 ps
T794 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1565844015 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:29 PM PDT 24 13593044 ps
T370 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3112100225 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:53 PM PDT 24 549650548 ps
T795 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.97700228 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:40 PM PDT 24 25900275 ps
T796 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3303601090 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:42 PM PDT 24 104759725 ps
T797 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.547381362 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:51 PM PDT 24 1419402530 ps
T798 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4198092379 Apr 02 12:28:59 PM PDT 24 Apr 02 12:29:02 PM PDT 24 172031439 ps
T799 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1515994353 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:45 PM PDT 24 787444369 ps
T800 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1811810673 Apr 02 12:29:20 PM PDT 24 Apr 02 12:29:23 PM PDT 24 120202893 ps
T801 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3489317987 Apr 02 12:29:09 PM PDT 24 Apr 02 12:29:12 PM PDT 24 66508551 ps
T802 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1343150348 Apr 02 12:29:37 PM PDT 24 Apr 02 12:29:41 PM PDT 24 776684934 ps
T803 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.477514710 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:36 PM PDT 24 42002925 ps
T804 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1042348704 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:59 PM PDT 24 49006371 ps
T805 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3699754505 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:42 PM PDT 24 187470956 ps
T806 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3651661881 Apr 02 12:29:34 PM PDT 24 Apr 02 12:29:38 PM PDT 24 544310580 ps
T148 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.492579209 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:31 PM PDT 24 214580764 ps
T807 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.727535808 Apr 02 12:29:41 PM PDT 24 Apr 02 12:29:42 PM PDT 24 18077196 ps
T808 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3859723239 Apr 02 12:29:31 PM PDT 24 Apr 02 12:29:35 PM PDT 24 647065054 ps
T809 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.55046932 Apr 02 12:28:57 PM PDT 24 Apr 02 12:29:01 PM PDT 24 215229106 ps
T810 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2233603915 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:58 PM PDT 24 1046429469 ps
T811 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1403761081 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:46 PM PDT 24 439281227 ps
T812 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1859135465 Apr 02 12:29:33 PM PDT 24 Apr 02 12:29:34 PM PDT 24 163238794 ps
T813 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.844445775 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:49 PM PDT 24 405301096 ps
T814 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1044062471 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:39 PM PDT 24 68538105 ps
T815 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2759336617 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:41 PM PDT 24 130087115 ps
T101 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3278786707 Apr 02 12:29:04 PM PDT 24 Apr 02 12:29:05 PM PDT 24 171966864 ps
T816 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1921822583 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:28 PM PDT 24 38568680 ps
T817 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1964485351 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:41 PM PDT 24 59105045 ps
T818 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2884036681 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:40 PM PDT 24 137324960 ps
T819 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2010165026 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:28 PM PDT 24 862776131 ps
T820 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.375993220 Apr 02 12:29:43 PM PDT 24 Apr 02 12:29:44 PM PDT 24 33165298 ps
T821 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2958499125 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:44 PM PDT 24 40001860 ps
T822 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1829405150 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:40 PM PDT 24 53966057 ps
T823 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.350580602 Apr 02 12:29:31 PM PDT 24 Apr 02 12:29:31 PM PDT 24 19627696 ps
T102 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3730801398 Apr 02 12:29:22 PM PDT 24 Apr 02 12:29:23 PM PDT 24 15170836 ps
T824 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2424927253 Apr 02 12:29:32 PM PDT 24 Apr 02 12:29:35 PM PDT 24 867235788 ps
T825 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.25585646 Apr 02 12:29:37 PM PDT 24 Apr 02 12:29:50 PM PDT 24 1277595837 ps
T826 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1962551374 Apr 02 12:29:31 PM PDT 24 Apr 02 12:29:32 PM PDT 24 24899566 ps
T827 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.573103368 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:17 PM PDT 24 104443834 ps
T828 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2423101630 Apr 02 12:29:44 PM PDT 24 Apr 02 12:29:46 PM PDT 24 14023266 ps
T829 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4175291126 Apr 02 12:29:31 PM PDT 24 Apr 02 12:29:33 PM PDT 24 89468641 ps
T365 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.149182883 Apr 02 12:29:33 PM PDT 24 Apr 02 12:29:52 PM PDT 24 337720023 ps
T830 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.386246426 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:26 PM PDT 24 152856233 ps
T831 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1930723315 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:38 PM PDT 24 56090797 ps
T366 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.947048980 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:55 PM PDT 24 305176616 ps
T832 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3012931555 Apr 02 12:29:43 PM PDT 24 Apr 02 12:29:45 PM PDT 24 25122497 ps
T367 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4205678193 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:53 PM PDT 24 200627732 ps
T833 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3611614740 Apr 02 12:29:42 PM PDT 24 Apr 02 12:29:59 PM PDT 24 294058720 ps
T834 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2309736779 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:29 PM PDT 24 118703890 ps
T835 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.295189860 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:38 PM PDT 24 1586387798 ps
T836 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2023909003 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:16 PM PDT 24 24409094 ps
T837 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1561092448 Apr 02 12:29:32 PM PDT 24 Apr 02 12:29:37 PM PDT 24 160275016 ps
T838 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.727925772 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:23 PM PDT 24 98147257 ps
T839 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.965311287 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:39 PM PDT 24 16329229 ps
T840 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4269908928 Apr 02 12:29:33 PM PDT 24 Apr 02 12:29:34 PM PDT 24 57860941 ps
T841 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2722523676 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:51 PM PDT 24 575179742 ps
T842 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.199758807 Apr 02 12:29:32 PM PDT 24 Apr 02 12:29:35 PM PDT 24 435930268 ps
T843 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.65055359 Apr 02 12:29:16 PM PDT 24 Apr 02 12:29:18 PM PDT 24 76444884 ps
T844 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.562569937 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:37 PM PDT 24 19674063 ps
T845 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4092450397 Apr 02 12:29:40 PM PDT 24 Apr 02 12:29:44 PM PDT 24 55763332 ps
T846 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1557383020 Apr 02 12:29:27 PM PDT 24 Apr 02 12:29:29 PM PDT 24 99312288 ps
T847 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.279865136 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:28 PM PDT 24 86547693 ps
T848 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2964717206 Apr 02 12:29:22 PM PDT 24 Apr 02 12:29:56 PM PDT 24 3615101243 ps
T849 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3934569115 Apr 02 12:29:27 PM PDT 24 Apr 02 12:29:31 PM PDT 24 41699599 ps
T850 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.721928419 Apr 02 12:29:30 PM PDT 24 Apr 02 12:29:32 PM PDT 24 191553991 ps
T851 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1710522583 Apr 02 12:29:18 PM PDT 24 Apr 02 12:29:19 PM PDT 24 57774514 ps
T852 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3857923373 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:41 PM PDT 24 170690843 ps
T853 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.935370273 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:18 PM PDT 24 38065747 ps
T854 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.750965758 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:33 PM PDT 24 311589664 ps
T855 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3622044373 Apr 02 12:29:22 PM PDT 24 Apr 02 12:29:22 PM PDT 24 39069265 ps
T856 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3890804089 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:24 PM PDT 24 15236623 ps
T857 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4202243819 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:25 PM PDT 24 53998144 ps
T858 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2257369724 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:36 PM PDT 24 20265047 ps
T859 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2045700760 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:41 PM PDT 24 450330736 ps
T860 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2233922051 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:22 PM PDT 24 13322965 ps
T861 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4065112488 Apr 02 12:28:52 PM PDT 24 Apr 02 12:29:17 PM PDT 24 1361487651 ps
T862 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1034020694 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:39 PM PDT 24 13826473 ps
T863 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3458717988 Apr 02 12:29:29 PM PDT 24 Apr 02 12:29:31 PM PDT 24 25517257 ps
T864 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2382325613 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:36 PM PDT 24 13396861 ps
T865 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.416586713 Apr 02 12:29:36 PM PDT 24 Apr 02 12:29:38 PM PDT 24 38748808 ps
T866 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3982600962 Apr 02 12:29:42 PM PDT 24 Apr 02 12:29:43 PM PDT 24 13300477 ps
T867 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3201445109 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 11363761 ps
T868 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.240360908 Apr 02 12:29:28 PM PDT 24 Apr 02 12:29:33 PM PDT 24 352881465 ps
T869 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1519988522 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:57 PM PDT 24 636242693 ps
T870 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3023248582 Apr 02 12:29:39 PM PDT 24 Apr 02 12:29:40 PM PDT 24 14115330 ps

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3664429268
Short name T4
Test name
Test status
Simulation time 848038328 ps
CPU time 3.79 seconds
Started Apr 02 02:08:34 PM PDT 24
Finished Apr 02 02:08:38 PM PDT 24
Peak memory 219836 kb
Host smart-89172b19-3865-4e15-ad5c-70e3a0c91719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3664429268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3664429268
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.748089256
Short name T54
Test name
Test status
Simulation time 44796886879 ps
CPU time 42.99 seconds
Started Apr 02 02:05:23 PM PDT 24
Finished Apr 02 02:06:07 PM PDT 24
Peak memory 216444 kb
Host smart-9477c0b6-f8c6-4d00-ae58-60d9354010ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748089256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.748089256
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1103827506
Short name T12
Test name
Test status
Simulation time 10124061250 ps
CPU time 20.34 seconds
Started Apr 02 02:10:22 PM PDT 24
Finished Apr 02 02:10:43 PM PDT 24
Peak memory 224596 kb
Host smart-57553506-8305-4475-8f44-5bef2883431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103827506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1103827506
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1062112774
Short name T15
Test name
Test status
Simulation time 60280280292 ps
CPU time 60.85 seconds
Started Apr 02 02:02:38 PM PDT 24
Finished Apr 02 02:03:39 PM PDT 24
Peak memory 216432 kb
Host smart-2108054c-2f5f-42a0-9361-c683525fbcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062112774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1062112774
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2697148521
Short name T118
Test name
Test status
Simulation time 3586708870 ps
CPU time 17.89 seconds
Started Apr 02 02:09:38 PM PDT 24
Finished Apr 02 02:09:57 PM PDT 24
Peak memory 224316 kb
Host smart-41263a5e-6865-4eb7-a03b-306a11a8486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697148521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2697148521
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2441788916
Short name T122
Test name
Test status
Simulation time 4092441433 ps
CPU time 22.36 seconds
Started Apr 02 12:29:28 PM PDT 24
Finished Apr 02 12:29:51 PM PDT 24
Peak memory 215608 kb
Host smart-59c62673-9d93-466b-92c1-eb445300b6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441788916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2441788916
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2093102679
Short name T22
Test name
Test status
Simulation time 2982241071 ps
CPU time 14.17 seconds
Started Apr 02 02:08:16 PM PDT 24
Finished Apr 02 02:08:31 PM PDT 24
Peak memory 218804 kb
Host smart-66730031-f7b8-43aa-8c5a-70ecf1d8f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093102679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2093102679
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3878205899
Short name T363
Test name
Test status
Simulation time 212676724 ps
CPU time 1.04 seconds
Started Apr 02 02:07:06 PM PDT 24
Finished Apr 02 02:07:07 PM PDT 24
Peak memory 206980 kb
Host smart-5effd929-6097-4ae2-9b22-7369560f0649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878205899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3878205899
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1479003788
Short name T178
Test name
Test status
Simulation time 5459650717 ps
CPU time 17.84 seconds
Started Apr 02 02:07:19 PM PDT 24
Finished Apr 02 02:07:37 PM PDT 24
Peak memory 237848 kb
Host smart-d7399626-b616-4e6a-9591-551ce5c3f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479003788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1479003788
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1082625489
Short name T42
Test name
Test status
Simulation time 27147911 ps
CPU time 0.76 seconds
Started Apr 02 02:03:02 PM PDT 24
Finished Apr 02 02:03:03 PM PDT 24
Peak memory 216272 kb
Host smart-96d2f2ab-b7d5-4b99-bb31-68086b08512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082625489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1082625489
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3746231649
Short name T59
Test name
Test status
Simulation time 2602184841 ps
CPU time 28.05 seconds
Started Apr 02 02:06:25 PM PDT 24
Finished Apr 02 02:06:53 PM PDT 24
Peak memory 216500 kb
Host smart-ab7dd6f1-3cd0-4e05-a7a3-e43901be85eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746231649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3746231649
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3793890184
Short name T91
Test name
Test status
Simulation time 247886355 ps
CPU time 5.13 seconds
Started Apr 02 02:10:08 PM PDT 24
Finished Apr 02 02:10:13 PM PDT 24
Peak memory 223360 kb
Host smart-062b0a3c-29a8-4575-9f9d-1fcf23e74bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793890184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3793890184
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3049100350
Short name T395
Test name
Test status
Simulation time 13504856102 ps
CPU time 35.24 seconds
Started Apr 02 02:09:58 PM PDT 24
Finished Apr 02 02:10:33 PM PDT 24
Peak memory 216456 kb
Host smart-17fd67b4-6be5-427a-b8da-b819784732f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049100350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3049100350
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2485766190
Short name T318
Test name
Test status
Simulation time 338219815 ps
CPU time 4.45 seconds
Started Apr 02 02:03:24 PM PDT 24
Finished Apr 02 02:03:29 PM PDT 24
Peak memory 223024 kb
Host smart-90da6abd-4511-4a74-9160-580e44d37251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485766190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2485766190
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1092239897
Short name T66
Test name
Test status
Simulation time 14069112297 ps
CPU time 18.76 seconds
Started Apr 02 02:03:35 PM PDT 24
Finished Apr 02 02:03:54 PM PDT 24
Peak memory 238408 kb
Host smart-413afe8d-ddfd-465d-9784-85cdfced220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092239897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1092239897
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1896065839
Short name T126
Test name
Test status
Simulation time 533618711 ps
CPU time 5.82 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 215752 kb
Host smart-ce3cc16f-78f6-40f6-8f24-669fc2420888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896065839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
896065839
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2355957523
Short name T1
Test name
Test status
Simulation time 49633249 ps
CPU time 0.96 seconds
Started Apr 02 02:02:53 PM PDT 24
Finished Apr 02 02:02:54 PM PDT 24
Peak memory 235372 kb
Host smart-0ea0e25b-4f08-4e82-b291-b2a9259d3599
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355957523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2355957523
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2337470226
Short name T63
Test name
Test status
Simulation time 14426893370 ps
CPU time 35.66 seconds
Started Apr 02 02:09:37 PM PDT 24
Finished Apr 02 02:10:13 PM PDT 24
Peak memory 232888 kb
Host smart-dbbfcdc1-d681-44b8-a668-a603d8a15aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337470226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2337470226
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.234610232
Short name T227
Test name
Test status
Simulation time 746813741 ps
CPU time 15.66 seconds
Started Apr 02 02:03:47 PM PDT 24
Finished Apr 02 02:04:03 PM PDT 24
Peak memory 238152 kb
Host smart-8486f538-a172-4d5d-9619-1643662dc247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234610232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.234610232
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3947437228
Short name T78
Test name
Test status
Simulation time 1073157282 ps
CPU time 18.82 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:09:10 PM PDT 24
Peak memory 224556 kb
Host smart-ff476e46-e902-4463-8f39-b419d151b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947437228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3947437228
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_upload.111931929
Short name T25
Test name
Test status
Simulation time 14196220903 ps
CPU time 43.4 seconds
Started Apr 02 02:11:00 PM PDT 24
Finished Apr 02 02:11:43 PM PDT 24
Peak memory 224776 kb
Host smart-4947ab60-3257-47b4-92d6-a75aa3cf28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111931929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.111931929
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1196443208
Short name T139
Test name
Test status
Simulation time 405757391 ps
CPU time 2.53 seconds
Started Apr 02 12:29:16 PM PDT 24
Finished Apr 02 12:29:19 PM PDT 24
Peak memory 215480 kb
Host smart-d05ad53a-7e4d-4d08-ac26-835658872870
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196443208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
196443208
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.196908615
Short name T105
Test name
Test status
Simulation time 6808363487 ps
CPU time 30.55 seconds
Started Apr 02 02:07:25 PM PDT 24
Finished Apr 02 02:07:57 PM PDT 24
Peak memory 216492 kb
Host smart-23de50bb-67a9-4921-8620-5fa438d9b772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196908615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.196908615
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1048985227
Short name T326
Test name
Test status
Simulation time 102655687595 ps
CPU time 27.73 seconds
Started Apr 02 02:04:02 PM PDT 24
Finished Apr 02 02:04:33 PM PDT 24
Peak memory 238100 kb
Host smart-9979b6e6-5ac4-45ba-b9f4-62edd9e66fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048985227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1048985227
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_upload.2660890085
Short name T214
Test name
Test status
Simulation time 4257133580 ps
CPU time 10.85 seconds
Started Apr 02 02:09:10 PM PDT 24
Finished Apr 02 02:09:22 PM PDT 24
Peak memory 220140 kb
Host smart-d7f378ae-585a-423b-80a4-62ce1946d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660890085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2660890085
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2148322433
Short name T215
Test name
Test status
Simulation time 12085887243 ps
CPU time 57.33 seconds
Started Apr 02 02:06:05 PM PDT 24
Finished Apr 02 02:07:03 PM PDT 24
Peak memory 234948 kb
Host smart-05678368-ad14-4069-9849-964ba52c604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148322433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2148322433
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3593200198
Short name T195
Test name
Test status
Simulation time 1709481405 ps
CPU time 6.59 seconds
Started Apr 02 02:08:25 PM PDT 24
Finished Apr 02 02:08:32 PM PDT 24
Peak memory 221620 kb
Host smart-3efc13ac-299b-4220-9d7a-442409adb4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593200198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3593200198
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1009915115
Short name T388
Test name
Test status
Simulation time 162493571817 ps
CPU time 49.79 seconds
Started Apr 02 02:06:44 PM PDT 24
Finished Apr 02 02:07:34 PM PDT 24
Peak memory 216480 kb
Host smart-c2e5fd98-4850-4b65-9b67-fc7078c6eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009915115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1009915115
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2449387022
Short name T48
Test name
Test status
Simulation time 10377511667 ps
CPU time 32.99 seconds
Started Apr 02 02:04:24 PM PDT 24
Finished Apr 02 02:04:57 PM PDT 24
Peak memory 216900 kb
Host smart-f75d941b-9fe6-4bc6-8a1d-fa3599ac5eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449387022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2449387022
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3406920243
Short name T291
Test name
Test status
Simulation time 3185407881 ps
CPU time 11.6 seconds
Started Apr 02 02:07:24 PM PDT 24
Finished Apr 02 02:07:36 PM PDT 24
Peak memory 230988 kb
Host smart-662d4a52-c4ce-4fa2-bee5-d49cd3afd212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406920243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3406920243
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2219796104
Short name T440
Test name
Test status
Simulation time 16312513 ps
CPU time 0.98 seconds
Started Apr 02 02:02:58 PM PDT 24
Finished Apr 02 02:02:59 PM PDT 24
Peak memory 218056 kb
Host smart-c0cc8ce8-b935-44c9-bdf1-11b19353b6c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219796104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2219796104
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1890070450
Short name T67
Test name
Test status
Simulation time 432224837 ps
CPU time 7.04 seconds
Started Apr 02 02:05:55 PM PDT 24
Finished Apr 02 02:06:03 PM PDT 24
Peak memory 236444 kb
Host smart-0f5f30a7-c7c9-41e8-a4b0-c6e322ec1ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890070450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1890070450
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_upload.3673643483
Short name T266
Test name
Test status
Simulation time 15916386704 ps
CPU time 11.72 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:07:11 PM PDT 24
Peak memory 233308 kb
Host smart-a8dd2c7c-8e5b-458e-9464-5d8ab334a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673643483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3673643483
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.1867051242
Short name T212
Test name
Test status
Simulation time 10981943873 ps
CPU time 13.6 seconds
Started Apr 02 02:05:05 PM PDT 24
Finished Apr 02 02:05:19 PM PDT 24
Peak memory 225324 kb
Host smart-a6b5ba39-d8b7-4f49-a154-821b870b2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867051242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1867051242
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1344050316
Short name T84
Test name
Test status
Simulation time 520820029 ps
CPU time 10.13 seconds
Started Apr 02 02:03:24 PM PDT 24
Finished Apr 02 02:03:34 PM PDT 24
Peak memory 224584 kb
Host smart-f1fc4c77-51b0-47ae-bc30-7e0c02afe775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344050316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1344050316
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_upload.1317304257
Short name T374
Test name
Test status
Simulation time 3611809233 ps
CPU time 15.21 seconds
Started Apr 02 02:08:25 PM PDT 24
Finished Apr 02 02:08:40 PM PDT 24
Peak memory 224048 kb
Host smart-0f027ad1-afd7-4a76-b539-13b1b1e61c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317304257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1317304257
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_intercept.624465892
Short name T117
Test name
Test status
Simulation time 80020104 ps
CPU time 3.51 seconds
Started Apr 02 02:09:03 PM PDT 24
Finished Apr 02 02:09:07 PM PDT 24
Peak memory 224116 kb
Host smart-4acd3ec4-cd5f-4429-95b9-7967d54ca477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624465892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.624465892
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3822799450
Short name T330
Test name
Test status
Simulation time 11710740372 ps
CPU time 28.75 seconds
Started Apr 02 02:04:31 PM PDT 24
Finished Apr 02 02:04:59 PM PDT 24
Peak memory 224172 kb
Host smart-fa8d1009-8a28-41ea-9383-f3b724786f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822799450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3822799450
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.408763703
Short name T338
Test name
Test status
Simulation time 3300483548 ps
CPU time 7.91 seconds
Started Apr 02 02:08:41 PM PDT 24
Finished Apr 02 02:08:49 PM PDT 24
Peak memory 219896 kb
Host smart-fbfb477c-8efd-42d6-86a9-1771a477d60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408763703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.408763703
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4045173763
Short name T72
Test name
Test status
Simulation time 2978728109 ps
CPU time 10.39 seconds
Started Apr 02 02:05:46 PM PDT 24
Finished Apr 02 02:05:56 PM PDT 24
Peak memory 216796 kb
Host smart-70895fad-f8ed-433c-bc6d-97c10ce38b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045173763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4045173763
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2669471608
Short name T290
Test name
Test status
Simulation time 14754758783 ps
CPU time 42.53 seconds
Started Apr 02 02:06:47 PM PDT 24
Finished Apr 02 02:07:30 PM PDT 24
Peak memory 238392 kb
Host smart-e3c5352b-74ed-4647-aeb3-d9fd2183703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669471608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2669471608
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2010656088
Short name T188
Test name
Test status
Simulation time 4460253816 ps
CPU time 9.51 seconds
Started Apr 02 02:08:49 PM PDT 24
Finished Apr 02 02:08:59 PM PDT 24
Peak memory 224660 kb
Host smart-324102bc-69af-48cc-be48-b16d4d847f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010656088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2010656088
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_upload.1220788776
Short name T223
Test name
Test status
Simulation time 4929821295 ps
CPU time 16.93 seconds
Started Apr 02 02:09:03 PM PDT 24
Finished Apr 02 02:09:20 PM PDT 24
Peak memory 236476 kb
Host smart-117c4956-eb60-46a0-9e60-d69a545bc4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220788776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1220788776
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.426816627
Short name T221
Test name
Test status
Simulation time 9758276429 ps
CPU time 9.86 seconds
Started Apr 02 02:09:39 PM PDT 24
Finished Apr 02 02:09:49 PM PDT 24
Peak memory 217644 kb
Host smart-f421d1c9-1378-4d8e-8937-fb12b440c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426816627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.426816627
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1851651402
Short name T252
Test name
Test status
Simulation time 23531457572 ps
CPU time 120.39 seconds
Started Apr 02 02:10:49 PM PDT 24
Finished Apr 02 02:12:50 PM PDT 24
Peak memory 238196 kb
Host smart-67d5aca1-4a0b-421e-a9a4-da48b14e7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851651402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1851651402
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.975121595
Short name T38
Test name
Test status
Simulation time 54863659 ps
CPU time 0.97 seconds
Started Apr 02 02:08:49 PM PDT 24
Finished Apr 02 02:08:51 PM PDT 24
Peak memory 205576 kb
Host smart-0e8f8c10-1b3d-4c0d-9e4e-58cc0075b7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975121595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.975121595
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2551544924
Short name T205
Test name
Test status
Simulation time 4642559395 ps
CPU time 11.17 seconds
Started Apr 02 02:04:57 PM PDT 24
Finished Apr 02 02:05:11 PM PDT 24
Peak memory 223916 kb
Host smart-f1c9d464-47e2-41d4-904a-01d2b5148ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551544924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2551544924
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3122686952
Short name T283
Test name
Test status
Simulation time 3095099913 ps
CPU time 10.26 seconds
Started Apr 02 02:05:16 PM PDT 24
Finished Apr 02 02:05:27 PM PDT 24
Peak memory 233512 kb
Host smart-6447d963-50ee-4d6b-abaa-acd19d5d80a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122686952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3122686952
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3805560785
Short name T379
Test name
Test status
Simulation time 40409388952 ps
CPU time 68.16 seconds
Started Apr 02 02:08:37 PM PDT 24
Finished Apr 02 02:09:45 PM PDT 24
Peak memory 216456 kb
Host smart-786d0ad6-0d8f-4be7-abe3-bb0781401ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805560785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3805560785
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4238604053
Short name T202
Test name
Test status
Simulation time 1317402779 ps
CPU time 14.64 seconds
Started Apr 02 02:09:31 PM PDT 24
Finished Apr 02 02:09:46 PM PDT 24
Peak memory 222192 kb
Host smart-86b2625e-496d-4c92-96e2-08496e95515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238604053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4238604053
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4171297753
Short name T29
Test name
Test status
Simulation time 42750222 ps
CPU time 0.69 seconds
Started Apr 02 02:02:54 PM PDT 24
Finished Apr 02 02:02:54 PM PDT 24
Peak memory 205336 kb
Host smart-953152df-9b45-46a0-8aa2-4649673e4a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171297753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
171297753
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2035180871
Short name T44
Test name
Test status
Simulation time 252982190 ps
CPU time 5.43 seconds
Started Apr 02 02:07:54 PM PDT 24
Finished Apr 02 02:08:00 PM PDT 24
Peak memory 216756 kb
Host smart-c075f4c6-3074-422d-a821-d41d719ba507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035180871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2035180871
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3001836281
Short name T339
Test name
Test status
Simulation time 1601093866 ps
CPU time 5.76 seconds
Started Apr 02 02:07:42 PM PDT 24
Finished Apr 02 02:07:48 PM PDT 24
Peak memory 221532 kb
Host smart-11929994-3c8b-4c03-b4a5-d1b1b812c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001836281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3001836281
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3960081866
Short name T315
Test name
Test status
Simulation time 259444080 ps
CPU time 7.06 seconds
Started Apr 02 02:11:06 PM PDT 24
Finished Apr 02 02:11:13 PM PDT 24
Peak memory 232736 kb
Host smart-ec5c60cc-e8cf-4070-bb27-9c026ebab948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960081866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3960081866
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4083155478
Short name T76
Test name
Test status
Simulation time 535273228 ps
CPU time 3.2 seconds
Started Apr 02 02:05:37 PM PDT 24
Finished Apr 02 02:05:40 PM PDT 24
Peak memory 217116 kb
Host smart-4b72daad-fb4c-4c66-b2ad-24b527af8212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083155478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4083155478
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_upload.1183781316
Short name T373
Test name
Test status
Simulation time 17867063445 ps
CPU time 16.66 seconds
Started Apr 02 02:05:51 PM PDT 24
Finished Apr 02 02:06:09 PM PDT 24
Peak memory 232604 kb
Host smart-7d74c60e-bc76-4c7c-b617-392bf7a126e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183781316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1183781316
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2927841996
Short name T179
Test name
Test status
Simulation time 11234402843 ps
CPU time 13.38 seconds
Started Apr 02 02:06:17 PM PDT 24
Finished Apr 02 02:06:30 PM PDT 24
Peak memory 224196 kb
Host smart-819286d9-9103-48a6-b8bf-3381b465e593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927841996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2927841996
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.2012559350
Short name T218
Test name
Test status
Simulation time 2671091226 ps
CPU time 10.49 seconds
Started Apr 02 02:07:05 PM PDT 24
Finished Apr 02 02:07:16 PM PDT 24
Peak memory 216512 kb
Host smart-d52e0ccf-55f6-42bc-a66d-3bd205178dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012559350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2012559350
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1837765788
Short name T119
Test name
Test status
Simulation time 1183227475 ps
CPU time 4.82 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:08:31 PM PDT 24
Peak memory 218784 kb
Host smart-7ea54d98-8f3b-42b6-bd8e-38e3514a74ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837765788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1837765788
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.185805805
Short name T316
Test name
Test status
Simulation time 354396269 ps
CPU time 7.1 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:08:34 PM PDT 24
Peak memory 218828 kb
Host smart-007f38c3-18d6-440c-a27a-231db242364d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185805805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.185805805
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1690133595
Short name T192
Test name
Test status
Simulation time 1354921596 ps
CPU time 2.89 seconds
Started Apr 02 02:10:47 PM PDT 24
Finished Apr 02 02:10:50 PM PDT 24
Peak memory 223276 kb
Host smart-18e8549e-c951-4fa0-b4fd-d235d8777c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690133595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1690133595
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3235106888
Short name T292
Test name
Test status
Simulation time 3531174835 ps
CPU time 18.61 seconds
Started Apr 02 02:11:22 PM PDT 24
Finished Apr 02 02:11:41 PM PDT 24
Peak memory 241076 kb
Host smart-0e5658c9-9cf8-44ab-aa09-2f3e3b2d3db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235106888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3235106888
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.149055910
Short name T231
Test name
Test status
Simulation time 352706816 ps
CPU time 6.88 seconds
Started Apr 02 02:04:17 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 223560 kb
Host smart-2dff7d8b-8565-4e77-aee1-b68518b264bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149055910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.149055910
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3007166536
Short name T127
Test name
Test status
Simulation time 2537779370 ps
CPU time 4.63 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 215428 kb
Host smart-7c3e98f7-dfd4-4718-93b3-f83c13670ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007166536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3007166536
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1872360313
Short name T65
Test name
Test status
Simulation time 20411802675 ps
CPU time 51.5 seconds
Started Apr 02 02:06:00 PM PDT 24
Finished Apr 02 02:06:52 PM PDT 24
Peak memory 240296 kb
Host smart-0cd2fd6a-f08b-4d86-955b-b778c8a12c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872360313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1872360313
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3523600390
Short name T389
Test name
Test status
Simulation time 36018402023 ps
CPU time 50.01 seconds
Started Apr 02 02:06:31 PM PDT 24
Finished Apr 02 02:07:22 PM PDT 24
Peak memory 216408 kb
Host smart-9f64ca7a-a9dd-4bc6-ab29-d2e352fa48b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523600390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3523600390
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1000942978
Short name T352
Test name
Test status
Simulation time 391938163 ps
CPU time 13.38 seconds
Started Apr 02 02:06:41 PM PDT 24
Finished Apr 02 02:06:55 PM PDT 24
Peak memory 237740 kb
Host smart-31e9567f-f5d9-4359-aef0-501caa2b0552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000942978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1000942978
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3772133290
Short name T277
Test name
Test status
Simulation time 7250546474 ps
CPU time 24.57 seconds
Started Apr 02 02:07:24 PM PDT 24
Finished Apr 02 02:07:49 PM PDT 24
Peak memory 238844 kb
Host smart-d6d8985c-2d1e-46af-8f52-db30d7b7a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772133290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3772133290
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3048972370
Short name T75
Test name
Test status
Simulation time 916925478 ps
CPU time 4.71 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:08:30 PM PDT 24
Peak memory 222556 kb
Host smart-fcf9685b-4859-44be-9dc0-ac95713f1aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048972370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3048972370
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1562653897
Short name T224
Test name
Test status
Simulation time 2968577258 ps
CPU time 11.02 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:09:02 PM PDT 24
Peak memory 224616 kb
Host smart-a835856c-6c38-4f5d-9016-043b72585366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562653897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1562653897
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3924660922
Short name T322
Test name
Test status
Simulation time 152541055 ps
CPU time 3.7 seconds
Started Apr 02 02:09:17 PM PDT 24
Finished Apr 02 02:09:22 PM PDT 24
Peak memory 218796 kb
Host smart-1a0aa565-ab62-420c-adfb-ce2ecb01433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924660922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3924660922
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3177001539
Short name T305
Test name
Test status
Simulation time 30537682423 ps
CPU time 49.26 seconds
Started Apr 02 02:09:26 PM PDT 24
Finished Apr 02 02:10:16 PM PDT 24
Peak memory 232820 kb
Host smart-eff70ba9-46ec-4036-bc39-78319c1dc7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177001539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3177001539
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4227981865
Short name T70
Test name
Test status
Simulation time 439758931 ps
CPU time 7.61 seconds
Started Apr 02 02:10:59 PM PDT 24
Finished Apr 02 02:11:07 PM PDT 24
Peak memory 223104 kb
Host smart-2302af9c-d12b-455d-86e2-1584acd47938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227981865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4227981865
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3539664143
Short name T93
Test name
Test status
Simulation time 7200094092 ps
CPU time 17.81 seconds
Started Apr 02 02:11:05 PM PDT 24
Finished Apr 02 02:11:23 PM PDT 24
Peak memory 218156 kb
Host smart-64fe3bbc-abd8-4ffa-b6da-c92e4d56797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539664143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3539664143
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2208641270
Short name T81
Test name
Test status
Simulation time 24791066563 ps
CPU time 59.08 seconds
Started Apr 02 02:05:33 PM PDT 24
Finished Apr 02 02:06:32 PM PDT 24
Peak memory 236972 kb
Host smart-5100790c-7c46-4e5f-bed1-4d8fb9c79129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208641270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2208641270
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3659382159
Short name T113
Test name
Test status
Simulation time 227895764 ps
CPU time 3.42 seconds
Started Apr 02 02:08:41 PM PDT 24
Finished Apr 02 02:08:44 PM PDT 24
Peak memory 223572 kb
Host smart-d6035b70-8e3d-4446-818c-f83e8e4d5b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659382159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3659382159
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1515325779
Short name T107
Test name
Test status
Simulation time 3445591634 ps
CPU time 7.58 seconds
Started Apr 02 02:05:46 PM PDT 24
Finished Apr 02 02:05:53 PM PDT 24
Peak memory 216344 kb
Host smart-b77a181e-aa9f-44cc-85cf-c4c53c17d462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515325779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1515325779
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1126645541
Short name T245
Test name
Test status
Simulation time 1774783952 ps
CPU time 5.5 seconds
Started Apr 02 02:03:24 PM PDT 24
Finished Apr 02 02:03:30 PM PDT 24
Peak memory 218424 kb
Host smart-11ac6b52-42c4-4882-acba-ca475ac2903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126645541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1126645541
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2041958182
Short name T131
Test name
Test status
Simulation time 1201715907 ps
CPU time 18.42 seconds
Started Apr 02 12:29:30 PM PDT 24
Finished Apr 02 12:29:48 PM PDT 24
Peak memory 215464 kb
Host smart-0617f7c9-a2b6-4835-a7fb-612d07d53da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041958182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2041958182
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.947048980
Short name T366
Test name
Test status
Simulation time 305176616 ps
CPU time 19.01 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:55 PM PDT 24
Peak memory 222604 kb
Host smart-67f60214-e5c5-4d78-89d5-ca5e1daaf572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947048980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.947048980
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2966925180
Short name T282
Test name
Test status
Simulation time 1771233103 ps
CPU time 7.11 seconds
Started Apr 02 02:02:44 PM PDT 24
Finished Apr 02 02:02:51 PM PDT 24
Peak memory 223220 kb
Host smart-cfee7db4-c36d-4c27-8130-806ec4be3a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966925180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2966925180
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3585197749
Short name T257
Test name
Test status
Simulation time 256917961 ps
CPU time 3.02 seconds
Started Apr 02 02:05:00 PM PDT 24
Finished Apr 02 02:05:04 PM PDT 24
Peak memory 218272 kb
Host smart-8174c1a4-caaa-4e60-8628-85d2849de90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585197749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3585197749
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1935443887
Short name T297
Test name
Test status
Simulation time 2199924707 ps
CPU time 31.33 seconds
Started Apr 02 02:05:19 PM PDT 24
Finished Apr 02 02:05:51 PM PDT 24
Peak memory 232900 kb
Host smart-ae5c7091-8341-4a5f-b267-7600d5e66ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935443887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1935443887
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1381781432
Short name T324
Test name
Test status
Simulation time 205897889 ps
CPU time 3.54 seconds
Started Apr 02 02:05:16 PM PDT 24
Finished Apr 02 02:05:20 PM PDT 24
Peak memory 218632 kb
Host smart-fcc21aaf-9f32-4522-9189-202b20c94495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381781432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1381781432
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4086932565
Short name T80
Test name
Test status
Simulation time 3927223145 ps
CPU time 15.54 seconds
Started Apr 02 02:05:13 PM PDT 24
Finished Apr 02 02:05:28 PM PDT 24
Peak memory 216420 kb
Host smart-4931a640-046d-48b3-85ae-9f8b1eb7d060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086932565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4086932565
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.208847787
Short name T261
Test name
Test status
Simulation time 431910831 ps
CPU time 3.36 seconds
Started Apr 02 02:05:35 PM PDT 24
Finished Apr 02 02:05:38 PM PDT 24
Peak memory 218448 kb
Host smart-aae89021-b528-4fa9-acea-dea90a7a5b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208847787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.208847787
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1102879948
Short name T197
Test name
Test status
Simulation time 626634401 ps
CPU time 2.82 seconds
Started Apr 02 02:06:23 PM PDT 24
Finished Apr 02 02:06:26 PM PDT 24
Peak memory 218852 kb
Host smart-4c19f0d9-2ef4-4f78-8d33-8b76d1ade8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102879948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1102879948
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1698001943
Short name T69
Test name
Test status
Simulation time 104442352392 ps
CPU time 25.41 seconds
Started Apr 02 02:06:23 PM PDT 24
Finished Apr 02 02:06:49 PM PDT 24
Peak memory 235340 kb
Host smart-7546fc5a-9412-408f-a85c-2d8e520e5c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698001943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1698001943
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3308552327
Short name T46
Test name
Test status
Simulation time 44060518 ps
CPU time 2.32 seconds
Started Apr 02 02:06:40 PM PDT 24
Finished Apr 02 02:06:43 PM PDT 24
Peak memory 216940 kb
Host smart-9a93c0aa-5691-480d-a9ae-fcd9e7ca0745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308552327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3308552327
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.177093078
Short name T208
Test name
Test status
Simulation time 15144641572 ps
CPU time 12.82 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:07:12 PM PDT 24
Peak memory 218768 kb
Host smart-c2b64d2b-8ca3-4e28-abd4-0433d71d07a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177093078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.177093078
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1812622164
Short name T279
Test name
Test status
Simulation time 3812936059 ps
CPU time 8.16 seconds
Started Apr 02 02:07:07 PM PDT 24
Finished Apr 02 02:07:15 PM PDT 24
Peak memory 216860 kb
Host smart-998dd30b-f195-48d5-b3d3-908e6c9f28fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812622164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1812622164
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2455881629
Short name T273
Test name
Test status
Simulation time 2047545762 ps
CPU time 5.72 seconds
Started Apr 02 02:07:21 PM PDT 24
Finished Apr 02 02:07:26 PM PDT 24
Peak memory 223040 kb
Host smart-57395826-633d-45fb-a02b-9c4d0a186d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455881629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2455881629
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2581421689
Short name T71
Test name
Test status
Simulation time 16470955389 ps
CPU time 7.91 seconds
Started Apr 02 02:07:20 PM PDT 24
Finished Apr 02 02:07:28 PM PDT 24
Peak memory 222656 kb
Host smart-3bfaee0c-1eba-45fc-bf56-f93d98acb480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581421689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2581421689
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.272618550
Short name T294
Test name
Test status
Simulation time 8603390443 ps
CPU time 122.84 seconds
Started Apr 02 02:07:48 PM PDT 24
Finished Apr 02 02:09:51 PM PDT 24
Peak memory 252132 kb
Host smart-b445c7d0-1322-43a4-95e6-23a82bb36c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272618550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.272618550
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2382562703
Short name T204
Test name
Test status
Simulation time 233484529 ps
CPU time 2.89 seconds
Started Apr 02 02:07:55 PM PDT 24
Finished Apr 02 02:07:58 PM PDT 24
Peak memory 222260 kb
Host smart-0b3e3967-39cd-47b5-9506-23d5f6f8e410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382562703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2382562703
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_upload.2141774717
Short name T274
Test name
Test status
Simulation time 91851140 ps
CPU time 2.81 seconds
Started Apr 02 02:03:39 PM PDT 24
Finished Apr 02 02:03:42 PM PDT 24
Peak memory 222656 kb
Host smart-1ae8c17c-9954-45c3-9ad0-7acf62601785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141774717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2141774717
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1240590175
Short name T289
Test name
Test status
Simulation time 444434756 ps
CPU time 2.97 seconds
Started Apr 02 02:08:47 PM PDT 24
Finished Apr 02 02:08:51 PM PDT 24
Peak memory 222208 kb
Host smart-69f53ac9-cc8f-49fb-84ff-3b6a52e97daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240590175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1240590175
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_upload.3583235136
Short name T233
Test name
Test status
Simulation time 3390300248 ps
CPU time 8.68 seconds
Started Apr 02 02:09:27 PM PDT 24
Finished Apr 02 02:09:36 PM PDT 24
Peak memory 217704 kb
Host smart-1bfca27f-c62c-49e9-9bac-f78c0da6ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583235136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3583235136
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2556817616
Short name T26
Test name
Test status
Simulation time 365072074 ps
CPU time 2.39 seconds
Started Apr 02 02:03:50 PM PDT 24
Finished Apr 02 02:03:53 PM PDT 24
Peak memory 221460 kb
Host smart-32d61d23-d6e0-41ab-ab62-c2d7d1986aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556817616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2556817616
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3302618133
Short name T248
Test name
Test status
Simulation time 5950258558 ps
CPU time 20.11 seconds
Started Apr 02 02:10:01 PM PDT 24
Finished Apr 02 02:10:21 PM PDT 24
Peak memory 218804 kb
Host smart-41b5bff2-c055-4152-a756-87e648900c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302618133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3302618133
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3014805410
Short name T288
Test name
Test status
Simulation time 695022595 ps
CPU time 2.62 seconds
Started Apr 02 02:09:58 PM PDT 24
Finished Apr 02 02:10:01 PM PDT 24
Peak memory 222796 kb
Host smart-6b23f910-b943-4925-b624-991e0fb81ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014805410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3014805410
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2117015555
Short name T219
Test name
Test status
Simulation time 9514634321 ps
CPU time 26.96 seconds
Started Apr 02 02:09:57 PM PDT 24
Finished Apr 02 02:10:25 PM PDT 24
Peak memory 234972 kb
Host smart-cff1c43b-1042-483e-affe-c02574c8b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117015555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2117015555
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.278383476
Short name T210
Test name
Test status
Simulation time 17031446431 ps
CPU time 24.05 seconds
Started Apr 02 02:10:32 PM PDT 24
Finished Apr 02 02:10:56 PM PDT 24
Peak memory 216800 kb
Host smart-126e7a29-56f4-4747-b598-472be1b38ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278383476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.278383476
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1731451170
Short name T236
Test name
Test status
Simulation time 20482564308 ps
CPU time 9.23 seconds
Started Apr 02 02:10:34 PM PDT 24
Finished Apr 02 02:10:43 PM PDT 24
Peak memory 222220 kb
Host smart-6bade1ca-ddc1-4138-a74e-da0c874db983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731451170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1731451170
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.216638245
Short name T189
Test name
Test status
Simulation time 1818306812 ps
CPU time 7.82 seconds
Started Apr 02 02:11:06 PM PDT 24
Finished Apr 02 02:11:13 PM PDT 24
Peak memory 222968 kb
Host smart-d8c2b298-1d86-48a6-97fb-22a6026e46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216638245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.216638245
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.92457606
Short name T99
Test name
Test status
Simulation time 32463496 ps
CPU time 0.91 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 207068 kb
Host smart-cdbc9250-7e6b-47c5-98cb-b1ce0a08569d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92457606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.92457606
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2139864332
Short name T753
Test name
Test status
Simulation time 13899627 ps
CPU time 0.71 seconds
Started Apr 02 12:28:58 PM PDT 24
Finished Apr 02 12:28:59 PM PDT 24
Peak memory 203784 kb
Host smart-e9daac4a-b6be-4f01-95f0-04c490d1d28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139864332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
139864332
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1298977746
Short name T174
Test name
Test status
Simulation time 329982770 ps
CPU time 5.74 seconds
Started Apr 02 02:03:06 PM PDT 24
Finished Apr 02 02:03:12 PM PDT 24
Peak memory 216628 kb
Host smart-0b559eab-c2c8-41ba-ac33-f4e093cc3b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298977746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1298977746
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2115859253
Short name T263
Test name
Test status
Simulation time 5641803700 ps
CPU time 7.9 seconds
Started Apr 02 02:03:03 PM PDT 24
Finished Apr 02 02:03:11 PM PDT 24
Peak memory 235516 kb
Host smart-ddc56278-8ea5-49e9-8043-db8152f845c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115859253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2115859253
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3179839700
Short name T377
Test name
Test status
Simulation time 5792011309 ps
CPU time 36.82 seconds
Started Apr 02 02:03:02 PM PDT 24
Finished Apr 02 02:03:39 PM PDT 24
Peak memory 216460 kb
Host smart-51d9eefe-8e66-42f0-aa0f-4a669990750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179839700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3179839700
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_upload.1847197828
Short name T77
Test name
Test status
Simulation time 130668822 ps
CPU time 3.51 seconds
Started Apr 02 02:03:06 PM PDT 24
Finished Apr 02 02:03:10 PM PDT 24
Peak memory 222104 kb
Host smart-3c09d9ce-33e5-435a-b594-089b5029d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847197828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1847197828
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2531292727
Short name T229
Test name
Test status
Simulation time 536796914 ps
CPU time 8.74 seconds
Started Apr 02 02:04:57 PM PDT 24
Finished Apr 02 02:05:08 PM PDT 24
Peak memory 224616 kb
Host smart-3a064c2f-9799-4e5d-895e-53312154c295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531292727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2531292727
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1675402025
Short name T394
Test name
Test status
Simulation time 1863780191 ps
CPU time 14.84 seconds
Started Apr 02 02:04:55 PM PDT 24
Finished Apr 02 02:05:14 PM PDT 24
Peak memory 216352 kb
Host smart-f27bf8ef-810c-40e1-ac7e-8b8fc58be5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675402025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1675402025
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1708686847
Short name T344
Test name
Test status
Simulation time 584721904 ps
CPU time 3.06 seconds
Started Apr 02 02:05:03 PM PDT 24
Finished Apr 02 02:05:06 PM PDT 24
Peak memory 224360 kb
Host smart-6af6e99d-0e1d-49bd-af99-9dbaf34d80d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708686847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1708686847
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.955806890
Short name T259
Test name
Test status
Simulation time 986822882 ps
CPU time 2.52 seconds
Started Apr 02 02:05:30 PM PDT 24
Finished Apr 02 02:05:33 PM PDT 24
Peak memory 222796 kb
Host smart-7049b6c2-b3c2-40a5-bf23-5cde8514d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955806890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.955806890
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.707251963
Short name T83
Test name
Test status
Simulation time 19648287315 ps
CPU time 43.37 seconds
Started Apr 02 02:05:47 PM PDT 24
Finished Apr 02 02:06:31 PM PDT 24
Peak memory 223248 kb
Host smart-14974a19-fc91-4d4a-a068-1b97617a66b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707251963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.707251963
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_upload.432165532
Short name T272
Test name
Test status
Simulation time 4070849795 ps
CPU time 14.23 seconds
Started Apr 02 02:06:33 PM PDT 24
Finished Apr 02 02:06:49 PM PDT 24
Peak memory 216400 kb
Host smart-84df2c67-a963-432e-a03d-c581e1ad8b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432165532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.432165532
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3837061036
Short name T225
Test name
Test status
Simulation time 3483301807 ps
CPU time 10.83 seconds
Started Apr 02 02:06:39 PM PDT 24
Finished Apr 02 02:06:50 PM PDT 24
Peak memory 221952 kb
Host smart-8b715a30-42b5-4822-be6f-ead01d2d1d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837061036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3837061036
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.197500333
Short name T334
Test name
Test status
Simulation time 6940080649 ps
CPU time 19.24 seconds
Started Apr 02 02:06:57 PM PDT 24
Finished Apr 02 02:07:16 PM PDT 24
Peak memory 232936 kb
Host smart-2da79dfe-1358-4128-a958-d5fb60948ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197500333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.197500333
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.155845708
Short name T73
Test name
Test status
Simulation time 35698842370 ps
CPU time 25.1 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:07:24 PM PDT 24
Peak memory 237852 kb
Host smart-10d52b8c-8968-4145-8f23-700308bd1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155845708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.155845708
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1039346591
Short name T97
Test name
Test status
Simulation time 4524200636 ps
CPU time 9.33 seconds
Started Apr 02 02:07:38 PM PDT 24
Finished Apr 02 02:07:48 PM PDT 24
Peak memory 218832 kb
Host smart-14899fcd-d7bf-412e-be43-7efa821b1d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039346591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1039346591
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1629095016
Short name T175
Test name
Test status
Simulation time 2481411198 ps
CPU time 23.03 seconds
Started Apr 02 02:07:47 PM PDT 24
Finished Apr 02 02:08:10 PM PDT 24
Peak memory 223148 kb
Host smart-b74fdaf9-9e49-4ccb-aea1-441ac548de13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629095016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1629095016
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.339128149
Short name T295
Test name
Test status
Simulation time 4457819987 ps
CPU time 33.95 seconds
Started Apr 02 02:07:54 PM PDT 24
Finished Apr 02 02:08:28 PM PDT 24
Peak memory 241036 kb
Host smart-9895c12a-9fe6-4a04-af76-4175c7c06f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339128149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.339128149
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3062061725
Short name T241
Test name
Test status
Simulation time 1037372806 ps
CPU time 16.81 seconds
Started Apr 02 02:03:35 PM PDT 24
Finished Apr 02 02:03:52 PM PDT 24
Peak memory 252152 kb
Host smart-74595926-5ba8-4988-b8df-94a08379c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062061725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3062061725
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3156745104
Short name T331
Test name
Test status
Simulation time 593014524 ps
CPU time 7.15 seconds
Started Apr 02 02:08:06 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 223004 kb
Host smart-d5e333b8-3afd-43b2-a0de-61aeda3546b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156745104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3156745104
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3548287464
Short name T243
Test name
Test status
Simulation time 585324757 ps
CPU time 4.84 seconds
Started Apr 02 02:08:05 PM PDT 24
Finished Apr 02 02:08:11 PM PDT 24
Peak memory 226304 kb
Host smart-beae1cfa-bd5e-472d-98f7-65eb98e3d395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548287464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3548287464
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_upload.1756259918
Short name T314
Test name
Test status
Simulation time 702102285 ps
CPU time 7.2 seconds
Started Apr 02 02:08:16 PM PDT 24
Finished Apr 02 02:08:24 PM PDT 24
Peak memory 234808 kb
Host smart-8ab3ee99-f34d-4898-9263-c8794d92ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756259918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1756259918
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_intercept.494113023
Short name T90
Test name
Test status
Simulation time 10626383088 ps
CPU time 13.59 seconds
Started Apr 02 02:08:34 PM PDT 24
Finished Apr 02 02:08:48 PM PDT 24
Peak memory 217960 kb
Host smart-9c496945-4d57-483b-af8d-e1856d42a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494113023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.494113023
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_upload.1793815059
Short name T222
Test name
Test status
Simulation time 4828808924 ps
CPU time 5.76 seconds
Started Apr 02 02:08:41 PM PDT 24
Finished Apr 02 02:08:47 PM PDT 24
Peak memory 224680 kb
Host smart-dd042b87-eaa2-4b7c-987b-fb4a9babec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793815059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1793815059
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3362002385
Short name T310
Test name
Test status
Simulation time 298183503 ps
CPU time 11.95 seconds
Started Apr 02 02:09:07 PM PDT 24
Finished Apr 02 02:09:19 PM PDT 24
Peak memory 243100 kb
Host smart-69d3ea7f-109e-4147-a8fe-848d8371c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362002385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3362002385
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4243574428
Short name T254
Test name
Test status
Simulation time 6191110793 ps
CPU time 24.33 seconds
Started Apr 02 02:09:08 PM PDT 24
Finished Apr 02 02:09:32 PM PDT 24
Peak memory 230268 kb
Host smart-ad3724f3-59fd-4e60-b5e8-59dd53e4db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243574428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4243574428
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2653855019
Short name T234
Test name
Test status
Simulation time 9219384340 ps
CPU time 20.34 seconds
Started Apr 02 02:09:12 PM PDT 24
Finished Apr 02 02:09:33 PM PDT 24
Peak memory 237896 kb
Host smart-7a58faf0-487d-4c67-a599-f0708bc2fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653855019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2653855019
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1655771557
Short name T244
Test name
Test status
Simulation time 637680666 ps
CPU time 5.54 seconds
Started Apr 02 02:09:12 PM PDT 24
Finished Apr 02 02:09:18 PM PDT 24
Peak memory 223064 kb
Host smart-d4534a83-ae38-4069-af6f-965559142648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655771557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1655771557
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1786383346
Short name T343
Test name
Test status
Simulation time 240185883 ps
CPU time 2.94 seconds
Started Apr 02 02:09:25 PM PDT 24
Finished Apr 02 02:09:29 PM PDT 24
Peak memory 222712 kb
Host smart-5a9c40a5-b58b-4c8b-a7ef-c0300b2fd554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786383346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1786383346
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.299515201
Short name T74
Test name
Test status
Simulation time 1430440140 ps
CPU time 7.75 seconds
Started Apr 02 02:09:49 PM PDT 24
Finished Apr 02 02:09:57 PM PDT 24
Peak memory 217452 kb
Host smart-7ff9e5e1-4125-4551-8a90-0d460a7f0f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299515201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.299515201
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3664493565
Short name T24
Test name
Test status
Simulation time 127339522 ps
CPU time 2.6 seconds
Started Apr 02 02:10:35 PM PDT 24
Finished Apr 02 02:10:38 PM PDT 24
Peak memory 218956 kb
Host smart-64455950-3046-4851-b343-ccc19a25d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664493565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3664493565
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2486447355
Short name T187
Test name
Test status
Simulation time 2032449911 ps
CPU time 6.45 seconds
Started Apr 02 02:10:46 PM PDT 24
Finished Apr 02 02:10:53 PM PDT 24
Peak memory 223388 kb
Host smart-b3a8cc83-9de8-4b4a-939e-ab69ce5f0efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486447355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2486447355
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2045663682
Short name T319
Test name
Test status
Simulation time 1769877892 ps
CPU time 6.79 seconds
Started Apr 02 02:10:44 PM PDT 24
Finished Apr 02 02:10:51 PM PDT 24
Peak memory 216664 kb
Host smart-9068df92-2600-432c-bc17-688db59fb4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045663682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2045663682
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_upload.312828819
Short name T253
Test name
Test status
Simulation time 2640472836 ps
CPU time 9.21 seconds
Started Apr 02 02:10:45 PM PDT 24
Finished Apr 02 02:10:54 PM PDT 24
Peak memory 222508 kb
Host smart-8db9bd88-e463-4c49-b62a-1ab6d60fc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312828819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.312828819
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1127005923
Short name T226
Test name
Test status
Simulation time 815657325 ps
CPU time 4.35 seconds
Started Apr 02 02:10:59 PM PDT 24
Finished Apr 02 02:11:04 PM PDT 24
Peak memory 222196 kb
Host smart-c970ce62-533a-4b0a-9862-b22edd654b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127005923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1127005923
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3333705779
Short name T298
Test name
Test status
Simulation time 3688257061 ps
CPU time 55.49 seconds
Started Apr 02 02:11:08 PM PDT 24
Finished Apr 02 02:12:04 PM PDT 24
Peak memory 240260 kb
Host smart-97c66d49-3b64-4e97-b4e8-6583da9afd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333705779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3333705779
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1409023238
Short name T286
Test name
Test status
Simulation time 701554599 ps
CPU time 5.95 seconds
Started Apr 02 02:11:16 PM PDT 24
Finished Apr 02 02:11:22 PM PDT 24
Peak memory 222556 kb
Host smart-b20d866c-45d8-4548-8d78-0fbb0a59e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409023238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1409023238
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3078085663
Short name T190
Test name
Test status
Simulation time 19744910486 ps
CPU time 9.08 seconds
Started Apr 02 02:04:33 PM PDT 24
Finished Apr 02 02:04:43 PM PDT 24
Peak memory 216852 kb
Host smart-682ee059-f185-4185-897a-be9719f80dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078085663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3078085663
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1316266413
Short name T323
Test name
Test status
Simulation time 477765688 ps
CPU time 2.91 seconds
Started Apr 02 02:04:45 PM PDT 24
Finished Apr 02 02:04:49 PM PDT 24
Peak memory 222800 kb
Host smart-d708515f-b350-4a5e-9a8a-8fc446e34a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316266413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1316266413
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3278786707
Short name T101
Test name
Test status
Simulation time 171966864 ps
CPU time 1.41 seconds
Started Apr 02 12:29:04 PM PDT 24
Finished Apr 02 12:29:05 PM PDT 24
Peak memory 207252 kb
Host smart-198f1bcf-65ad-4a4f-96f1-9e291458de99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278786707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3278786707
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4065112488
Short name T861
Test name
Test status
Simulation time 1361487651 ps
CPU time 25.13 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 215508 kb
Host smart-ea67ca69-84bd-4348-901b-9ae887ba0a42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065112488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4065112488
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.958432984
Short name T782
Test name
Test status
Simulation time 1208922312 ps
CPU time 13.81 seconds
Started Apr 02 12:28:57 PM PDT 24
Finished Apr 02 12:29:12 PM PDT 24
Peak memory 207160 kb
Host smart-206364bc-e2b8-4308-9950-9940260f312d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958432984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.958432984
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3730801398
Short name T102
Test name
Test status
Simulation time 15170836 ps
CPU time 0.94 seconds
Started Apr 02 12:29:22 PM PDT 24
Finished Apr 02 12:29:23 PM PDT 24
Peak memory 206712 kb
Host smart-ca79f625-ca48-4bd6-969a-245bbcf782f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730801398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3730801398
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1042348704
Short name T804
Test name
Test status
Simulation time 49006371 ps
CPU time 1.7 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:59 PM PDT 24
Peak memory 215684 kb
Host smart-98f22923-5119-4b5d-9188-5780de856f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042348704 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1042348704
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4191525284
Short name T789
Test name
Test status
Simulation time 219666213 ps
CPU time 1.55 seconds
Started Apr 02 12:28:56 PM PDT 24
Finished Apr 02 12:28:58 PM PDT 24
Peak memory 207320 kb
Host smart-b37d128b-7cb1-4ee6-895a-e465576bfdc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191525284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
191525284
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.492579209
Short name T148
Test name
Test status
Simulation time 214580764 ps
CPU time 1.81 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 215576 kb
Host smart-ce366c3a-6c19-465c-ac7d-6bb4c9a5f73b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492579209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.492579209
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3201445109
Short name T867
Test name
Test status
Simulation time 11363761 ps
CPU time 0.66 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 203508 kb
Host smart-fec2d497-3951-44b8-874c-9287a0b7bdc1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201445109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3201445109
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.55046932
Short name T809
Test name
Test status
Simulation time 215229106 ps
CPU time 3.61 seconds
Started Apr 02 12:28:57 PM PDT 24
Finished Apr 02 12:29:01 PM PDT 24
Peak memory 215528 kb
Host smart-ccf79904-d17d-4423-85d7-6a0e3635ea9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55046932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.55046932
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1811810673
Short name T800
Test name
Test status
Simulation time 120202893 ps
CPU time 3.11 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:23 PM PDT 24
Peak memory 215620 kb
Host smart-3a51ba58-282e-494e-9098-c346e49ea3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811810673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
811810673
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.936093707
Short name T364
Test name
Test status
Simulation time 285220498 ps
CPU time 6.59 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 215756 kb
Host smart-92726f87-dd7f-430f-8dc6-92e9857c8df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936093707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.936093707
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2526511814
Short name T130
Test name
Test status
Simulation time 1249110670 ps
CPU time 8.45 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 207224 kb
Host smart-f5ec3e7e-1af4-4183-bd48-abf0f189d976
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526511814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2526511814
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2964717206
Short name T848
Test name
Test status
Simulation time 3615101243 ps
CPU time 34.23 seconds
Started Apr 02 12:29:22 PM PDT 24
Finished Apr 02 12:29:56 PM PDT 24
Peak memory 215412 kb
Host smart-0dd5673e-8f11-403a-b1cc-20bc68f1a18b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964717206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2964717206
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2999875493
Short name T135
Test name
Test status
Simulation time 787320372 ps
CPU time 3.93 seconds
Started Apr 02 12:29:13 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 217520 kb
Host smart-3346bd68-1c14-4250-bc43-f0519897ea67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999875493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2999875493
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3459979582
Short name T156
Test name
Test status
Simulation time 171054017 ps
CPU time 1.33 seconds
Started Apr 02 12:29:06 PM PDT 24
Finished Apr 02 12:29:07 PM PDT 24
Peak memory 207296 kb
Host smart-53c6043c-7a5c-4436-8238-42dceccdd788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459979582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
459979582
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2023909003
Short name T836
Test name
Test status
Simulation time 24409094 ps
CPU time 0.72 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:16 PM PDT 24
Peak memory 203476 kb
Host smart-706da76a-462b-4a80-aaa0-432a668909a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023909003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
023909003
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.65055359
Short name T843
Test name
Test status
Simulation time 76444884 ps
CPU time 1.73 seconds
Started Apr 02 12:29:16 PM PDT 24
Finished Apr 02 12:29:18 PM PDT 24
Peak memory 215500 kb
Host smart-7e18f631-2536-4fa9-afb9-c138a8214f51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65055359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.65055359
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3622044373
Short name T855
Test name
Test status
Simulation time 39069265 ps
CPU time 0.68 seconds
Started Apr 02 12:29:22 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 203524 kb
Host smart-5aef0ec2-9291-427f-bf0b-169071d5ca21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622044373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3622044373
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1410935949
Short name T152
Test name
Test status
Simulation time 104663099 ps
CPU time 1.77 seconds
Started Apr 02 12:29:16 PM PDT 24
Finished Apr 02 12:29:18 PM PDT 24
Peak memory 215768 kb
Host smart-e4d3068b-74aa-4388-9465-596f47375211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410935949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1410935949
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4198092379
Short name T798
Test name
Test status
Simulation time 172031439 ps
CPU time 3.39 seconds
Started Apr 02 12:28:59 PM PDT 24
Finished Apr 02 12:29:02 PM PDT 24
Peak memory 215672 kb
Host smart-88f023fa-d592-49c6-9897-ee02fcce91c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198092379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
198092379
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.615193959
Short name T157
Test name
Test status
Simulation time 7111371158 ps
CPU time 15.3 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 215688 kb
Host smart-a4112eb6-f54e-475e-a1b4-4be13899fbc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615193959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.615193959
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3449197702
Short name T780
Test name
Test status
Simulation time 194451439 ps
CPU time 1.59 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 215684 kb
Host smart-525e118d-6419-4118-abb3-5e90d26bc4d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449197702 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3449197702
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1557383020
Short name T846
Test name
Test status
Simulation time 99312288 ps
CPU time 1.78 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215420 kb
Host smart-0ca07b10-bf1c-4578-aca0-af7e2e4b8b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557383020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1557383020
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4202243819
Short name T857
Test name
Test status
Simulation time 53998144 ps
CPU time 0.73 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:25 PM PDT 24
Peak memory 203776 kb
Host smart-0455b968-47d8-43fc-a029-cf7d632adcd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202243819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4202243819
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.199758807
Short name T842
Test name
Test status
Simulation time 435930268 ps
CPU time 3.15 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 215444 kb
Host smart-5c1c891d-6057-4ab1-b478-f77ade90e430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199758807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.199758807
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1506981832
Short name T114
Test name
Test status
Simulation time 357603719 ps
CPU time 4.77 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 215560 kb
Host smart-0e1595d9-547a-43e0-a58a-cac610877613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506981832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1506981832
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4269337436
Short name T172
Test name
Test status
Simulation time 311224116 ps
CPU time 6.77 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 216964 kb
Host smart-802da723-ce4f-4d34-bb80-5b0f33a3e02f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269337436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4269337436
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.840796876
Short name T766
Test name
Test status
Simulation time 89764942 ps
CPU time 2.44 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 216772 kb
Host smart-11818850-989e-4812-a091-2898173a40cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840796876 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.840796876
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.808110263
Short name T151
Test name
Test status
Simulation time 91927542 ps
CPU time 1.37 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 207232 kb
Host smart-bdb57ca9-053c-4b68-b023-556ae4a33b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808110263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.808110263
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1382481901
Short name T769
Test name
Test status
Simulation time 46393034 ps
CPU time 0.74 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:30 PM PDT 24
Peak memory 203492 kb
Host smart-57b7b27d-0c7d-40ee-a7a4-e892e09082af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382481901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1382481901
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1343150348
Short name T802
Test name
Test status
Simulation time 776684934 ps
CPU time 3.96 seconds
Started Apr 02 12:29:37 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 215604 kb
Host smart-c64c0c0b-bfec-47da-8f78-edd1391115d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343150348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1343150348
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1057258276
Short name T123
Test name
Test status
Simulation time 195034866 ps
CPU time 3.57 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215584 kb
Host smart-092bcee5-9edb-474a-b242-c98f91c9fba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057258276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1057258276
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3857923373
Short name T852
Test name
Test status
Simulation time 170690843 ps
CPU time 2.65 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 216636 kb
Host smart-a6bf963b-4847-4407-92a5-4af22b163236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857923373 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3857923373
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1189642044
Short name T150
Test name
Test status
Simulation time 446707576 ps
CPU time 2.21 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 215424 kb
Host smart-88c26a28-0f37-495f-9bc1-b49f6c14345f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189642044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1189642044
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4150695962
Short name T785
Test name
Test status
Simulation time 12124381 ps
CPU time 0.76 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 203772 kb
Host smart-9fb1b391-24df-4ae5-9459-5b2ba57b46b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150695962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4150695962
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1930723315
Short name T831
Test name
Test status
Simulation time 56090797 ps
CPU time 2.86 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 215504 kb
Host smart-f23b805e-f9e0-4fb8-a2cd-321b67798b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930723315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1930723315
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1702450150
Short name T115
Test name
Test status
Simulation time 68925870 ps
CPU time 1.51 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 215768 kb
Host smart-a186c727-5edb-4852-a49d-492f696462af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702450150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1702450150
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.370161276
Short name T368
Test name
Test status
Simulation time 878288540 ps
CPU time 22.98 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:52 PM PDT 24
Peak memory 215432 kb
Host smart-6e2a4dc1-c7f4-4a2a-a5a0-07dfe97d8c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370161276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.370161276
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3844236509
Short name T781
Test name
Test status
Simulation time 40611942 ps
CPU time 2.55 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 216964 kb
Host smart-ad8f976e-a746-4716-a406-f82a909e0f22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844236509 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3844236509
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.416586713
Short name T865
Test name
Test status
Simulation time 38748808 ps
CPU time 1.29 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 215460 kb
Host smart-d8ab1201-d056-405f-bceb-6e04868904f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416586713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.416586713
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.154854171
Short name T787
Test name
Test status
Simulation time 46299805 ps
CPU time 0.71 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 203752 kb
Host smart-7dcf2437-dcce-48ba-9824-38c053623a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154854171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.154854171
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3859723239
Short name T808
Test name
Test status
Simulation time 647065054 ps
CPU time 4.24 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 215476 kb
Host smart-eb33808d-1a48-499c-8c78-47ed64827fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859723239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3859723239
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.295189860
Short name T835
Test name
Test status
Simulation time 1586387798 ps
CPU time 3.71 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 215552 kb
Host smart-4b722ec5-a02b-47fe-ab75-da95765f33cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295189860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.295189860
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.844445775
Short name T813
Test name
Test status
Simulation time 405301096 ps
CPU time 12.5 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:49 PM PDT 24
Peak memory 215556 kb
Host smart-f33168bd-8023-4c24-b30a-587fa9ce4e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844445775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.844445775
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3651661881
Short name T806
Test name
Test status
Simulation time 544310580 ps
CPU time 3.41 seconds
Started Apr 02 12:29:34 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 217892 kb
Host smart-aa26dab1-01f6-4686-a150-857077150ba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651661881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3651661881
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4175291126
Short name T829
Test name
Test status
Simulation time 89468641 ps
CPU time 1.92 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 215488 kb
Host smart-b3e8f8c5-5f86-408e-a7b4-ef2ca67019e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175291126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4175291126
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3175404735
Short name T779
Test name
Test status
Simulation time 16790996 ps
CPU time 0.77 seconds
Started Apr 02 12:29:44 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 203800 kb
Host smart-a8e4c535-ce3c-4aff-8b74-b45dbdacf592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175404735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3175404735
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.563896469
Short name T129
Test name
Test status
Simulation time 406266758 ps
CPU time 2.58 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 215452 kb
Host smart-0fec24c1-20b9-4e5a-884e-fe844ce88401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563896469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.563896469
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.124495373
Short name T793
Test name
Test status
Simulation time 66589259 ps
CPU time 2.17 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215656 kb
Host smart-fed94a10-b27e-449b-b803-667dced36159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124495373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.124495373
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2722523676
Short name T841
Test name
Test status
Simulation time 575179742 ps
CPU time 15.06 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:51 PM PDT 24
Peak memory 215524 kb
Host smart-8fa8fb4c-f470-4890-b7df-8695666f2f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722523676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2722523676
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1664673969
Short name T771
Test name
Test status
Simulation time 26393743 ps
CPU time 1.77 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:46 PM PDT 24
Peak memory 215628 kb
Host smart-5f6ae445-0f4e-483d-8cc3-c41703165c47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664673969 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1664673969
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1855974579
Short name T143
Test name
Test status
Simulation time 202573493 ps
CPU time 1.46 seconds
Started Apr 02 12:29:33 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 215508 kb
Host smart-d6fc529f-7996-4cc8-b114-1dca102675d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855974579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1855974579
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1293121659
Short name T774
Test name
Test status
Simulation time 21181950 ps
CPU time 0.76 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 203432 kb
Host smart-ab049851-2325-40e3-a4ef-c6c5ca30ac44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293121659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1293121659
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4269908928
Short name T840
Test name
Test status
Simulation time 57860941 ps
CPU time 1.79 seconds
Started Apr 02 12:29:33 PM PDT 24
Finished Apr 02 12:29:34 PM PDT 24
Peak memory 215504 kb
Host smart-e019f6a8-efae-44af-901f-59ff91c173be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269908928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4269908928
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.240360908
Short name T868
Test name
Test status
Simulation time 352881465 ps
CPU time 4.49 seconds
Started Apr 02 12:29:28 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 216636 kb
Host smart-144c8ff8-0513-4a3b-8915-c763f144b0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240360908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.240360908
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2847595151
Short name T369
Test name
Test status
Simulation time 594565511 ps
CPU time 17.68 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:49 PM PDT 24
Peak memory 215552 kb
Host smart-c885ac12-f4e7-48f7-b9eb-6166221a73f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847595151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2847595151
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3303601090
Short name T796
Test name
Test status
Simulation time 104759725 ps
CPU time 3.64 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 217628 kb
Host smart-aa9e5322-0eda-41d8-a5ce-59d2507142ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303601090 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3303601090
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4079125207
Short name T149
Test name
Test status
Simulation time 114262610 ps
CPU time 1.2 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 207224 kb
Host smart-bbb8f34c-f380-4f19-8650-8fed2d77308a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079125207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4079125207
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2940979357
Short name T770
Test name
Test status
Simulation time 17912801 ps
CPU time 0.75 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 203472 kb
Host smart-21ee808c-8e28-4c9e-a830-9258094c3a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940979357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2940979357
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4092450397
Short name T845
Test name
Test status
Simulation time 55763332 ps
CPU time 3.42 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 215544 kb
Host smart-57f4d30f-133c-4f5e-81f8-3e5206b94e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092450397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4092450397
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3169317605
Short name T159
Test name
Test status
Simulation time 3943837984 ps
CPU time 21.07 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:58 PM PDT 24
Peak memory 215600 kb
Host smart-415751c9-6ba6-4a8a-9efe-ae7b89dcbe6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169317605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3169317605
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1964485351
Short name T817
Test name
Test status
Simulation time 59105045 ps
CPU time 2.76 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 216704 kb
Host smart-bb23d10a-118e-4286-8047-be2f46f6216f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964485351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1964485351
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1705607462
Short name T141
Test name
Test status
Simulation time 110838951 ps
CPU time 2.66 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 207236 kb
Host smart-43d47605-7020-45e0-af8f-c787bebdede9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705607462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1705607462
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.97700228
Short name T795
Test name
Test status
Simulation time 25900275 ps
CPU time 0.74 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 203228 kb
Host smart-783f6f23-b357-4986-82c3-e1689b04c996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97700228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.97700228
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2424927253
Short name T824
Test name
Test status
Simulation time 867235788 ps
CPU time 3.58 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 215496 kb
Host smart-8ea7daf8-9634-421d-bb26-f94f69df6e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424927253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2424927253
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1403761081
Short name T811
Test name
Test status
Simulation time 439281227 ps
CPU time 4.94 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:46 PM PDT 24
Peak memory 215564 kb
Host smart-e49f2557-e185-4a17-99eb-c13464e35375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403761081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1403761081
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.547381362
Short name T797
Test name
Test status
Simulation time 1419402530 ps
CPU time 7.83 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:51 PM PDT 24
Peak memory 215632 kb
Host smart-b4bc35df-6da7-4518-bf84-28ce2fc64f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547381362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.547381362
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2884036681
Short name T818
Test name
Test status
Simulation time 137324960 ps
CPU time 3.47 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 217536 kb
Host smart-366c87a5-589a-46d9-a422-88e307f4c55a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884036681 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2884036681
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1447073908
Short name T145
Test name
Test status
Simulation time 166169809 ps
CPU time 1.44 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 207204 kb
Host smart-2ae791ad-6d47-44c2-a5c9-ab5c01926739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447073908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1447073908
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.562569937
Short name T844
Test name
Test status
Simulation time 19674063 ps
CPU time 0.78 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 203444 kb
Host smart-a457c364-92e2-48ad-ac9f-e7f8cfd246d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562569937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.562569937
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3676135745
Short name T37
Test name
Test status
Simulation time 257612963 ps
CPU time 3 seconds
Started Apr 02 12:29:34 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 215480 kb
Host smart-bdd88b28-b1bc-4434-9d13-12909b659647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676135745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3676135745
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3072746493
Short name T116
Test name
Test status
Simulation time 635058360 ps
CPU time 4.18 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 215728 kb
Host smart-c4f59928-8fdc-43c0-a54f-fefe967faac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072746493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3072746493
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2350511001
Short name T121
Test name
Test status
Simulation time 284184661 ps
CPU time 7.36 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 215536 kb
Host smart-bc5f2c85-369d-4ffa-9399-434ed119e64b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350511001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2350511001
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.483086924
Short name T786
Test name
Test status
Simulation time 88242104 ps
CPU time 2.73 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:54 PM PDT 24
Peak memory 216628 kb
Host smart-6b43d178-6b52-4b21-8f23-20e327be7379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483086924 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.483086924
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.477514710
Short name T803
Test name
Test status
Simulation time 42002925 ps
CPU time 1.42 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:36 PM PDT 24
Peak memory 207300 kb
Host smart-ac92e4c0-4be2-46a9-90d0-bf094a540ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477514710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.477514710
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.546181805
Short name T754
Test name
Test status
Simulation time 12191779 ps
CPU time 0.69 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203468 kb
Host smart-789b265c-6263-49d9-85c4-decf906bde8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546181805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.546181805
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1561092448
Short name T837
Test name
Test status
Simulation time 160275016 ps
CPU time 4.12 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 215432 kb
Host smart-778aa8de-acae-4e25-a2c5-3a1645c2cca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561092448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1561092448
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3699754505
Short name T805
Test name
Test status
Simulation time 187470956 ps
CPU time 2.93 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 215532 kb
Host smart-c09ba52a-748e-4961-b8b9-6dd4acd89feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699754505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3699754505
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4205678193
Short name T367
Test name
Test status
Simulation time 200627732 ps
CPU time 11.78 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:53 PM PDT 24
Peak memory 215468 kb
Host smart-8b6492f5-06b1-47c6-86aa-77b6d4ae5d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205678193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4205678193
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1515994353
Short name T799
Test name
Test status
Simulation time 787444369 ps
CPU time 15.81 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 215464 kb
Host smart-c8facd47-89c7-4b72-9013-8a0404e9dd8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515994353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1515994353
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2765705838
Short name T137
Test name
Test status
Simulation time 355375968 ps
CPU time 22.1 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:46 PM PDT 24
Peak memory 207376 kb
Host smart-68007096-bb6b-4d2f-a85b-8497f5ccc996
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765705838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2765705838
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1735744900
Short name T792
Test name
Test status
Simulation time 213922702 ps
CPU time 1.24 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 207132 kb
Host smart-b654e0d8-7aaf-4211-b8e8-75c540f66c68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735744900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1735744900
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.721928419
Short name T850
Test name
Test status
Simulation time 191553991 ps
CPU time 1.77 seconds
Started Apr 02 12:29:30 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 215604 kb
Host smart-5c8a6bf7-8c67-4776-8acc-ea4f08f69685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721928419 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.721928419
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2157177017
Short name T788
Test name
Test status
Simulation time 47168964 ps
CPU time 1.47 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215428 kb
Host smart-eab16223-d337-42d2-a24c-b5760e42e3a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157177017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
157177017
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.201896782
Short name T164
Test name
Test status
Simulation time 17433680 ps
CPU time 0.75 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:24 PM PDT 24
Peak memory 203508 kb
Host smart-5bae7d06-0011-440a-801e-ffeeb72769ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201896782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.201896782
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3305076691
Short name T136
Test name
Test status
Simulation time 448344101 ps
CPU time 2.1 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:23 PM PDT 24
Peak memory 215616 kb
Host smart-18ebe713-e277-45e4-a92c-8197a71f7bbc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305076691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3305076691
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2233922051
Short name T860
Test name
Test status
Simulation time 13322965 ps
CPU time 0.66 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 203820 kb
Host smart-241df008-b5e4-4037-a579-42e0b31c2681
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233922051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2233922051
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.52040393
Short name T153
Test name
Test status
Simulation time 212384209 ps
CPU time 2.72 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215552 kb
Host smart-0fdc0c4b-da63-4aab-8fe4-be093ff12a5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52040393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_same_csr_outstanding.52040393
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1895976142
Short name T133
Test name
Test status
Simulation time 502568511 ps
CPU time 1.87 seconds
Started Apr 02 12:29:09 PM PDT 24
Finished Apr 02 12:29:11 PM PDT 24
Peak memory 215588 kb
Host smart-34aa5619-e082-42d8-819d-af6fec7bd5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895976142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
895976142
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3192986481
Short name T762
Test name
Test status
Simulation time 62742694 ps
CPU time 0.75 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 203460 kb
Host smart-9623f93b-f4eb-420c-8f49-2225ac8eff83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192986481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3192986481
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3012931555
Short name T832
Test name
Test status
Simulation time 25122497 ps
CPU time 0.73 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 203560 kb
Host smart-7636e5ab-ddb8-4889-9cd7-cddd8914c534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012931555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3012931555
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3023248582
Short name T870
Test name
Test status
Simulation time 14115330 ps
CPU time 0.72 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 203844 kb
Host smart-7138ea21-becf-4358-86da-dd24192fd064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023248582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3023248582
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1478816290
Short name T768
Test name
Test status
Simulation time 14729834 ps
CPU time 0.74 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 203904 kb
Host smart-a519d25f-cb1e-4f4b-8be4-5fd752076c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478816290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1478816290
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1044062471
Short name T814
Test name
Test status
Simulation time 68538105 ps
CPU time 0.81 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 203504 kb
Host smart-1be28793-18b2-4cb4-814e-c9f1af1681eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044062471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1044062471
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.447910670
Short name T783
Test name
Test status
Simulation time 22916142 ps
CPU time 0.72 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203444 kb
Host smart-8749f048-01d2-4dc4-9778-dd272075c9b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447910670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.447910670
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3189903128
Short name T755
Test name
Test status
Simulation time 15707445 ps
CPU time 0.76 seconds
Started Apr 02 12:29:37 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 203500 kb
Host smart-a06f399d-282b-44da-9738-c50bbd87fad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189903128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3189903128
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2544754221
Short name T763
Test name
Test status
Simulation time 26820465 ps
CPU time 0.75 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 203536 kb
Host smart-76a6f5e1-648a-4270-bf75-d3efc84434a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544754221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2544754221
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.704088787
Short name T761
Test name
Test status
Simulation time 48278557 ps
CPU time 0.77 seconds
Started Apr 02 12:29:34 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 203544 kb
Host smart-0796134e-6211-4ae4-a33a-1ab25b47e358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704088787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.704088787
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2382325613
Short name T864
Test name
Test status
Simulation time 13396861 ps
CPU time 0.69 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:36 PM PDT 24
Peak memory 203496 kb
Host smart-acff5980-6453-42ed-ac67-61e8bcde6554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382325613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2382325613
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3422384798
Short name T144
Test name
Test status
Simulation time 608645601 ps
CPU time 16.3 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:37 PM PDT 24
Peak memory 215436 kb
Host smart-741e19c6-7764-480c-8e0b-7418067b53e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422384798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3422384798
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2233603915
Short name T810
Test name
Test status
Simulation time 1046429469 ps
CPU time 32.33 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:58 PM PDT 24
Peak memory 206976 kb
Host smart-a689b286-451f-42b5-ad75-40b8a8d81ce9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233603915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2233603915
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1989565089
Short name T100
Test name
Test status
Simulation time 20018179 ps
CPU time 1.2 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 207188 kb
Host smart-219bbe04-5716-43de-afc5-689f0b8c9dd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989565089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1989565089
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.573103368
Short name T827
Test name
Test status
Simulation time 104443834 ps
CPU time 1.71 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 215616 kb
Host smart-8c4bf655-90a2-4dc9-a10b-fd4416a3d859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573103368 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.573103368
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1859135465
Short name T812
Test name
Test status
Simulation time 163238794 ps
CPU time 1.26 seconds
Started Apr 02 12:29:33 PM PDT 24
Finished Apr 02 12:29:34 PM PDT 24
Peak memory 215396 kb
Host smart-c9624596-abdb-42f3-befd-759a906ac6e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859135465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
859135465
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.694858870
Short name T773
Test name
Test status
Simulation time 10745165 ps
CPU time 0.74 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 203760 kb
Host smart-0c36769b-1faf-4761-9e4a-46045e78359e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694858870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.694858870
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1621152181
Short name T147
Test name
Test status
Simulation time 18775080 ps
CPU time 1.24 seconds
Started Apr 02 12:29:28 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215524 kb
Host smart-042de99b-cb9d-47a4-80e8-d81c7d0bd887
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621152181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1621152181
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1710522583
Short name T851
Test name
Test status
Simulation time 57774514 ps
CPU time 0.68 seconds
Started Apr 02 12:29:18 PM PDT 24
Finished Apr 02 12:29:19 PM PDT 24
Peak memory 203824 kb
Host smart-86bc51ff-0a20-4a61-8106-a0ab491bd1ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710522583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1710522583
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2010165026
Short name T819
Test name
Test status
Simulation time 862776131 ps
CPU time 4.34 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215224 kb
Host smart-a5c96061-c232-4f4c-9658-fbd5ce2c12b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010165026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2010165026
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1793013956
Short name T35
Test name
Test status
Simulation time 105263576 ps
CPU time 7.06 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:30 PM PDT 24
Peak memory 215516 kb
Host smart-39df0b02-42cc-4390-bf21-b6738e551a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793013956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1793013956
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1565844015
Short name T794
Test name
Test status
Simulation time 13593044 ps
CPU time 0.69 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 203524 kb
Host smart-30af4052-dab0-47aa-bc01-e9dc2f6e752c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565844015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1565844015
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3095808646
Short name T756
Test name
Test status
Simulation time 27385675 ps
CPU time 0.77 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:01 PM PDT 24
Peak memory 203804 kb
Host smart-363c97de-6559-48b4-b126-fe8f5e102a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095808646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3095808646
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.267673310
Short name T166
Test name
Test status
Simulation time 36936187 ps
CPU time 0.77 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 203796 kb
Host smart-57f01875-022d-494c-b902-eababa3ffbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267673310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.267673310
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.332650067
Short name T778
Test name
Test status
Simulation time 19434886 ps
CPU time 0.71 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:47 PM PDT 24
Peak memory 203432 kb
Host smart-3ae028d9-9533-49be-ab97-6257a3e82992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332650067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.332650067
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1034020694
Short name T862
Test name
Test status
Simulation time 13826473 ps
CPU time 0.69 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 203900 kb
Host smart-fed81bbe-86ad-4531-a129-f8afe90db987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034020694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1034020694
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.965311287
Short name T839
Test name
Test status
Simulation time 16329229 ps
CPU time 0.74 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 203628 kb
Host smart-3859d44f-31b9-4446-befb-af1aa96588bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965311287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.965311287
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1829405150
Short name T822
Test name
Test status
Simulation time 53966057 ps
CPU time 0.74 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 203824 kb
Host smart-94aa59d0-c163-4ab5-83e9-7e0fb4c9233a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829405150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1829405150
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2423101630
Short name T828
Test name
Test status
Simulation time 14023266 ps
CPU time 0.76 seconds
Started Apr 02 12:29:44 PM PDT 24
Finished Apr 02 12:29:46 PM PDT 24
Peak memory 203540 kb
Host smart-192e44c4-30b9-4fcf-b441-7d14a5dfe848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423101630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2423101630
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3101158061
Short name T777
Test name
Test status
Simulation time 21700351 ps
CPU time 0.7 seconds
Started Apr 02 12:29:42 PM PDT 24
Finished Apr 02 12:29:43 PM PDT 24
Peak memory 203428 kb
Host smart-b823b9fa-dc4a-4709-8552-d1339d603220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101158061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3101158061
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3794377162
Short name T790
Test name
Test status
Simulation time 14293755 ps
CPU time 0.67 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:36 PM PDT 24
Peak memory 203772 kb
Host smart-96351408-e822-434e-96ff-1c12ff0270f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794377162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3794377162
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.575192962
Short name T138
Test name
Test status
Simulation time 303392770 ps
CPU time 19.97 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:46 PM PDT 24
Peak memory 215456 kb
Host smart-9e2a08a4-d66f-4e0b-9c52-b99f5508e333
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575192962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.575192962
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.25585646
Short name T825
Test name
Test status
Simulation time 1277595837 ps
CPU time 13.27 seconds
Started Apr 02 12:29:37 PM PDT 24
Finished Apr 02 12:29:50 PM PDT 24
Peak memory 207236 kb
Host smart-943c63b8-a088-4619-85be-fdc2fadb71e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25585646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.25585646
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.935370273
Short name T853
Test name
Test status
Simulation time 38065747 ps
CPU time 2.43 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:18 PM PDT 24
Peak memory 217860 kb
Host smart-2c5e16fd-c2e0-4a48-8e67-a721bd337ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935370273 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.935370273
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2292653670
Short name T140
Test name
Test status
Simulation time 257855995 ps
CPU time 1.87 seconds
Started Apr 02 12:29:28 PM PDT 24
Finished Apr 02 12:29:30 PM PDT 24
Peak memory 215416 kb
Host smart-c979eefd-8e3f-4a8d-bd28-59561629b6e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292653670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
292653670
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3304015582
Short name T760
Test name
Test status
Simulation time 57551950 ps
CPU time 0.75 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 203496 kb
Host smart-3029f256-beee-4db1-ad2f-05b2ec865784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304015582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
304015582
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.279865136
Short name T847
Test name
Test status
Simulation time 86547693 ps
CPU time 1.92 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215580 kb
Host smart-f4f15597-a15d-4784-950a-23f6975a8f9a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279865136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.279865136
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.74465781
Short name T784
Test name
Test status
Simulation time 13864029 ps
CPU time 0.66 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 203544 kb
Host smart-ecb5a7cc-37f9-4957-8a14-4a4dd1375853
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74465781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_
walk.74465781
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1881566593
Short name T791
Test name
Test status
Simulation time 3051554365 ps
CPU time 4.22 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 215500 kb
Host smart-4628d471-1b80-45b9-befe-fb9f89fe10aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881566593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1881566593
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.386246426
Short name T830
Test name
Test status
Simulation time 152856233 ps
CPU time 4.35 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 215660 kb
Host smart-a5ed2273-4add-4020-a21f-60236c1f1a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386246426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.386246426
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.991219724
Short name T371
Test name
Test status
Simulation time 1188689125 ps
CPU time 7.83 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 215568 kb
Host smart-40c8345b-9fbe-484a-8fe1-70d5fe2bcaf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991219724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.991219724
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.350580602
Short name T823
Test name
Test status
Simulation time 19627696 ps
CPU time 0.7 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 203852 kb
Host smart-56c3a67e-b3a6-4dd1-ab3b-946d03b8bd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350580602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.350580602
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.486728774
Short name T767
Test name
Test status
Simulation time 36827905 ps
CPU time 0.68 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203492 kb
Host smart-5af36925-2abb-4080-bc09-1127fad5c4f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486728774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.486728774
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1941542482
Short name T165
Test name
Test status
Simulation time 18078743 ps
CPU time 0.74 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203508 kb
Host smart-fc93e9b3-a288-4da7-b850-109d1b88d422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941542482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1941542482
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.346228604
Short name T758
Test name
Test status
Simulation time 40002693 ps
CPU time 0.73 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203488 kb
Host smart-7692cb1e-4b06-44d9-a539-1d6a5b0cf31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346228604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.346228604
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3982600962
Short name T866
Test name
Test status
Simulation time 13300477 ps
CPU time 0.74 seconds
Started Apr 02 12:29:42 PM PDT 24
Finished Apr 02 12:29:43 PM PDT 24
Peak memory 203560 kb
Host smart-2b56d210-697a-4de8-a0dd-f554b51bdf24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982600962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3982600962
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1975488600
Short name T775
Test name
Test status
Simulation time 16685699 ps
CPU time 0.72 seconds
Started Apr 02 12:29:34 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 203504 kb
Host smart-d95871e1-add1-40df-b13c-147f41722b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975488600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1975488600
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.375993220
Short name T820
Test name
Test status
Simulation time 33165298 ps
CPU time 0.7 seconds
Started Apr 02 12:29:43 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 203880 kb
Host smart-d41c2171-ae22-4006-b1e0-548659f2be1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375993220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.375993220
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.727535808
Short name T807
Test name
Test status
Simulation time 18077196 ps
CPU time 0.7 seconds
Started Apr 02 12:29:41 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 203748 kb
Host smart-5a06137a-f56f-4a3f-88f0-18917fc6c91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727535808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.727535808
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3911823327
Short name T776
Test name
Test status
Simulation time 50682625 ps
CPU time 0.75 seconds
Started Apr 02 12:30:01 PM PDT 24
Finished Apr 02 12:30:01 PM PDT 24
Peak memory 203504 kb
Host smart-10fa392a-c4ba-4488-bc5b-5f9ed6b8898d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911823327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3911823327
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2257369724
Short name T858
Test name
Test status
Simulation time 20265047 ps
CPU time 0.71 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:36 PM PDT 24
Peak memory 203836 kb
Host smart-a44d4e20-464c-4976-a9ab-7812a39b5ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257369724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2257369724
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2094807018
Short name T134
Test name
Test status
Simulation time 164944766 ps
CPU time 2.74 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:26 PM PDT 24
Peak memory 216788 kb
Host smart-37e964ab-18ef-4efc-982b-677bad2623e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094807018 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2094807018
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1087061662
Short name T142
Test name
Test status
Simulation time 56881100 ps
CPU time 1.91 seconds
Started Apr 02 12:29:16 PM PDT 24
Finished Apr 02 12:29:18 PM PDT 24
Peak memory 215472 kb
Host smart-147727e4-3e53-4422-ae8e-7b24a12e7ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087061662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
087061662
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1619602920
Short name T772
Test name
Test status
Simulation time 28701308 ps
CPU time 0.73 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:21 PM PDT 24
Peak memory 203744 kb
Host smart-4370cd15-e61a-455d-bf21-9280edb46bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619602920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
619602920
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2309736779
Short name T834
Test name
Test status
Simulation time 118703890 ps
CPU time 2.88 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215500 kb
Host smart-3c44cee3-d935-4124-bc79-64b791f559af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309736779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2309736779
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.727925772
Short name T838
Test name
Test status
Simulation time 98147257 ps
CPU time 1.72 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:23 PM PDT 24
Peak memory 215740 kb
Host smart-ae81551c-b649-488d-b20d-9a5eb75fa58a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727925772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.727925772
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2017688968
Short name T765
Test name
Test status
Simulation time 311481244 ps
CPU time 2.54 seconds
Started Apr 02 12:29:19 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 216664 kb
Host smart-0f4c5cd0-8c78-4a88-a590-71e25d295424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017688968 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2017688968
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3335386691
Short name T757
Test name
Test status
Simulation time 36407798 ps
CPU time 0.75 seconds
Started Apr 02 12:29:32 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 203480 kb
Host smart-33590a57-5bc8-4f18-ac28-197d75376576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335386691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
335386691
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1663204886
Short name T36
Test name
Test status
Simulation time 900631523 ps
CPU time 4.2 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215520 kb
Host smart-08a00e84-14e9-48db-954c-edee885ceb0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663204886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1663204886
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3934569115
Short name T849
Test name
Test status
Simulation time 41699599 ps
CPU time 3.21 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 215744 kb
Host smart-68b7169b-17de-4c22-892b-a485e7a11b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934569115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
934569115
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3611614740
Short name T833
Test name
Test status
Simulation time 294058720 ps
CPU time 16.58 seconds
Started Apr 02 12:29:42 PM PDT 24
Finished Apr 02 12:29:59 PM PDT 24
Peak memory 215404 kb
Host smart-df98f6f4-e10d-4406-bc6a-fac8356bf49d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611614740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3611614740
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3489317987
Short name T801
Test name
Test status
Simulation time 66508551 ps
CPU time 2.75 seconds
Started Apr 02 12:29:09 PM PDT 24
Finished Apr 02 12:29:12 PM PDT 24
Peak memory 216976 kb
Host smart-f2dce939-88c2-44de-937b-fb832490fd01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489317987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3489317987
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1408987483
Short name T146
Test name
Test status
Simulation time 18346043 ps
CPU time 1.18 seconds
Started Apr 02 12:29:22 PM PDT 24
Finished Apr 02 12:29:23 PM PDT 24
Peak memory 207280 kb
Host smart-eaa5114e-8537-41ff-ae48-9bf23bf1f491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408987483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
408987483
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3890804089
Short name T856
Test name
Test status
Simulation time 15236623 ps
CPU time 0.7 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:24 PM PDT 24
Peak memory 203540 kb
Host smart-c55f7b76-e9fc-440d-a3b3-d3820fac780a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890804089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
890804089
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2785440127
Short name T158
Test name
Test status
Simulation time 85608319 ps
CPU time 2 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:40 PM PDT 24
Peak memory 215548 kb
Host smart-458a27b6-f9d1-403b-a259-2ff837e50123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785440127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2785440127
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2045700760
Short name T859
Test name
Test status
Simulation time 450330736 ps
CPU time 5.18 seconds
Started Apr 02 12:29:36 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 219692 kb
Host smart-a5f0790c-b0ba-4e65-9e60-22a49572807e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045700760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
045700760
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.149182883
Short name T365
Test name
Test status
Simulation time 337720023 ps
CPU time 19.58 seconds
Started Apr 02 12:29:33 PM PDT 24
Finished Apr 02 12:29:52 PM PDT 24
Peak memory 215572 kb
Host smart-1ebead4d-2a0e-446b-9704-61c8ddefd443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149182883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.149182883
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2759336617
Short name T815
Test name
Test status
Simulation time 130087115 ps
CPU time 2.62 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:41 PM PDT 24
Peak memory 216928 kb
Host smart-bc480e3b-c241-49ee-b311-4e7bc8a7000a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759336617 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2759336617
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1921822583
Short name T816
Test name
Test status
Simulation time 38568680 ps
CPU time 2.47 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215416 kb
Host smart-b3d5fe13-9d27-4aa3-a6e8-91da1db924df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921822583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
921822583
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2294278527
Short name T759
Test name
Test status
Simulation time 35576661 ps
CPU time 0.74 seconds
Started Apr 02 12:29:30 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 203508 kb
Host smart-3c898e42-f599-4e72-9d98-6c91a8530bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294278527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
294278527
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.750965758
Short name T854
Test name
Test status
Simulation time 311589664 ps
CPU time 3.98 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 215528 kb
Host smart-0d860f42-bc3c-40d6-bbaf-3431f98cf130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750965758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.750965758
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3420588450
Short name T128
Test name
Test status
Simulation time 40418556 ps
CPU time 3.18 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 215700 kb
Host smart-81363b7b-16b3-49ef-a130-a0c47a1c5322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420588450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
420588450
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3112100225
Short name T370
Test name
Test status
Simulation time 549650548 ps
CPU time 13.92 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:53 PM PDT 24
Peak memory 215520 kb
Host smart-1d813196-d6a4-44c6-8cb3-36296fa7db4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112100225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3112100225
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3458717988
Short name T863
Test name
Test status
Simulation time 25517257 ps
CPU time 1.76 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 215680 kb
Host smart-66f6fe68-8e64-4590-bd79-edc62cb70343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458717988 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3458717988
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2958499125
Short name T821
Test name
Test status
Simulation time 40001860 ps
CPU time 2.51 seconds
Started Apr 02 12:29:40 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 215440 kb
Host smart-b38272ce-3204-41ad-8e17-2497015cae0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958499125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
958499125
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1962551374
Short name T826
Test name
Test status
Simulation time 24899566 ps
CPU time 0.71 seconds
Started Apr 02 12:29:31 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 203452 kb
Host smart-59caac65-35b1-4ec4-8124-ea55b5ca1159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962551374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
962551374
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.724990679
Short name T764
Test name
Test status
Simulation time 301807492 ps
CPU time 3.94 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 215480 kb
Host smart-fab20feb-bc3e-47a3-9f70-7e1f797a36b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724990679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.724990679
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3335876446
Short name T132
Test name
Test status
Simulation time 319399441 ps
CPU time 5.73 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 215664 kb
Host smart-4aa20af8-3851-4b84-b5fa-a1d209997529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335876446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
335876446
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1519988522
Short name T869
Test name
Test status
Simulation time 636242693 ps
CPU time 17.89 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:57 PM PDT 24
Peak memory 215584 kb
Host smart-63e997d1-30d5-4c66-a575-a7ce399a7ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519988522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1519988522
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2917465398
Short name T458
Test name
Test status
Simulation time 28684722 ps
CPU time 0.73 seconds
Started Apr 02 02:02:26 PM PDT 24
Finished Apr 02 02:02:27 PM PDT 24
Peak memory 206460 kb
Host smart-7a260361-35f6-45eb-a792-efd7ada0d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917465398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2917465398
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2814853249
Short name T597
Test name
Test status
Simulation time 6624087079 ps
CPU time 29.9 seconds
Started Apr 02 02:02:50 PM PDT 24
Finished Apr 02 02:03:21 PM PDT 24
Peak memory 253768 kb
Host smart-19df2853-b416-4e4c-9208-8182987139a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814853249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2814853249
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.85714751
Short name T313
Test name
Test status
Simulation time 3313625866 ps
CPU time 42.02 seconds
Started Apr 02 02:02:45 PM PDT 24
Finished Apr 02 02:03:27 PM PDT 24
Peak memory 216636 kb
Host smart-9fec7a95-a43c-448f-820c-3deaa413ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85714751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.85714751
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.571918021
Short name T616
Test name
Test status
Simulation time 94122338 ps
CPU time 1 seconds
Started Apr 02 02:02:28 PM PDT 24
Finished Apr 02 02:02:29 PM PDT 24
Peak memory 218052 kb
Host smart-ab0eeb40-dcd7-4e40-b855-870a808ec186
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571918021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.571918021
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1193882134
Short name T209
Test name
Test status
Simulation time 10722296705 ps
CPU time 11.1 seconds
Started Apr 02 02:02:43 PM PDT 24
Finished Apr 02 02:02:54 PM PDT 24
Peak memory 224624 kb
Host smart-d6b6b142-d618-4bdc-ab1b-95cdf7c18aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193882134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1193882134
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1871633563
Short name T732
Test name
Test status
Simulation time 63987978 ps
CPU time 0.7 seconds
Started Apr 02 02:02:30 PM PDT 24
Finished Apr 02 02:02:31 PM PDT 24
Peak memory 216292 kb
Host smart-759f012e-4913-4753-9664-0b508f185196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871633563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1871633563
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1293880420
Short name T601
Test name
Test status
Simulation time 2534709567 ps
CPU time 6.99 seconds
Started Apr 02 02:02:49 PM PDT 24
Finished Apr 02 02:02:57 PM PDT 24
Peak memory 221628 kb
Host smart-1bcfb5f7-99f2-459a-b238-96f00ceb95c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1293880420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1293880420
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1866034619
Short name T163
Test name
Test status
Simulation time 85297343 ps
CPU time 0.94 seconds
Started Apr 02 02:02:52 PM PDT 24
Finished Apr 02 02:02:53 PM PDT 24
Peak memory 206948 kb
Host smart-88f8f98c-ba5b-4651-93e9-fffe6f05d1d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866034619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1866034619
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3183321687
Short name T701
Test name
Test status
Simulation time 804358666 ps
CPU time 1.99 seconds
Started Apr 02 02:02:38 PM PDT 24
Finished Apr 02 02:02:41 PM PDT 24
Peak memory 207768 kb
Host smart-6d933256-e06a-4174-9a54-20d3a46cb5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183321687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3183321687
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3779602922
Short name T669
Test name
Test status
Simulation time 62604195 ps
CPU time 0.84 seconds
Started Apr 02 02:02:39 PM PDT 24
Finished Apr 02 02:02:40 PM PDT 24
Peak memory 207096 kb
Host smart-4eb4aafa-ed77-4b7c-a77f-f301fd8fae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779602922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3779602922
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2318817013
Short name T598
Test name
Test status
Simulation time 26177269 ps
CPU time 0.69 seconds
Started Apr 02 02:02:38 PM PDT 24
Finished Apr 02 02:02:39 PM PDT 24
Peak memory 205752 kb
Host smart-932c635f-f417-4d8e-ad45-141e873b4075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318817013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2318817013
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4246869069
Short name T711
Test name
Test status
Simulation time 137883141 ps
CPU time 2.61 seconds
Started Apr 02 02:02:47 PM PDT 24
Finished Apr 02 02:02:50 PM PDT 24
Peak memory 222196 kb
Host smart-0a2141e6-2fd0-4d45-a64d-b6ec289aef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246869069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4246869069
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.999252067
Short name T493
Test name
Test status
Simulation time 20566054 ps
CPU time 0.67 seconds
Started Apr 02 02:03:14 PM PDT 24
Finished Apr 02 02:03:15 PM PDT 24
Peak memory 205260 kb
Host smart-848e3e37-3264-44f3-9785-a878fe4fcf92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999252067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.999252067
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4016248364
Short name T404
Test name
Test status
Simulation time 21381184 ps
CPU time 0.78 seconds
Started Apr 02 02:02:58 PM PDT 24
Finished Apr 02 02:02:59 PM PDT 24
Peak memory 206480 kb
Host smart-78f96cec-c658-468c-88a8-d6e7ce7edd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016248364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4016248364
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2956553605
Short name T304
Test name
Test status
Simulation time 6465881678 ps
CPU time 42.09 seconds
Started Apr 02 02:03:10 PM PDT 24
Finished Apr 02 02:03:53 PM PDT 24
Peak memory 257352 kb
Host smart-d78cd633-fd07-438d-b527-18571c856758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956553605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2956553605
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1412477131
Short name T206
Test name
Test status
Simulation time 1391006431 ps
CPU time 13.15 seconds
Started Apr 02 02:03:05 PM PDT 24
Finished Apr 02 02:03:19 PM PDT 24
Peak memory 236328 kb
Host smart-0a659602-5c58-41a8-9df1-f70b1e8cae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412477131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1412477131
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.322484632
Short name T11
Test name
Test status
Simulation time 129666729 ps
CPU time 2.81 seconds
Started Apr 02 02:03:01 PM PDT 24
Finished Apr 02 02:03:04 PM PDT 24
Peak memory 218844 kb
Host smart-46c8ae27-b2df-49ca-9a49-05bc301ca9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322484632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.322484632
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.360136809
Short name T499
Test name
Test status
Simulation time 1406147147 ps
CPU time 5.77 seconds
Started Apr 02 02:03:12 PM PDT 24
Finished Apr 02 02:03:18 PM PDT 24
Peak memory 220300 kb
Host smart-fe98ea02-911e-41a6-81bf-1dafd6bcf191
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=360136809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.360136809
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2907980804
Short name T51
Test name
Test status
Simulation time 147083828 ps
CPU time 0.92 seconds
Started Apr 02 02:03:14 PM PDT 24
Finished Apr 02 02:03:15 PM PDT 24
Peak memory 234452 kb
Host smart-5eff162f-206b-4f64-8bd8-2cac5718917f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907980804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2907980804
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2568136384
Short name T504
Test name
Test status
Simulation time 1904995542 ps
CPU time 7.72 seconds
Started Apr 02 02:03:02 PM PDT 24
Finished Apr 02 02:03:10 PM PDT 24
Peak memory 216288 kb
Host smart-a6d990a0-9a29-41e2-84a1-516a69762900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568136384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2568136384
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3613646836
Short name T416
Test name
Test status
Simulation time 297412019 ps
CPU time 1.44 seconds
Started Apr 02 02:03:03 PM PDT 24
Finished Apr 02 02:03:05 PM PDT 24
Peak memory 216436 kb
Host smart-abac2ae6-1dcf-4a5e-b9b6-847d6ac4f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613646836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3613646836
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3094715390
Short name T538
Test name
Test status
Simulation time 49721564 ps
CPU time 0.81 seconds
Started Apr 02 02:03:03 PM PDT 24
Finished Apr 02 02:03:04 PM PDT 24
Peak memory 205740 kb
Host smart-21885ba0-0ee4-488b-9f89-ed8de0d82741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094715390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3094715390
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3658519974
Short name T745
Test name
Test status
Simulation time 38231627 ps
CPU time 0.74 seconds
Started Apr 02 02:05:00 PM PDT 24
Finished Apr 02 02:05:02 PM PDT 24
Peak memory 205332 kb
Host smart-165ad7ed-8839-4d8f-8333-d2b16bbdf663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658519974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3658519974
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4034593377
Short name T405
Test name
Test status
Simulation time 78187261 ps
CPU time 0.76 seconds
Started Apr 02 02:04:50 PM PDT 24
Finished Apr 02 02:04:52 PM PDT 24
Peak memory 206488 kb
Host smart-501b07b3-ff94-46ad-9a8b-628921f5a386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034593377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4034593377
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1747828253
Short name T559
Test name
Test status
Simulation time 796992861 ps
CPU time 15.49 seconds
Started Apr 02 02:05:01 PM PDT 24
Finished Apr 02 02:05:17 PM PDT 24
Peak memory 224616 kb
Host smart-413fb003-1a52-4f26-98d1-349cb76b6500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747828253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1747828253
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1657893352
Short name T199
Test name
Test status
Simulation time 493689642 ps
CPU time 7.54 seconds
Started Apr 02 02:04:55 PM PDT 24
Finished Apr 02 02:05:03 PM PDT 24
Peak memory 221124 kb
Host smart-e622503e-b86a-44b9-b8b1-d12d8c44b30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657893352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1657893352
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3712591236
Short name T33
Test name
Test status
Simulation time 186794863 ps
CPU time 0.98 seconds
Started Apr 02 02:04:54 PM PDT 24
Finished Apr 02 02:04:56 PM PDT 24
Peak memory 218024 kb
Host smart-de36a462-63c5-4a41-8bb2-148ceeb22c08
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712591236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3712591236
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2761600873
Short name T437
Test name
Test status
Simulation time 102911155 ps
CPU time 0.71 seconds
Started Apr 02 02:04:55 PM PDT 24
Finished Apr 02 02:04:56 PM PDT 24
Peak memory 216288 kb
Host smart-2275f16d-15bd-468a-8a06-b43c399f5be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761600873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2761600873
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1064439727
Short name T155
Test name
Test status
Simulation time 152112983 ps
CPU time 4.58 seconds
Started Apr 02 02:04:59 PM PDT 24
Finished Apr 02 02:05:05 PM PDT 24
Peak memory 222816 kb
Host smart-8a4f626c-8cd0-4622-8a04-b3c498ea6abf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1064439727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1064439727
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.339962940
Short name T676
Test name
Test status
Simulation time 5423085925 ps
CPU time 3.67 seconds
Started Apr 02 02:04:54 PM PDT 24
Finished Apr 02 02:04:59 PM PDT 24
Peak memory 216324 kb
Host smart-777b1d70-e3b3-4cf7-ba98-0c359f99079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339962940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.339962940
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3967088443
Short name T592
Test name
Test status
Simulation time 15509791 ps
CPU time 0.98 seconds
Started Apr 02 02:04:55 PM PDT 24
Finished Apr 02 02:05:00 PM PDT 24
Peak memory 207232 kb
Host smart-57e8c9cb-3ec2-4b49-81b0-84432d9d3b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967088443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3967088443
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3490562681
Short name T498
Test name
Test status
Simulation time 67263945 ps
CPU time 0.7 seconds
Started Apr 02 02:04:56 PM PDT 24
Finished Apr 02 02:05:00 PM PDT 24
Peak memory 205748 kb
Host smart-4a01bf00-71da-42e8-9708-1286127defa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490562681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3490562681
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3827853104
Short name T357
Test name
Test status
Simulation time 10974143589 ps
CPU time 20.17 seconds
Started Apr 02 02:04:58 PM PDT 24
Finished Apr 02 02:05:19 PM PDT 24
Peak memory 219660 kb
Host smart-205cd38d-802c-4f49-a1f1-f02a2582f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827853104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3827853104
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2150451425
Short name T465
Test name
Test status
Simulation time 33139647 ps
CPU time 0.68 seconds
Started Apr 02 02:05:08 PM PDT 24
Finished Apr 02 02:05:09 PM PDT 24
Peak memory 204776 kb
Host smart-2cacadce-88f5-44c1-bd72-daf880a9fd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150451425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2150451425
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3581955070
Short name T491
Test name
Test status
Simulation time 23178649 ps
CPU time 0.78 seconds
Started Apr 02 02:05:03 PM PDT 24
Finished Apr 02 02:05:04 PM PDT 24
Peak memory 206708 kb
Host smart-21cd572a-6074-402f-8f59-57be6b976c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581955070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3581955070
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1657325015
Short name T361
Test name
Test status
Simulation time 1430379554 ps
CPU time 15.25 seconds
Started Apr 02 02:05:06 PM PDT 24
Finished Apr 02 02:05:22 PM PDT 24
Peak memory 224628 kb
Host smart-4805d337-89b9-44c4-8901-4f621c0c1ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657325015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1657325015
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2112633332
Short name T287
Test name
Test status
Simulation time 2334761408 ps
CPU time 8.12 seconds
Started Apr 02 02:05:09 PM PDT 24
Finished Apr 02 02:05:17 PM PDT 24
Peak memory 223644 kb
Host smart-487ad969-dfb5-4ed9-91aa-f1d1fcbd45d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112633332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2112633332
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1914866689
Short name T246
Test name
Test status
Simulation time 10666169821 ps
CPU time 12.94 seconds
Started Apr 02 02:05:09 PM PDT 24
Finished Apr 02 02:05:22 PM PDT 24
Peak memory 223964 kb
Host smart-be72b389-0297-4e37-bfa1-6422613062d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914866689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1914866689
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.479947520
Short name T739
Test name
Test status
Simulation time 15751118 ps
CPU time 1.01 seconds
Started Apr 02 02:04:58 PM PDT 24
Finished Apr 02 02:05:00 PM PDT 24
Peak memory 216836 kb
Host smart-6f7a908c-a1ab-49ad-b136-60dc8424d4a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479947520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.479947520
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1021563818
Short name T600
Test name
Test status
Simulation time 819100868 ps
CPU time 6.15 seconds
Started Apr 02 02:05:03 PM PDT 24
Finished Apr 02 02:05:09 PM PDT 24
Peak memory 223120 kb
Host smart-e81dfd37-33cd-4c01-86d2-a9f38aa279f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021563818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1021563818
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3253324648
Short name T428
Test name
Test status
Simulation time 45126739 ps
CPU time 0.77 seconds
Started Apr 02 02:05:03 PM PDT 24
Finished Apr 02 02:05:03 PM PDT 24
Peak memory 216288 kb
Host smart-c91dc279-c56d-4b5c-b62a-751581c8fc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253324648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3253324648
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1368352946
Short name T98
Test name
Test status
Simulation time 2033939016 ps
CPU time 7.55 seconds
Started Apr 02 02:05:06 PM PDT 24
Finished Apr 02 02:05:14 PM PDT 24
Peak memory 221844 kb
Host smart-d2a78ab7-37d5-4455-acaf-12af2f9703ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368352946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1368352946
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1509985060
Short name T632
Test name
Test status
Simulation time 338937345 ps
CPU time 2.68 seconds
Started Apr 02 02:05:07 PM PDT 24
Finished Apr 02 02:05:10 PM PDT 24
Peak memory 216356 kb
Host smart-98bd5bad-906b-48a5-a65b-32e355cdff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509985060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1509985060
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3963526627
Short name T459
Test name
Test status
Simulation time 112502595825 ps
CPU time 26.63 seconds
Started Apr 02 02:05:01 PM PDT 24
Finished Apr 02 02:05:28 PM PDT 24
Peak memory 216372 kb
Host smart-17ce9330-504b-4fc0-a190-994fb16ee398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963526627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3963526627
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3503628518
Short name T431
Test name
Test status
Simulation time 1820828013 ps
CPU time 14.17 seconds
Started Apr 02 02:05:07 PM PDT 24
Finished Apr 02 02:05:21 PM PDT 24
Peak memory 216392 kb
Host smart-b55dbabe-3b32-4cbd-8eeb-38467637e85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503628518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3503628518
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3656339929
Short name T714
Test name
Test status
Simulation time 15881320 ps
CPU time 0.74 seconds
Started Apr 02 02:05:08 PM PDT 24
Finished Apr 02 02:05:09 PM PDT 24
Peak memory 205732 kb
Host smart-467a1925-4a2c-41ad-810f-025b6a527051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656339929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3656339929
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2327561173
Short name T596
Test name
Test status
Simulation time 68136465 ps
CPU time 0.71 seconds
Started Apr 02 02:05:20 PM PDT 24
Finished Apr 02 02:05:21 PM PDT 24
Peak memory 205364 kb
Host smart-afe05729-d296-43b1-a36f-181ba257c95b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327561173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2327561173
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2239554737
Short name T419
Test name
Test status
Simulation time 1150497559 ps
CPU time 6.55 seconds
Started Apr 02 02:05:17 PM PDT 24
Finished Apr 02 02:05:23 PM PDT 24
Peak memory 222960 kb
Host smart-9ebf4756-3472-43f0-acd9-b73c66c120e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239554737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2239554737
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3097044183
Short name T532
Test name
Test status
Simulation time 16006282 ps
CPU time 0.71 seconds
Started Apr 02 02:05:07 PM PDT 24
Finished Apr 02 02:05:08 PM PDT 24
Peak memory 205796 kb
Host smart-8621bd2c-4330-4dac-8d48-d758083e8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097044183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3097044183
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.949019931
Short name T636
Test name
Test status
Simulation time 75611745 ps
CPU time 1.06 seconds
Started Apr 02 02:05:15 PM PDT 24
Finished Apr 02 02:05:16 PM PDT 24
Peak memory 216828 kb
Host smart-97b84cc7-0c03-4d82-b460-3956558fcddd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949019931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.949019931
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3014573229
Short name T337
Test name
Test status
Simulation time 23372171819 ps
CPU time 34.09 seconds
Started Apr 02 02:05:12 PM PDT 24
Finished Apr 02 02:05:46 PM PDT 24
Peak memory 235716 kb
Host smart-9e1cba00-eb59-49be-a20c-9a5543e19479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014573229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3014573229
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3148098547
Short name T256
Test name
Test status
Simulation time 368239000 ps
CPU time 3.8 seconds
Started Apr 02 02:05:14 PM PDT 24
Finished Apr 02 02:05:18 PM PDT 24
Peak memory 219128 kb
Host smart-e5bf0058-1133-4500-a95a-f3845941631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148098547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3148098547
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3419521939
Short name T486
Test name
Test status
Simulation time 15850966 ps
CPU time 0.72 seconds
Started Apr 02 02:05:15 PM PDT 24
Finished Apr 02 02:05:16 PM PDT 24
Peak memory 216288 kb
Host smart-ddb546e8-a064-47fa-a5bc-8c850c22fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419521939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3419521939
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1569124107
Short name T8
Test name
Test status
Simulation time 225906581 ps
CPU time 4.23 seconds
Started Apr 02 02:05:19 PM PDT 24
Finished Apr 02 02:05:24 PM PDT 24
Peak memory 219204 kb
Host smart-1a9850fb-adb6-4e30-890b-a8454ab1dd92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1569124107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1569124107
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1220986891
Short name T523
Test name
Test status
Simulation time 35967808 ps
CPU time 0.95 seconds
Started Apr 02 02:05:20 PM PDT 24
Finished Apr 02 02:05:21 PM PDT 24
Peak memory 206860 kb
Host smart-510f18b9-f2e1-4db3-b626-bb12e19c2726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220986891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1220986891
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.686852586
Short name T376
Test name
Test status
Simulation time 6671439280 ps
CPU time 31.07 seconds
Started Apr 02 02:05:13 PM PDT 24
Finished Apr 02 02:05:45 PM PDT 24
Peak memory 216468 kb
Host smart-0bb94e3c-d6d5-44e1-b358-d0ad37b758d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686852586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.686852586
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.233722181
Short name T455
Test name
Test status
Simulation time 189458376 ps
CPU time 2.93 seconds
Started Apr 02 02:05:14 PM PDT 24
Finished Apr 02 02:05:17 PM PDT 24
Peak memory 216316 kb
Host smart-1bd0a771-45cf-484c-9d45-9c1edac0a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233722181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.233722181
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.568784946
Short name T13
Test name
Test status
Simulation time 48290524 ps
CPU time 0.83 seconds
Started Apr 02 02:05:17 PM PDT 24
Finished Apr 02 02:05:18 PM PDT 24
Peak memory 205708 kb
Host smart-1509b791-8101-4aa9-bd19-c3ce825880d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568784946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.568784946
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.479826314
Short name T439
Test name
Test status
Simulation time 13524786 ps
CPU time 0.72 seconds
Started Apr 02 02:05:33 PM PDT 24
Finished Apr 02 02:05:34 PM PDT 24
Peak memory 205340 kb
Host smart-bd74ec8c-0e17-4142-8218-7c0bc029b476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479826314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.479826314
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1920056682
Short name T516
Test name
Test status
Simulation time 73621494 ps
CPU time 0.78 seconds
Started Apr 02 02:05:21 PM PDT 24
Finished Apr 02 02:05:22 PM PDT 24
Peak memory 206520 kb
Host smart-98e33c48-b924-48a6-8b1c-0e2aefa2dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920056682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1920056682
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.760944067
Short name T61
Test name
Test status
Simulation time 1522206855 ps
CPU time 32.66 seconds
Started Apr 02 02:05:31 PM PDT 24
Finished Apr 02 02:06:04 PM PDT 24
Peak memory 251860 kb
Host smart-311f2672-668b-4b04-9aca-3ea3c65f3c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760944067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.760944067
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1203161553
Short name T230
Test name
Test status
Simulation time 12453485870 ps
CPU time 23.94 seconds
Started Apr 02 02:05:32 PM PDT 24
Finished Apr 02 02:05:56 PM PDT 24
Peak memory 216932 kb
Host smart-d10e3abd-b410-4cf7-933e-ba25b4bc1231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203161553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1203161553
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3342958114
Short name T659
Test name
Test status
Simulation time 42865930 ps
CPU time 0.96 seconds
Started Apr 02 02:05:22 PM PDT 24
Finished Apr 02 02:05:23 PM PDT 24
Peak memory 218040 kb
Host smart-0450d6a4-7097-41f5-bff1-3b80df0aa8fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342958114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3342958114
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4179824759
Short name T207
Test name
Test status
Simulation time 2114254644 ps
CPU time 3.46 seconds
Started Apr 02 02:05:28 PM PDT 24
Finished Apr 02 02:05:32 PM PDT 24
Peak memory 216892 kb
Host smart-b8be9023-716f-425b-a16d-caab53f41990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179824759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4179824759
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3687127575
Short name T43
Test name
Test status
Simulation time 19047557 ps
CPU time 0.72 seconds
Started Apr 02 02:05:26 PM PDT 24
Finished Apr 02 02:05:27 PM PDT 24
Peak memory 216244 kb
Host smart-67b82059-0535-460b-803e-6276e68be1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687127575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3687127575
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2250860010
Short name T9
Test name
Test status
Simulation time 82379826 ps
CPU time 3.72 seconds
Started Apr 02 02:05:34 PM PDT 24
Finished Apr 02 02:05:38 PM PDT 24
Peak memory 222820 kb
Host smart-27878ec2-5647-4038-8378-2add9c8f6cff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2250860010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2250860010
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.842116121
Short name T31
Test name
Test status
Simulation time 185573526 ps
CPU time 0.95 seconds
Started Apr 02 02:05:30 PM PDT 24
Finished Apr 02 02:05:31 PM PDT 24
Peak memory 206680 kb
Host smart-ef5159e5-f9ee-42de-8ac6-906f62ca4cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842116121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.842116121
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.794379006
Short name T558
Test name
Test status
Simulation time 7447264850 ps
CPU time 23.95 seconds
Started Apr 02 02:05:25 PM PDT 24
Finished Apr 02 02:05:49 PM PDT 24
Peak memory 216444 kb
Host smart-1a8a62fc-417c-4837-aad7-93e73411b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794379006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.794379006
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.37154724
Short name T614
Test name
Test status
Simulation time 696559502 ps
CPU time 9.74 seconds
Started Apr 02 02:05:28 PM PDT 24
Finished Apr 02 02:05:38 PM PDT 24
Peak memory 216464 kb
Host smart-8f8c2db2-604c-46ba-b57e-4d31afbe450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37154724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.37154724
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3393842042
Short name T534
Test name
Test status
Simulation time 411234819 ps
CPU time 0.97 seconds
Started Apr 02 02:05:27 PM PDT 24
Finished Apr 02 02:05:28 PM PDT 24
Peak memory 206196 kb
Host smart-82dc2795-33bb-429c-adaa-dfbae16d66d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393842042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3393842042
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2888897338
Short name T726
Test name
Test status
Simulation time 13634778 ps
CPU time 0.71 seconds
Started Apr 02 02:05:40 PM PDT 24
Finished Apr 02 02:05:41 PM PDT 24
Peak memory 205288 kb
Host smart-fc6668c0-2ea2-4b31-8279-e2dec0c1bd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888897338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2888897338
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.47124089
Short name T666
Test name
Test status
Simulation time 54614369 ps
CPU time 0.73 seconds
Started Apr 02 02:05:31 PM PDT 24
Finished Apr 02 02:05:32 PM PDT 24
Peak memory 205776 kb
Host smart-56e40c0e-34b8-4e30-beeb-1ff803a74510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47124089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.47124089
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.845949874
Short name T301
Test name
Test status
Simulation time 963121759 ps
CPU time 8.13 seconds
Started Apr 02 02:05:39 PM PDT 24
Finished Apr 02 02:05:47 PM PDT 24
Peak memory 237008 kb
Host smart-6feb076c-452f-40e5-9d60-a4f29a8d79cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845949874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.845949874
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1669551437
Short name T276
Test name
Test status
Simulation time 3224137961 ps
CPU time 10.52 seconds
Started Apr 02 02:05:37 PM PDT 24
Finished Apr 02 02:05:48 PM PDT 24
Peak memory 223720 kb
Host smart-df2394b4-719e-4e2e-ac57-f6ee07548327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669551437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1669551437
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4061455027
Short name T220
Test name
Test status
Simulation time 907137942 ps
CPU time 12.11 seconds
Started Apr 02 02:05:35 PM PDT 24
Finished Apr 02 02:05:47 PM PDT 24
Peak memory 237164 kb
Host smart-583a74b8-b07e-4314-b639-0e1849717042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061455027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4061455027
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.145420491
Short name T453
Test name
Test status
Simulation time 53330654 ps
CPU time 0.99 seconds
Started Apr 02 02:05:33 PM PDT 24
Finished Apr 02 02:05:35 PM PDT 24
Peak memory 218060 kb
Host smart-14e85147-48d0-47b9-bf15-4adf333ce647
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145420491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.145420491
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1472941274
Short name T627
Test name
Test status
Simulation time 24011567 ps
CPU time 0.71 seconds
Started Apr 02 02:05:35 PM PDT 24
Finished Apr 02 02:05:35 PM PDT 24
Peak memory 216224 kb
Host smart-ac603551-08ff-415b-b55b-2a06b9f529aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472941274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1472941274
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1222828168
Short name T511
Test name
Test status
Simulation time 721910546 ps
CPU time 3.54 seconds
Started Apr 02 02:05:44 PM PDT 24
Finished Apr 02 02:05:48 PM PDT 24
Peak memory 219096 kb
Host smart-79c82937-d564-4297-bcd3-cf46f8e711c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222828168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1222828168
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2538319143
Short name T398
Test name
Test status
Simulation time 7985270097 ps
CPU time 21.43 seconds
Started Apr 02 02:05:35 PM PDT 24
Finished Apr 02 02:05:56 PM PDT 24
Peak memory 216436 kb
Host smart-83cc1503-56e0-4098-85ff-d9c35dcf4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538319143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2538319143
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1614236301
Short name T749
Test name
Test status
Simulation time 12765576732 ps
CPU time 29.87 seconds
Started Apr 02 02:05:36 PM PDT 24
Finished Apr 02 02:06:06 PM PDT 24
Peak memory 216372 kb
Host smart-6edc9154-92a5-4f64-bd73-df3632645980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614236301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1614236301
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2769964656
Short name T641
Test name
Test status
Simulation time 311594657 ps
CPU time 3.17 seconds
Started Apr 02 02:05:35 PM PDT 24
Finished Apr 02 02:05:38 PM PDT 24
Peak memory 216456 kb
Host smart-361d4b8e-7d90-4d92-ad8b-f7192e043421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769964656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2769964656
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4148709521
Short name T505
Test name
Test status
Simulation time 55189529 ps
CPU time 0.82 seconds
Started Apr 02 02:05:36 PM PDT 24
Finished Apr 02 02:05:37 PM PDT 24
Peak memory 205744 kb
Host smart-f431ba56-9ba0-4f38-9e3b-8ae856cab8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148709521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4148709521
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3185915196
Short name T258
Test name
Test status
Simulation time 2799385314 ps
CPU time 9.17 seconds
Started Apr 02 02:05:44 PM PDT 24
Finished Apr 02 02:05:54 PM PDT 24
Peak memory 219008 kb
Host smart-e1107047-2c0d-4035-ae4e-079c586100a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185915196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3185915196
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4165478826
Short name T496
Test name
Test status
Simulation time 12325164 ps
CPU time 0.67 seconds
Started Apr 02 02:05:56 PM PDT 24
Finished Apr 02 02:05:57 PM PDT 24
Peak memory 204772 kb
Host smart-2dd42ae7-8967-4f2b-acf4-fcf786c5a354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165478826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4165478826
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1068889708
Short name T488
Test name
Test status
Simulation time 14226505 ps
CPU time 0.76 seconds
Started Apr 02 02:05:57 PM PDT 24
Finished Apr 02 02:06:00 PM PDT 24
Peak memory 206500 kb
Host smart-4807083a-8426-40fe-b80a-b7f469ace725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068889708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1068889708
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1945455796
Short name T536
Test name
Test status
Simulation time 45366098 ps
CPU time 0.98 seconds
Started Apr 02 02:05:47 PM PDT 24
Finished Apr 02 02:05:48 PM PDT 24
Peak memory 218032 kb
Host smart-96abd85b-c666-43c3-b524-422326bb569a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945455796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1945455796
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2894106815
Short name T124
Test name
Test status
Simulation time 751438506 ps
CPU time 2.36 seconds
Started Apr 02 02:05:46 PM PDT 24
Finished Apr 02 02:05:49 PM PDT 24
Peak memory 216308 kb
Host smart-ea28b6a4-c1d4-442b-855e-6b5fd2cf2324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894106815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2894106815
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.4258473712
Short name T530
Test name
Test status
Simulation time 42889658 ps
CPU time 0.73 seconds
Started Apr 02 02:05:46 PM PDT 24
Finished Apr 02 02:05:47 PM PDT 24
Peak memory 216216 kb
Host smart-2b44d2a6-16ad-4986-a61d-b10e0781eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258473712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.4258473712
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3555487317
Short name T539
Test name
Test status
Simulation time 9989657972 ps
CPU time 4.9 seconds
Started Apr 02 02:05:48 PM PDT 24
Finished Apr 02 02:05:53 PM PDT 24
Peak memory 222884 kb
Host smart-407829cd-58d5-476c-835b-32b7c1aff53c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555487317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3555487317
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1681441971
Short name T525
Test name
Test status
Simulation time 3205495136 ps
CPU time 5.2 seconds
Started Apr 02 02:05:42 PM PDT 24
Finished Apr 02 02:05:49 PM PDT 24
Peak memory 216376 kb
Host smart-5b8dc147-1cd1-4586-a747-9d9e73f186e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681441971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1681441971
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2192023872
Short name T660
Test name
Test status
Simulation time 237925448 ps
CPU time 3.67 seconds
Started Apr 02 02:05:45 PM PDT 24
Finished Apr 02 02:05:49 PM PDT 24
Peak memory 216292 kb
Host smart-d308b8db-1e89-4105-bdd2-fe9a93475b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192023872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2192023872
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1591806135
Short name T622
Test name
Test status
Simulation time 106280249 ps
CPU time 0.89 seconds
Started Apr 02 02:05:44 PM PDT 24
Finished Apr 02 02:05:45 PM PDT 24
Peak memory 206164 kb
Host smart-94f35169-da36-42b6-95b6-c8155cd1141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591806135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1591806135
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1766894991
Short name T705
Test name
Test status
Simulation time 13127386 ps
CPU time 0.69 seconds
Started Apr 02 02:05:55 PM PDT 24
Finished Apr 02 02:05:57 PM PDT 24
Peak memory 204800 kb
Host smart-c9f8eabe-48f0-406e-9c74-4b8047b74e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766894991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1766894991
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1420865369
Short name T112
Test name
Test status
Simulation time 1720677338 ps
CPU time 18.1 seconds
Started Apr 02 02:05:56 PM PDT 24
Finished Apr 02 02:06:17 PM PDT 24
Peak memory 216940 kb
Host smart-e0d376ab-3de7-41d8-a49b-982f8f258a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420865369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1420865369
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1971682438
Short name T551
Test name
Test status
Simulation time 33537602 ps
CPU time 0.74 seconds
Started Apr 02 02:05:49 PM PDT 24
Finished Apr 02 02:05:50 PM PDT 24
Peak memory 206516 kb
Host smart-b025f981-60a9-47d0-b028-83fa4c5be07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971682438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1971682438
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1239739314
Short name T474
Test name
Test status
Simulation time 2150047313 ps
CPU time 8.18 seconds
Started Apr 02 02:05:52 PM PDT 24
Finished Apr 02 02:06:01 PM PDT 24
Peak memory 221840 kb
Host smart-2805391b-ae4d-402b-bb02-86e70cd42139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239739314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1239739314
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2809318823
Short name T240
Test name
Test status
Simulation time 3653795429 ps
CPU time 40.5 seconds
Started Apr 02 02:05:57 PM PDT 24
Finished Apr 02 02:06:39 PM PDT 24
Peak memory 222528 kb
Host smart-a0140a52-2cac-470d-a1bf-1a35b344aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809318823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2809318823
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.367682044
Short name T34
Test name
Test status
Simulation time 134686355 ps
CPU time 0.96 seconds
Started Apr 02 02:05:50 PM PDT 24
Finished Apr 02 02:05:51 PM PDT 24
Peak memory 216824 kb
Host smart-44484403-4dcf-406c-960f-56306bb4e9f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367682044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.367682044
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2869709689
Short name T332
Test name
Test status
Simulation time 125136070 ps
CPU time 2.25 seconds
Started Apr 02 02:05:52 PM PDT 24
Finished Apr 02 02:05:55 PM PDT 24
Peak memory 220048 kb
Host smart-e30f30eb-1ac3-41f7-b589-e6cdd151b708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869709689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2869709689
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2251293156
Short name T41
Test name
Test status
Simulation time 46847025 ps
CPU time 0.74 seconds
Started Apr 02 02:05:56 PM PDT 24
Finished Apr 02 02:05:58 PM PDT 24
Peak memory 216224 kb
Host smart-ea09d6d1-5f80-4127-8b6f-b2e110864353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251293156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2251293156
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.992398970
Short name T469
Test name
Test status
Simulation time 139658159 ps
CPU time 3.97 seconds
Started Apr 02 02:05:57 PM PDT 24
Finished Apr 02 02:06:03 PM PDT 24
Peak memory 220468 kb
Host smart-efca9158-7289-4cc0-8f73-c0c08a05ac55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=992398970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.992398970
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2851504534
Short name T709
Test name
Test status
Simulation time 6464038098 ps
CPU time 33.32 seconds
Started Apr 02 02:05:50 PM PDT 24
Finished Apr 02 02:06:24 PM PDT 24
Peak memory 216456 kb
Host smart-2a575cb6-5fbd-475d-9644-7eaccc087bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851504534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2851504534
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1204782818
Short name T573
Test name
Test status
Simulation time 8187008071 ps
CPU time 22.47 seconds
Started Apr 02 02:05:51 PM PDT 24
Finished Apr 02 02:06:15 PM PDT 24
Peak memory 216408 kb
Host smart-3ed757c9-7152-4266-a3b1-5d5546306fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204782818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1204782818
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2920902737
Short name T588
Test name
Test status
Simulation time 63227581 ps
CPU time 3.51 seconds
Started Apr 02 02:05:54 PM PDT 24
Finished Apr 02 02:05:58 PM PDT 24
Peak memory 216392 kb
Host smart-bdb75ca0-e66e-4b07-80f5-aabcb215c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920902737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2920902737
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.572706803
Short name T108
Test name
Test status
Simulation time 58058637 ps
CPU time 0.83 seconds
Started Apr 02 02:05:51 PM PDT 24
Finished Apr 02 02:05:54 PM PDT 24
Peak memory 205756 kb
Host smart-1db13fe2-fa4e-4a85-bba7-ff74abacd235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572706803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.572706803
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2440018848
Short name T251
Test name
Test status
Simulation time 1281515798 ps
CPU time 14.69 seconds
Started Apr 02 02:05:54 PM PDT 24
Finished Apr 02 02:06:09 PM PDT 24
Peak memory 236488 kb
Host smart-ece84a40-ecaa-4f27-a7df-deb8ec40f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440018848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2440018848
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3933451155
Short name T587
Test name
Test status
Simulation time 25115338 ps
CPU time 0.7 seconds
Started Apr 02 02:06:10 PM PDT 24
Finished Apr 02 02:06:11 PM PDT 24
Peak memory 204772 kb
Host smart-bdf3e4b1-3996-4189-89dd-2ee2c3d58287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933451155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3933451155
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1537945077
Short name T713
Test name
Test status
Simulation time 79280094 ps
CPU time 2.17 seconds
Started Apr 02 02:06:03 PM PDT 24
Finished Apr 02 02:06:06 PM PDT 24
Peak memory 218592 kb
Host smart-d8cad8e2-1756-4e3f-8ff7-808465452a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537945077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1537945077
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2106114714
Short name T485
Test name
Test status
Simulation time 40012827 ps
CPU time 0.73 seconds
Started Apr 02 02:05:58 PM PDT 24
Finished Apr 02 02:06:00 PM PDT 24
Peak memory 205472 kb
Host smart-28508157-a292-4c91-b35f-a2f384d197b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106114714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2106114714
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2418882
Short name T354
Test name
Test status
Simulation time 45852112275 ps
CPU time 170.57 seconds
Started Apr 02 02:06:05 PM PDT 24
Finished Apr 02 02:08:56 PM PDT 24
Peak memory 240812 kb
Host smart-7f65625c-1331-4ea6-bc43-e08173ab35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2418882
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2097486041
Short name T696
Test name
Test status
Simulation time 15490501 ps
CPU time 0.98 seconds
Started Apr 02 02:05:58 PM PDT 24
Finished Apr 02 02:06:00 PM PDT 24
Peak memory 216832 kb
Host smart-da80d61f-eb38-48f4-9681-829acc187d3f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097486041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2097486041
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1187548706
Short name T372
Test name
Test status
Simulation time 10986054427 ps
CPU time 13.31 seconds
Started Apr 02 02:06:01 PM PDT 24
Finished Apr 02 02:06:14 PM PDT 24
Peak memory 234656 kb
Host smart-a3b5e298-6176-442d-a264-c583bdf9d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187548706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1187548706
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.1982129602
Short name T403
Test name
Test status
Simulation time 42458244 ps
CPU time 0.72 seconds
Started Apr 02 02:05:59 PM PDT 24
Finished Apr 02 02:06:00 PM PDT 24
Peak memory 216304 kb
Host smart-be535ded-7a10-4bc5-b213-e7884c5241da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982129602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.1982129602
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.608116340
Short name T729
Test name
Test status
Simulation time 223672803 ps
CPU time 3.57 seconds
Started Apr 02 02:06:04 PM PDT 24
Finished Apr 02 02:06:08 PM PDT 24
Peak memory 220204 kb
Host smart-563a4606-d273-43c3-ac0e-4c70f1853595
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=608116340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.608116340
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2559401800
Short name T737
Test name
Test status
Simulation time 68409661 ps
CPU time 1.07 seconds
Started Apr 02 02:06:04 PM PDT 24
Finished Apr 02 02:06:06 PM PDT 24
Peak memory 206844 kb
Host smart-7e324f49-68b6-4438-92ee-c6dfb3aad708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559401800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2559401800
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4207347965
Short name T401
Test name
Test status
Simulation time 2542457931 ps
CPU time 35.38 seconds
Started Apr 02 02:05:59 PM PDT 24
Finished Apr 02 02:06:35 PM PDT 24
Peak memory 216444 kb
Host smart-6ddd8c2c-03ef-42cc-90fe-522f88b60597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207347965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4207347965
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1788754462
Short name T675
Test name
Test status
Simulation time 5203678808 ps
CPU time 7.07 seconds
Started Apr 02 02:06:04 PM PDT 24
Finished Apr 02 02:06:11 PM PDT 24
Peak memory 216432 kb
Host smart-7d53260d-e6e8-4b27-ab4a-a706cbbaf246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788754462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1788754462
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4063788900
Short name T740
Test name
Test status
Simulation time 72791818 ps
CPU time 1.09 seconds
Started Apr 02 02:06:02 PM PDT 24
Finished Apr 02 02:06:04 PM PDT 24
Peak memory 207984 kb
Host smart-7ec5c34f-2908-498a-aea8-c61fd75d1dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063788900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4063788900
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2124005384
Short name T109
Test name
Test status
Simulation time 62533639 ps
CPU time 0.78 seconds
Started Apr 02 02:06:01 PM PDT 24
Finished Apr 02 02:06:02 PM PDT 24
Peak memory 205716 kb
Host smart-4c76bf76-09f0-4f4e-be37-abc669b33ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124005384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2124005384
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3394806888
Short name T664
Test name
Test status
Simulation time 163493022 ps
CPU time 0.7 seconds
Started Apr 02 02:06:21 PM PDT 24
Finished Apr 02 02:06:21 PM PDT 24
Peak memory 204716 kb
Host smart-ca1c4cea-187c-4283-8d92-d4a1eb8f2c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394806888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3394806888
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.274343638
Short name T483
Test name
Test status
Simulation time 60352780 ps
CPU time 0.76 seconds
Started Apr 02 02:06:12 PM PDT 24
Finished Apr 02 02:06:13 PM PDT 24
Peak memory 206836 kb
Host smart-90fc5b34-04b8-446b-b073-eaebd80b6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274343638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.274343638
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2824863928
Short name T375
Test name
Test status
Simulation time 13896917631 ps
CPU time 84.29 seconds
Started Apr 02 02:06:20 PM PDT 24
Finished Apr 02 02:07:44 PM PDT 24
Peak memory 249284 kb
Host smart-d21ffeb4-2a4f-4d97-9414-4f65e307ffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824863928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2824863928
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.4133197955
Short name T586
Test name
Test status
Simulation time 36444998 ps
CPU time 1.06 seconds
Started Apr 02 02:06:09 PM PDT 24
Finished Apr 02 02:06:10 PM PDT 24
Peak memory 216832 kb
Host smart-d30d3adc-15fd-41e4-a929-2592b8c235ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133197955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.4133197955
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2406159109
Short name T350
Test name
Test status
Simulation time 5049229952 ps
CPU time 8.84 seconds
Started Apr 02 02:06:18 PM PDT 24
Finished Apr 02 02:06:27 PM PDT 24
Peak memory 220960 kb
Host smart-5c25f839-8eb5-441e-bdcf-7b4979dc3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406159109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2406159109
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3529161598
Short name T578
Test name
Test status
Simulation time 34251644 ps
CPU time 0.75 seconds
Started Apr 02 02:06:09 PM PDT 24
Finished Apr 02 02:06:10 PM PDT 24
Peak memory 216288 kb
Host smart-a6afa34a-4a1c-4281-bad5-ce69f0abfd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529161598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3529161598
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1191636225
Short name T471
Test name
Test status
Simulation time 1056836748 ps
CPU time 3.75 seconds
Started Apr 02 02:06:22 PM PDT 24
Finished Apr 02 02:06:26 PM PDT 24
Peak memory 222200 kb
Host smart-1530ad90-f997-4908-86b7-89ee7aca187f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1191636225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1191636225
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1052400162
Short name T689
Test name
Test status
Simulation time 2059884873 ps
CPU time 11.84 seconds
Started Apr 02 02:06:10 PM PDT 24
Finished Apr 02 02:06:22 PM PDT 24
Peak memory 218256 kb
Host smart-f94d1479-ff7e-4a4e-b027-ee2645bcbdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052400162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1052400162
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1443727253
Short name T444
Test name
Test status
Simulation time 13649660270 ps
CPU time 21.19 seconds
Started Apr 02 02:06:13 PM PDT 24
Finished Apr 02 02:06:34 PM PDT 24
Peak memory 217464 kb
Host smart-3c05a8c6-af5a-4f19-9f0e-77f573858beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443727253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1443727253
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.965462761
Short name T391
Test name
Test status
Simulation time 790996270 ps
CPU time 3.77 seconds
Started Apr 02 02:06:13 PM PDT 24
Finished Apr 02 02:06:17 PM PDT 24
Peak memory 216784 kb
Host smart-964d2b3c-3391-4ee4-8c1a-f0c830577504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965462761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.965462761
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3326206265
Short name T613
Test name
Test status
Simulation time 190514436 ps
CPU time 0.89 seconds
Started Apr 02 02:06:13 PM PDT 24
Finished Apr 02 02:06:14 PM PDT 24
Peak memory 206744 kb
Host smart-4a5a9c36-a429-4f0a-b5e2-1b29142d96bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326206265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3326206265
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1899540629
Short name T284
Test name
Test status
Simulation time 16534094739 ps
CPU time 12.87 seconds
Started Apr 02 02:06:16 PM PDT 24
Finished Apr 02 02:06:29 PM PDT 24
Peak memory 224536 kb
Host smart-b5e0eceb-fe9c-4c4e-ac6a-94c09d490a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899540629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1899540629
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1970301682
Short name T682
Test name
Test status
Simulation time 16038323 ps
CPU time 0.66 seconds
Started Apr 02 02:06:28 PM PDT 24
Finished Apr 02 02:06:29 PM PDT 24
Peak memory 205292 kb
Host smart-92518144-debd-45f8-8a0c-def58ba80875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970301682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1970301682
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1915300400
Short name T247
Test name
Test status
Simulation time 37439913 ps
CPU time 2.61 seconds
Started Apr 02 02:06:25 PM PDT 24
Finished Apr 02 02:06:28 PM PDT 24
Peak memory 222856 kb
Host smart-78ac0804-a85d-4652-84cb-3d051f23c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915300400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1915300400
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2296950054
Short name T427
Test name
Test status
Simulation time 19384228 ps
CPU time 0.78 seconds
Started Apr 02 02:06:18 PM PDT 24
Finished Apr 02 02:06:19 PM PDT 24
Peak memory 206488 kb
Host smart-3478a464-5dce-44e8-8b48-6afded82c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296950054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2296950054
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1378880935
Short name T728
Test name
Test status
Simulation time 3750998620 ps
CPU time 55.29 seconds
Started Apr 02 02:06:25 PM PDT 24
Finished Apr 02 02:07:20 PM PDT 24
Peak memory 240996 kb
Host smart-b55758df-08e9-460a-943a-77c4b8907bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378880935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1378880935
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.361039777
Short name T185
Test name
Test status
Simulation time 1919848224 ps
CPU time 8.24 seconds
Started Apr 02 02:06:25 PM PDT 24
Finished Apr 02 02:06:33 PM PDT 24
Peak memory 222980 kb
Host smart-a49ad8da-1a57-462b-a34d-6058a2b8e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361039777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.361039777
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3962404403
Short name T515
Test name
Test status
Simulation time 17655000 ps
CPU time 0.99 seconds
Started Apr 02 02:06:21 PM PDT 24
Finished Apr 02 02:06:23 PM PDT 24
Peak memory 216812 kb
Host smart-60f3ddee-74bd-4dfd-9518-d39257584c5c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962404403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3962404403
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3609283569
Short name T64
Test name
Test status
Simulation time 5249910702 ps
CPU time 6.48 seconds
Started Apr 02 02:06:24 PM PDT 24
Finished Apr 02 02:06:30 PM PDT 24
Peak memory 221524 kb
Host smart-ceab7c2e-50b2-44d7-95d8-6c02ffd6baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609283569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3609283569
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2056412536
Short name T634
Test name
Test status
Simulation time 24490166 ps
CPU time 0.74 seconds
Started Apr 02 02:06:22 PM PDT 24
Finished Apr 02 02:06:23 PM PDT 24
Peak memory 216288 kb
Host smart-6bd14912-8109-4242-a30b-d7dfe29ac9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056412536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2056412536
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2849780086
Short name T560
Test name
Test status
Simulation time 242559581 ps
CPU time 5.78 seconds
Started Apr 02 02:06:30 PM PDT 24
Finished Apr 02 02:06:36 PM PDT 24
Peak memory 220372 kb
Host smart-507472c7-911f-45fd-b4d5-391575c33c20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2849780086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2849780086
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2821647171
Short name T626
Test name
Test status
Simulation time 476199674 ps
CPU time 3.53 seconds
Started Apr 02 02:06:21 PM PDT 24
Finished Apr 02 02:06:24 PM PDT 24
Peak memory 216364 kb
Host smart-e10dc0c9-2582-4186-990f-64393012eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821647171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2821647171
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1973619033
Short name T52
Test name
Test status
Simulation time 183587341 ps
CPU time 3.29 seconds
Started Apr 02 02:06:23 PM PDT 24
Finished Apr 02 02:06:27 PM PDT 24
Peak memory 216332 kb
Host smart-0a8e4ee2-1a66-4dac-b00a-ad87c0cfed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973619033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1973619033
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.842709027
Short name T665
Test name
Test status
Simulation time 152361759 ps
CPU time 0.71 seconds
Started Apr 02 02:06:24 PM PDT 24
Finished Apr 02 02:06:25 PM PDT 24
Peak memory 205744 kb
Host smart-d2ac64a1-72c3-4ffd-b3c5-b47647004697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842709027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.842709027
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.62733074
Short name T670
Test name
Test status
Simulation time 131959381 ps
CPU time 0.68 seconds
Started Apr 02 02:03:26 PM PDT 24
Finished Apr 02 02:03:27 PM PDT 24
Peak memory 204752 kb
Host smart-784a4c18-3288-4f04-92ae-457f84cf3774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62733074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.62733074
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.742684407
Short name T508
Test name
Test status
Simulation time 19895686 ps
CPU time 0.76 seconds
Started Apr 02 02:03:15 PM PDT 24
Finished Apr 02 02:03:16 PM PDT 24
Peak memory 206516 kb
Host smart-e9dff9ba-aba1-401b-9ff9-0532ea827b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742684407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.742684407
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2738614353
Short name T268
Test name
Test status
Simulation time 7413562524 ps
CPU time 36.69 seconds
Started Apr 02 02:03:22 PM PDT 24
Finished Apr 02 02:03:59 PM PDT 24
Peak memory 233668 kb
Host smart-24c7a6f2-cde9-436e-886b-3a8070417e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738614353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2738614353
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1699849389
Short name T32
Test name
Test status
Simulation time 16112987 ps
CPU time 0.98 seconds
Started Apr 02 02:03:14 PM PDT 24
Finished Apr 02 02:03:15 PM PDT 24
Peak memory 216824 kb
Host smart-cdcd7403-58c0-47c2-ae3d-d0bb62af05f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699849389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1699849389
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2052076023
Short name T264
Test name
Test status
Simulation time 445770460 ps
CPU time 8.75 seconds
Started Apr 02 02:03:22 PM PDT 24
Finished Apr 02 02:03:31 PM PDT 24
Peak memory 236300 kb
Host smart-5054996d-3594-42a0-9616-f52d786935a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052076023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2052076023
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1488214108
Short name T242
Test name
Test status
Simulation time 39198211878 ps
CPU time 42.91 seconds
Started Apr 02 02:03:19 PM PDT 24
Finished Apr 02 02:04:02 PM PDT 24
Peak memory 223828 kb
Host smart-a6d1fef5-e435-409b-b62a-92d62ed24020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488214108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1488214108
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3219478032
Short name T480
Test name
Test status
Simulation time 69689357 ps
CPU time 0.7 seconds
Started Apr 02 02:03:15 PM PDT 24
Finished Apr 02 02:03:16 PM PDT 24
Peak memory 216300 kb
Host smart-25d22f87-b2d8-4974-9258-2bf4cdd24602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219478032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3219478032
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.201970954
Short name T421
Test name
Test status
Simulation time 453516540 ps
CPU time 6.44 seconds
Started Apr 02 02:03:28 PM PDT 24
Finished Apr 02 02:03:35 PM PDT 24
Peak memory 222760 kb
Host smart-77530af8-3513-4599-9a80-64c6cefa5e8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=201970954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.201970954
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.393680212
Short name T30
Test name
Test status
Simulation time 101565347 ps
CPU time 1.14 seconds
Started Apr 02 02:03:29 PM PDT 24
Finished Apr 02 02:03:30 PM PDT 24
Peak memory 236996 kb
Host smart-34eee0e4-84e9-48b1-899a-704b4ed3fc84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393680212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.393680212
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.407509684
Short name T399
Test name
Test status
Simulation time 1122135076 ps
CPU time 6.82 seconds
Started Apr 02 02:03:14 PM PDT 24
Finished Apr 02 02:03:21 PM PDT 24
Peak memory 216396 kb
Host smart-ae80fffe-2a95-4626-bcdd-e7989e38d0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407509684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.407509684
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1154286081
Short name T693
Test name
Test status
Simulation time 21298007157 ps
CPU time 15.42 seconds
Started Apr 02 02:03:15 PM PDT 24
Finished Apr 02 02:03:30 PM PDT 24
Peak memory 216356 kb
Host smart-d40e284c-c05f-420d-acca-078c98944d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154286081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1154286081
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3331554586
Short name T450
Test name
Test status
Simulation time 62433890 ps
CPU time 1.14 seconds
Started Apr 02 02:03:15 PM PDT 24
Finished Apr 02 02:03:16 PM PDT 24
Peak memory 208168 kb
Host smart-4ba3bbf1-74f5-4e36-9a28-c4ecc25dfe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331554586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3331554586
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1791467819
Short name T495
Test name
Test status
Simulation time 181744006 ps
CPU time 0.92 seconds
Started Apr 02 02:03:15 PM PDT 24
Finished Apr 02 02:03:16 PM PDT 24
Peak memory 206736 kb
Host smart-1a25456a-4070-40bb-bae2-1bac52ba2387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791467819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1791467819
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1610421855
Short name T228
Test name
Test status
Simulation time 11596410732 ps
CPU time 11.26 seconds
Started Apr 02 02:03:25 PM PDT 24
Finished Apr 02 02:03:36 PM PDT 24
Peak memory 232820 kb
Host smart-6d7c77a7-f19b-4261-961e-b782e9b0d867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610421855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1610421855
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1478096525
Short name T543
Test name
Test status
Simulation time 15405087 ps
CPU time 0.77 seconds
Started Apr 02 02:06:37 PM PDT 24
Finished Apr 02 02:06:40 PM PDT 24
Peak memory 205332 kb
Host smart-1375150f-caf9-4951-8d6e-126443d89a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478096525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1478096525
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2436640894
Short name T89
Test name
Test status
Simulation time 309738833 ps
CPU time 2.84 seconds
Started Apr 02 02:06:32 PM PDT 24
Finished Apr 02 02:06:35 PM PDT 24
Peak memory 218896 kb
Host smart-146261c9-49a3-4dd9-abcb-4e1c5c85a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436640894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2436640894
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2679156460
Short name T467
Test name
Test status
Simulation time 27672470 ps
CPU time 0.73 seconds
Started Apr 02 02:06:26 PM PDT 24
Finished Apr 02 02:06:27 PM PDT 24
Peak memory 205340 kb
Host smart-cf0f0ab3-8354-4c84-a3ef-e8a10f9dfc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679156460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2679156460
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1786054453
Short name T308
Test name
Test status
Simulation time 3744072101 ps
CPU time 13.98 seconds
Started Apr 02 02:06:33 PM PDT 24
Finished Apr 02 02:06:50 PM PDT 24
Peak memory 224672 kb
Host smart-3c4cef27-f6e8-4ef3-be03-4a9696c3427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786054453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1786054453
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3275311671
Short name T182
Test name
Test status
Simulation time 3600842045 ps
CPU time 10.11 seconds
Started Apr 02 02:06:33 PM PDT 24
Finished Apr 02 02:06:45 PM PDT 24
Peak memory 219012 kb
Host smart-1460677e-662f-40cf-a6d8-2d220bc22ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275311671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3275311671
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.177083318
Short name T191
Test name
Test status
Simulation time 2836199744 ps
CPU time 7.09 seconds
Started Apr 02 02:06:28 PM PDT 24
Finished Apr 02 02:06:37 PM PDT 24
Peak memory 222524 kb
Host smart-316130ae-aa39-4911-86f3-882be0b78b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177083318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.177083318
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2367584296
Short name T232
Test name
Test status
Simulation time 72900292771 ps
CPU time 28.2 seconds
Started Apr 02 02:06:28 PM PDT 24
Finished Apr 02 02:06:58 PM PDT 24
Peak memory 237128 kb
Host smart-d70dc86c-ed19-4052-836a-21632df7233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367584296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2367584296
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1014446245
Short name T10
Test name
Test status
Simulation time 1144525885 ps
CPU time 9.5 seconds
Started Apr 02 02:06:34 PM PDT 24
Finished Apr 02 02:06:45 PM PDT 24
Peak memory 221860 kb
Host smart-68b459b5-7be1-4ab3-a87b-f880845d1e1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1014446245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1014446245
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1431962451
Short name T552
Test name
Test status
Simulation time 21562553907 ps
CPU time 28.06 seconds
Started Apr 02 02:06:30 PM PDT 24
Finished Apr 02 02:06:59 PM PDT 24
Peak memory 216456 kb
Host smart-76cf687a-a420-4a6e-a1f3-ddaab4803455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431962451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1431962451
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2174273299
Short name T518
Test name
Test status
Simulation time 233871250 ps
CPU time 3.24 seconds
Started Apr 02 02:06:32 PM PDT 24
Finished Apr 02 02:06:35 PM PDT 24
Peak memory 216396 kb
Host smart-e66fcd0e-7375-4567-865f-c4d249335089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174273299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2174273299
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2004725832
Short name T568
Test name
Test status
Simulation time 98397978 ps
CPU time 0.88 seconds
Started Apr 02 02:06:32 PM PDT 24
Finished Apr 02 02:06:34 PM PDT 24
Peak memory 206768 kb
Host smart-b9a29a96-9b3f-478a-918d-240f69e1eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004725832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2004725832
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.617034718
Short name T503
Test name
Test status
Simulation time 13213526 ps
CPU time 0.77 seconds
Started Apr 02 02:06:44 PM PDT 24
Finished Apr 02 02:06:45 PM PDT 24
Peak memory 205280 kb
Host smart-1f5fb0a6-e98b-4254-bf0f-4d7dd4e6e6a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617034718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.617034718
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.703232352
Short name T527
Test name
Test status
Simulation time 12781418 ps
CPU time 0.72 seconds
Started Apr 02 02:06:38 PM PDT 24
Finished Apr 02 02:06:40 PM PDT 24
Peak memory 206524 kb
Host smart-e386d364-0e80-458b-a4c2-bf7fc5f30236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703232352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.703232352
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2374164351
Short name T255
Test name
Test status
Simulation time 1814728694 ps
CPU time 13.03 seconds
Started Apr 02 02:06:40 PM PDT 24
Finished Apr 02 02:06:54 PM PDT 24
Peak memory 238732 kb
Host smart-21e65b2c-d921-4fcc-ba53-1f2ab98b8b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374164351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2374164351
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2998473291
Short name T181
Test name
Test status
Simulation time 6581208680 ps
CPU time 19.71 seconds
Started Apr 02 02:06:37 PM PDT 24
Finished Apr 02 02:06:59 PM PDT 24
Peak memory 232796 kb
Host smart-f4f8aaa8-3038-4893-9c26-23c5b292eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998473291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2998473291
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1499657751
Short name T468
Test name
Test status
Simulation time 902069280 ps
CPU time 11.65 seconds
Started Apr 02 02:06:41 PM PDT 24
Finished Apr 02 02:06:53 PM PDT 24
Peak memory 220224 kb
Host smart-23dd892a-9d0f-45d0-b745-2520e2330cbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499657751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1499657751
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.787231374
Short name T692
Test name
Test status
Simulation time 28255528281 ps
CPU time 69.14 seconds
Started Apr 02 02:06:41 PM PDT 24
Finished Apr 02 02:07:51 PM PDT 24
Peak memory 216452 kb
Host smart-c729adfc-7622-45a4-b703-ab926b4ea342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787231374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.787231374
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2241699243
Short name T618
Test name
Test status
Simulation time 5497341368 ps
CPU time 16.36 seconds
Started Apr 02 02:06:36 PM PDT 24
Finished Apr 02 02:06:52 PM PDT 24
Peak memory 216404 kb
Host smart-5971dd44-5e73-4880-beb0-baa5c0c5528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241699243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2241699243
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2844005010
Short name T171
Test name
Test status
Simulation time 154158483 ps
CPU time 0.93 seconds
Started Apr 02 02:06:39 PM PDT 24
Finished Apr 02 02:06:41 PM PDT 24
Peak memory 206900 kb
Host smart-d8436da3-2f02-4a6d-84c3-b5a904dfe0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844005010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2844005010
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1871010766
Short name T466
Test name
Test status
Simulation time 103691239 ps
CPU time 0.84 seconds
Started Apr 02 02:06:37 PM PDT 24
Finished Apr 02 02:06:40 PM PDT 24
Peak memory 206148 kb
Host smart-4bdd5a68-7dcc-4575-90b5-bfb5bf912dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871010766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1871010766
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1252236485
Short name T513
Test name
Test status
Simulation time 20065768 ps
CPU time 0.71 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:06:59 PM PDT 24
Peak memory 205148 kb
Host smart-8a780621-be1a-401d-ac50-2766834747e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252236485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1252236485
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2015805439
Short name T531
Test name
Test status
Simulation time 1161705952 ps
CPU time 8.59 seconds
Started Apr 02 02:06:54 PM PDT 24
Finished Apr 02 02:07:05 PM PDT 24
Peak memory 222484 kb
Host smart-ef0f3bf7-fe0f-4049-873e-da4c3f7e1652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015805439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2015805439
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2880723857
Short name T410
Test name
Test status
Simulation time 13746423 ps
CPU time 0.74 seconds
Started Apr 02 02:06:46 PM PDT 24
Finished Apr 02 02:06:46 PM PDT 24
Peak memory 206512 kb
Host smart-ac565685-59da-430a-a7af-e6c306a8d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880723857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2880723857
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.374010946
Short name T307
Test name
Test status
Simulation time 4960838366 ps
CPU time 74.98 seconds
Started Apr 02 02:06:53 PM PDT 24
Finished Apr 02 02:08:08 PM PDT 24
Peak memory 240952 kb
Host smart-b52e1959-5060-4732-8365-3cb0b47385c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374010946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.374010946
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1662534904
Short name T621
Test name
Test status
Simulation time 198129418 ps
CPU time 2.33 seconds
Started Apr 02 02:06:48 PM PDT 24
Finished Apr 02 02:06:50 PM PDT 24
Peak memory 218664 kb
Host smart-6b4a8639-cdf0-40da-b79f-e2806cbc9544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662534904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1662534904
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.269701904
Short name T198
Test name
Test status
Simulation time 5168024993 ps
CPU time 7.76 seconds
Started Apr 02 02:06:47 PM PDT 24
Finished Apr 02 02:06:55 PM PDT 24
Peak memory 223668 kb
Host smart-bd776c7f-6eba-48fe-ad35-1c99b2b235fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269701904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.269701904
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1591187449
Short name T442
Test name
Test status
Simulation time 1078726080 ps
CPU time 11.86 seconds
Started Apr 02 02:06:52 PM PDT 24
Finished Apr 02 02:07:04 PM PDT 24
Peak memory 221844 kb
Host smart-b94b5541-5fbf-4879-997c-8c50527c34d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1591187449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1591187449
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4189491759
Short name T39
Test name
Test status
Simulation time 158991293 ps
CPU time 0.96 seconds
Started Apr 02 02:06:56 PM PDT 24
Finished Apr 02 02:06:57 PM PDT 24
Peak memory 207044 kb
Host smart-83dfc48a-425b-470e-92e5-6d8836cd1513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189491759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4189491759
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.394039847
Short name T698
Test name
Test status
Simulation time 6499801204 ps
CPU time 5.92 seconds
Started Apr 02 02:06:44 PM PDT 24
Finished Apr 02 02:06:51 PM PDT 24
Peak memory 216440 kb
Host smart-90eec1d4-8926-446f-8439-3404d6487836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394039847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.394039847
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3904247854
Short name T731
Test name
Test status
Simulation time 88847336 ps
CPU time 1.89 seconds
Started Apr 02 02:06:53 PM PDT 24
Finished Apr 02 02:06:55 PM PDT 24
Peak memory 216356 kb
Host smart-a713d5dc-aff8-472e-a0f4-a8b0079c3d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904247854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3904247854
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.495921283
Short name T611
Test name
Test status
Simulation time 72142768 ps
CPU time 0.93 seconds
Started Apr 02 02:06:45 PM PDT 24
Finished Apr 02 02:06:46 PM PDT 24
Peak memory 206752 kb
Host smart-8e9d0315-8ba4-40fc-8a2f-e9d10b24ba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495921283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.495921283
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3741907479
Short name T278
Test name
Test status
Simulation time 6256406811 ps
CPU time 11.83 seconds
Started Apr 02 02:06:54 PM PDT 24
Finished Apr 02 02:07:08 PM PDT 24
Peak memory 232852 kb
Host smart-0776ca98-4e0a-4c15-8e06-b857d2ffafe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741907479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3741907479
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2833350942
Short name T685
Test name
Test status
Simulation time 38264521 ps
CPU time 0.72 seconds
Started Apr 02 02:07:04 PM PDT 24
Finished Apr 02 02:07:06 PM PDT 24
Peak memory 204792 kb
Host smart-adce929c-287f-463c-8886-a5f5dea3dc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833350942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2833350942
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3601899632
Short name T457
Test name
Test status
Simulation time 55067088 ps
CPU time 0.76 seconds
Started Apr 02 02:06:55 PM PDT 24
Finished Apr 02 02:06:57 PM PDT 24
Peak memory 206496 kb
Host smart-2d5895cf-6a80-40f3-869e-add416d61d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601899632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3601899632
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2195864291
Short name T688
Test name
Test status
Simulation time 10207513324 ps
CPU time 41.31 seconds
Started Apr 02 02:07:00 PM PDT 24
Finished Apr 02 02:07:41 PM PDT 24
Peak memory 240072 kb
Host smart-12a7bc90-1b1c-40ba-b16b-befd922f5885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195864291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2195864291
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2981724428
Short name T492
Test name
Test status
Simulation time 746301795 ps
CPU time 3.8 seconds
Started Apr 02 02:07:00 PM PDT 24
Finished Apr 02 02:07:04 PM PDT 24
Peak memory 219308 kb
Host smart-f63d54ff-44a1-415c-acfc-5094334379cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2981724428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2981724428
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1743200326
Short name T53
Test name
Test status
Simulation time 541017987 ps
CPU time 3.75 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:07:02 PM PDT 24
Peak memory 216168 kb
Host smart-0c74e53f-7820-4cde-af35-a8509df70380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743200326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1743200326
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3744843561
Short name T656
Test name
Test status
Simulation time 2759951890 ps
CPU time 9.99 seconds
Started Apr 02 02:06:59 PM PDT 24
Finished Apr 02 02:07:10 PM PDT 24
Peak memory 216396 kb
Host smart-143d32ec-6ee3-45e0-957d-655dd6e8b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744843561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3744843561
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3332305038
Short name T524
Test name
Test status
Simulation time 314375193 ps
CPU time 4.19 seconds
Started Apr 02 02:06:57 PM PDT 24
Finished Apr 02 02:07:01 PM PDT 24
Peak memory 216388 kb
Host smart-f08c7990-166c-4757-ad35-3fb4a430689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332305038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3332305038
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.297743601
Short name T638
Test name
Test status
Simulation time 18378394 ps
CPU time 0.73 seconds
Started Apr 02 02:06:55 PM PDT 24
Finished Apr 02 02:06:57 PM PDT 24
Peak memory 205736 kb
Host smart-ec2dbd51-2429-4b0e-bf14-24fc0d8f4dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297743601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.297743601
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1417010507
Short name T507
Test name
Test status
Simulation time 124021545 ps
CPU time 0.67 seconds
Started Apr 02 02:07:14 PM PDT 24
Finished Apr 02 02:07:15 PM PDT 24
Peak memory 204800 kb
Host smart-501fc338-03f8-4ae8-a6e4-3d9568939871
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417010507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1417010507
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1375312097
Short name T629
Test name
Test status
Simulation time 30879808 ps
CPU time 1.96 seconds
Started Apr 02 02:07:06 PM PDT 24
Finished Apr 02 02:07:08 PM PDT 24
Peak memory 218884 kb
Host smart-8ad8084b-9165-4cf1-8432-ddbdcc2941d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375312097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1375312097
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1395484223
Short name T667
Test name
Test status
Simulation time 40820782 ps
CPU time 0.78 seconds
Started Apr 02 02:07:02 PM PDT 24
Finished Apr 02 02:07:04 PM PDT 24
Peak memory 206388 kb
Host smart-287de724-6c1f-4964-a7d1-70052ed9c15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395484223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1395484223
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2805017783
Short name T309
Test name
Test status
Simulation time 806185964 ps
CPU time 23.66 seconds
Started Apr 02 02:07:08 PM PDT 24
Finished Apr 02 02:07:31 PM PDT 24
Peak memory 239192 kb
Host smart-3d3e1a08-16f7-4e2c-9c63-bbe37aaf411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805017783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2805017783
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.120674780
Short name T201
Test name
Test status
Simulation time 5900412860 ps
CPU time 6.77 seconds
Started Apr 02 02:07:07 PM PDT 24
Finished Apr 02 02:07:14 PM PDT 24
Peak memory 222948 kb
Host smart-d1903ba1-3de5-4387-8809-a999b37061dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120674780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.120674780
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.445415009
Short name T432
Test name
Test status
Simulation time 879616463 ps
CPU time 9.51 seconds
Started Apr 02 02:07:06 PM PDT 24
Finished Apr 02 02:07:16 PM PDT 24
Peak memory 222932 kb
Host smart-e12b24d1-7613-40b7-8ac2-960912bb4052
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=445415009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.445415009
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1261580190
Short name T640
Test name
Test status
Simulation time 3592834579 ps
CPU time 6.47 seconds
Started Apr 02 02:07:05 PM PDT 24
Finished Apr 02 02:07:12 PM PDT 24
Peak memory 216432 kb
Host smart-61048960-9eab-4478-ac17-d88df14e3e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261580190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1261580190
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1696205177
Short name T644
Test name
Test status
Simulation time 1489272760 ps
CPU time 3.55 seconds
Started Apr 02 02:07:05 PM PDT 24
Finished Apr 02 02:07:09 PM PDT 24
Peak memory 216360 kb
Host smart-2354c844-0ef7-43ea-b526-4bcafe6ffd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696205177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1696205177
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1291407409
Short name T472
Test name
Test status
Simulation time 284583937 ps
CPU time 3.51 seconds
Started Apr 02 02:07:08 PM PDT 24
Finished Apr 02 02:07:11 PM PDT 24
Peak memory 216548 kb
Host smart-83ea8284-8225-4cfe-985a-4fa4a057bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291407409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1291407409
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.314506133
Short name T170
Test name
Test status
Simulation time 55394568 ps
CPU time 0.82 seconds
Started Apr 02 02:07:02 PM PDT 24
Finished Apr 02 02:07:03 PM PDT 24
Peak memory 205736 kb
Host smart-a227c2f1-3717-4b4f-86af-5061df8e1571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314506133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.314506133
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1964057289
Short name T411
Test name
Test status
Simulation time 47198608 ps
CPU time 0.69 seconds
Started Apr 02 02:07:22 PM PDT 24
Finished Apr 02 02:07:22 PM PDT 24
Peak memory 205372 kb
Host smart-e528de16-22da-4d69-8d3d-805d0ca302d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964057289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1964057289
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2164074486
Short name T537
Test name
Test status
Simulation time 78007453 ps
CPU time 0.78 seconds
Started Apr 02 02:07:12 PM PDT 24
Finished Apr 02 02:07:13 PM PDT 24
Peak memory 206480 kb
Host smart-b29e7245-bc96-4823-b107-542f44471d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164074486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2164074486
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3364718900
Short name T300
Test name
Test status
Simulation time 13287884747 ps
CPU time 92.59 seconds
Started Apr 02 02:07:21 PM PDT 24
Finished Apr 02 02:08:54 PM PDT 24
Peak memory 252088 kb
Host smart-0eb399e5-36fb-4ec8-a484-765c87697a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364718900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3364718900
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1593204541
Short name T47
Test name
Test status
Simulation time 1047744634 ps
CPU time 8.17 seconds
Started Apr 02 02:07:19 PM PDT 24
Finished Apr 02 02:07:28 PM PDT 24
Peak memory 238848 kb
Host smart-35ce8a4f-4d9e-4b56-a3fb-9db3d4ca81d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593204541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1593204541
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1305242048
Short name T706
Test name
Test status
Simulation time 2956954134 ps
CPU time 14.17 seconds
Started Apr 02 02:07:19 PM PDT 24
Finished Apr 02 02:07:34 PM PDT 24
Peak memory 219264 kb
Host smart-cde37764-cd45-4a22-9f56-c1570235316c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1305242048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1305242048
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.695230487
Short name T687
Test name
Test status
Simulation time 1146748727 ps
CPU time 16 seconds
Started Apr 02 02:07:14 PM PDT 24
Finished Apr 02 02:07:30 PM PDT 24
Peak memory 216432 kb
Host smart-7f0d3b7c-3c85-48fa-afee-c6e26609968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695230487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.695230487
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2053065371
Short name T430
Test name
Test status
Simulation time 3243817904 ps
CPU time 3.4 seconds
Started Apr 02 02:07:21 PM PDT 24
Finished Apr 02 02:07:25 PM PDT 24
Peak memory 216320 kb
Host smart-0d33d15a-5a29-40cc-807f-d042eb929227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053065371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2053065371
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.552026772
Short name T606
Test name
Test status
Simulation time 242527974 ps
CPU time 8.54 seconds
Started Apr 02 02:07:14 PM PDT 24
Finished Apr 02 02:07:22 PM PDT 24
Peak memory 216492 kb
Host smart-8ff0388f-5a16-4d43-bcb1-650ab76411bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552026772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.552026772
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.928209621
Short name T590
Test name
Test status
Simulation time 132127109 ps
CPU time 0.94 seconds
Started Apr 02 02:07:20 PM PDT 24
Finished Apr 02 02:07:21 PM PDT 24
Peak memory 206732 kb
Host smart-31500b14-9757-4988-8975-e65751737c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928209621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.928209621
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.300539682
Short name T28
Test name
Test status
Simulation time 36633694 ps
CPU time 0.72 seconds
Started Apr 02 02:07:30 PM PDT 24
Finished Apr 02 02:07:31 PM PDT 24
Peak memory 205384 kb
Host smart-4c29641b-abf2-4c2f-874c-cc702996207b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300539682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.300539682
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.218005088
Short name T535
Test name
Test status
Simulation time 16096708 ps
CPU time 0.75 seconds
Started Apr 02 02:07:21 PM PDT 24
Finished Apr 02 02:07:22 PM PDT 24
Peak memory 206440 kb
Host smart-de579ee1-e7fa-4ebe-9f61-5fb424a5653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218005088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.218005088
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2756655971
Short name T7
Test name
Test status
Simulation time 1259585349 ps
CPU time 22.53 seconds
Started Apr 02 02:07:29 PM PDT 24
Finished Apr 02 02:07:52 PM PDT 24
Peak memory 256140 kb
Host smart-2876d693-6036-4521-98fc-4f203e8173ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756655971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2756655971
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3630693710
Short name T690
Test name
Test status
Simulation time 13816161418 ps
CPU time 19.9 seconds
Started Apr 02 02:07:26 PM PDT 24
Finished Apr 02 02:07:48 PM PDT 24
Peak memory 232812 kb
Host smart-d7a68d72-311d-44ab-b558-7d8af2ce3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630693710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3630693710
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3085466908
Short name T340
Test name
Test status
Simulation time 46896788130 ps
CPU time 26.22 seconds
Started Apr 02 02:07:24 PM PDT 24
Finished Apr 02 02:07:51 PM PDT 24
Peak memory 230528 kb
Host smart-801110a0-e5c6-4590-801f-6f619b4e7702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085466908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3085466908
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1380678883
Short name T595
Test name
Test status
Simulation time 9147467444 ps
CPU time 22.75 seconds
Started Apr 02 02:07:27 PM PDT 24
Finished Apr 02 02:07:52 PM PDT 24
Peak memory 218952 kb
Host smart-c7f2f7d8-3dc0-45e1-a145-d2c7ebf54d01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1380678883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1380678883
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.961055883
Short name T502
Test name
Test status
Simulation time 3619131724 ps
CPU time 11.05 seconds
Started Apr 02 02:07:23 PM PDT 24
Finished Apr 02 02:07:34 PM PDT 24
Peak memory 216408 kb
Host smart-5c002991-7c55-422e-8f74-406b5a0fb425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961055883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.961055883
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1220174767
Short name T718
Test name
Test status
Simulation time 360312489 ps
CPU time 2.11 seconds
Started Apr 02 02:07:25 PM PDT 24
Finished Apr 02 02:07:28 PM PDT 24
Peak memory 216380 kb
Host smart-70e29783-9829-4e2c-970f-5e1b1c34ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220174767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1220174767
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1366024553
Short name T603
Test name
Test status
Simulation time 118054431 ps
CPU time 0.98 seconds
Started Apr 02 02:07:24 PM PDT 24
Finished Apr 02 02:07:25 PM PDT 24
Peak memory 205736 kb
Host smart-90694bf2-2801-4953-be3e-ee3d2c9d9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366024553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1366024553
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3390485898
Short name T86
Test name
Test status
Simulation time 396633107 ps
CPU time 5.44 seconds
Started Apr 02 02:07:29 PM PDT 24
Finished Apr 02 02:07:35 PM PDT 24
Peak memory 218332 kb
Host smart-6c5c806d-8ea2-4cc3-ab79-a30c12f49fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390485898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3390485898
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.140793925
Short name T477
Test name
Test status
Simulation time 22688302 ps
CPU time 0.74 seconds
Started Apr 02 02:07:41 PM PDT 24
Finished Apr 02 02:07:42 PM PDT 24
Peak memory 205716 kb
Host smart-6edd3f84-f27c-4505-a29a-6ff49cb29401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140793925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.140793925
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1356993940
Short name T57
Test name
Test status
Simulation time 135758898 ps
CPU time 3.5 seconds
Started Apr 02 02:07:36 PM PDT 24
Finished Apr 02 02:07:40 PM PDT 24
Peak memory 222940 kb
Host smart-f9486f65-1cba-47c5-be01-72f34d47d90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356993940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1356993940
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3681796301
Short name T16
Test name
Test status
Simulation time 41846152 ps
CPU time 0.73 seconds
Started Apr 02 02:07:31 PM PDT 24
Finished Apr 02 02:07:32 PM PDT 24
Peak memory 206808 kb
Host smart-719278a4-b001-4842-af8d-c0343b34cf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681796301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3681796301
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.265339496
Short name T697
Test name
Test status
Simulation time 28844014639 ps
CPU time 70.06 seconds
Started Apr 02 02:07:40 PM PDT 24
Finished Apr 02 02:08:50 PM PDT 24
Peak memory 234020 kb
Host smart-4c28d3f2-e8f4-4832-8488-3d070b985b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265339496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.265339496
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1867749528
Short name T3
Test name
Test status
Simulation time 874102648 ps
CPU time 3.11 seconds
Started Apr 02 02:07:35 PM PDT 24
Finished Apr 02 02:07:38 PM PDT 24
Peak memory 223148 kb
Host smart-022f5593-6049-441c-baef-250fc63450b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867749528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1867749528
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3671355683
Short name T341
Test name
Test status
Simulation time 102550004 ps
CPU time 2.52 seconds
Started Apr 02 02:07:36 PM PDT 24
Finished Apr 02 02:07:39 PM PDT 24
Peak memory 219112 kb
Host smart-69082974-f4dd-4b79-989c-8224bffd2f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671355683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3671355683
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.493999508
Short name T327
Test name
Test status
Simulation time 212067082 ps
CPU time 2.67 seconds
Started Apr 02 02:07:32 PM PDT 24
Finished Apr 02 02:07:36 PM PDT 24
Peak memory 222680 kb
Host smart-a341e848-3cde-412b-9ad9-5e675389a682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493999508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.493999508
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.292380148
Short name T617
Test name
Test status
Simulation time 809546706 ps
CPU time 9.04 seconds
Started Apr 02 02:07:39 PM PDT 24
Finished Apr 02 02:07:49 PM PDT 24
Peak memory 222300 kb
Host smart-de1e2c08-cdaa-4abb-8f87-da5d50ccbbd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=292380148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.292380148
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.516787255
Short name T40
Test name
Test status
Simulation time 137232247 ps
CPU time 0.89 seconds
Started Apr 02 02:07:39 PM PDT 24
Finished Apr 02 02:07:40 PM PDT 24
Peak memory 206692 kb
Host smart-75ad6c18-8ba8-485f-8e21-ab2cda931970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516787255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.516787255
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.693319543
Short name T18
Test name
Test status
Simulation time 13191218187 ps
CPU time 15.56 seconds
Started Apr 02 02:07:31 PM PDT 24
Finished Apr 02 02:07:47 PM PDT 24
Peak memory 216356 kb
Host smart-bd09527b-fa55-45ab-a94a-31726fe3dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693319543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.693319543
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.46734968
Short name T554
Test name
Test status
Simulation time 53073865244 ps
CPU time 10.77 seconds
Started Apr 02 02:07:31 PM PDT 24
Finished Apr 02 02:07:42 PM PDT 24
Peak memory 216440 kb
Host smart-a4e7c4bb-ac32-4abf-af4a-f952e1c88cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46734968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.46734968
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.282968241
Short name T623
Test name
Test status
Simulation time 63617595 ps
CPU time 1.44 seconds
Started Apr 02 02:07:31 PM PDT 24
Finished Apr 02 02:07:33 PM PDT 24
Peak memory 216376 kb
Host smart-9cad353d-6308-4324-a989-6f79964e06cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282968241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.282968241
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.21268105
Short name T529
Test name
Test status
Simulation time 53508221 ps
CPU time 0.77 seconds
Started Apr 02 02:07:32 PM PDT 24
Finished Apr 02 02:07:34 PM PDT 24
Peak memory 205752 kb
Host smart-5bde8be1-0aec-42a2-8c24-52225587277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21268105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.21268105
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.813375567
Short name T579
Test name
Test status
Simulation time 13582503 ps
CPU time 0.68 seconds
Started Apr 02 02:07:52 PM PDT 24
Finished Apr 02 02:07:52 PM PDT 24
Peak memory 205372 kb
Host smart-c216bbd6-29e2-45db-94f1-b22728ba8574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813375567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.813375567
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.102981642
Short name T489
Test name
Test status
Simulation time 47971044 ps
CPU time 0.77 seconds
Started Apr 02 02:07:41 PM PDT 24
Finished Apr 02 02:07:43 PM PDT 24
Peak memory 206792 kb
Host smart-5a24bef6-1c7c-4e24-852b-af8f942e352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102981642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.102981642
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.632760597
Short name T347
Test name
Test status
Simulation time 806010277 ps
CPU time 16.12 seconds
Started Apr 02 02:07:43 PM PDT 24
Finished Apr 02 02:08:01 PM PDT 24
Peak memory 239796 kb
Host smart-e9fc041c-69db-4d1d-9165-52c26489ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632760597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.632760597
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.909686490
Short name T333
Test name
Test status
Simulation time 13122641995 ps
CPU time 11.19 seconds
Started Apr 02 02:07:42 PM PDT 24
Finished Apr 02 02:07:54 PM PDT 24
Peak memory 223052 kb
Host smart-0181ff96-3e2c-4e92-9164-ed4428d98fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909686490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.909686490
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.222062406
Short name T735
Test name
Test status
Simulation time 194146367 ps
CPU time 4.31 seconds
Started Apr 02 02:07:45 PM PDT 24
Finished Apr 02 02:07:50 PM PDT 24
Peak memory 222316 kb
Host smart-191de9d8-dc87-44e6-bdf7-9ba3504b91ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=222062406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.222062406
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3266233544
Short name T382
Test name
Test status
Simulation time 1043555034 ps
CPU time 7.81 seconds
Started Apr 02 02:07:47 PM PDT 24
Finished Apr 02 02:07:55 PM PDT 24
Peak memory 216432 kb
Host smart-d8b8dbec-d72e-4703-a2bf-297d194f8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266233544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3266233544
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.427102858
Short name T541
Test name
Test status
Simulation time 6496350649 ps
CPU time 2.59 seconds
Started Apr 02 02:07:42 PM PDT 24
Finished Apr 02 02:07:45 PM PDT 24
Peak memory 216448 kb
Host smart-2069a057-80ec-480a-aeaa-8a75f5da18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427102858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.427102858
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1592877204
Short name T400
Test name
Test status
Simulation time 32107596 ps
CPU time 1.88 seconds
Started Apr 02 02:07:41 PM PDT 24
Finished Apr 02 02:07:44 PM PDT 24
Peak memory 216468 kb
Host smart-aebdfdd7-d806-49d0-bc38-d3d5a5f3bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592877204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1592877204
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.815048269
Short name T429
Test name
Test status
Simulation time 45709995 ps
CPU time 0.8 seconds
Started Apr 02 02:07:43 PM PDT 24
Finished Apr 02 02:07:44 PM PDT 24
Peak memory 206744 kb
Host smart-eef70498-c7e0-4548-83d9-ebe2036f273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815048269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.815048269
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.626229441
Short name T235
Test name
Test status
Simulation time 2985549281 ps
CPU time 11.03 seconds
Started Apr 02 02:07:43 PM PDT 24
Finished Apr 02 02:07:54 PM PDT 24
Peak memory 217592 kb
Host smart-892540ea-e335-41aa-8243-5b501f3ca31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626229441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.626229441
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1403448844
Short name T519
Test name
Test status
Simulation time 49092776 ps
CPU time 0.71 seconds
Started Apr 02 02:08:02 PM PDT 24
Finished Apr 02 02:08:03 PM PDT 24
Peak memory 205308 kb
Host smart-7b696d6b-cd59-4e04-b2ef-2502cae05875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403448844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1403448844
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3639918380
Short name T683
Test name
Test status
Simulation time 35898045 ps
CPU time 2.37 seconds
Started Apr 02 02:07:58 PM PDT 24
Finished Apr 02 02:08:01 PM PDT 24
Peak memory 223040 kb
Host smart-c488b33f-84b1-4e38-a49c-807f5475b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639918380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3639918380
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2019755016
Short name T545
Test name
Test status
Simulation time 16758865 ps
CPU time 0.72 seconds
Started Apr 02 02:07:50 PM PDT 24
Finished Apr 02 02:07:51 PM PDT 24
Peak memory 205796 kb
Host smart-e4369e86-b054-40c5-979c-c7e5c4da9483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019755016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2019755016
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2261691884
Short name T211
Test name
Test status
Simulation time 3252815737 ps
CPU time 12.28 seconds
Started Apr 02 02:07:53 PM PDT 24
Finished Apr 02 02:08:06 PM PDT 24
Peak memory 224636 kb
Host smart-86937e19-f4d8-4882-ac01-feb9c3246466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261691884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2261691884
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2995692376
Short name T239
Test name
Test status
Simulation time 20771055593 ps
CPU time 47.12 seconds
Started Apr 02 02:07:53 PM PDT 24
Finished Apr 02 02:08:41 PM PDT 24
Peak memory 224612 kb
Host smart-805092e5-be37-4f4b-abb6-ae91a2681ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995692376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2995692376
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.988240268
Short name T585
Test name
Test status
Simulation time 1551330380 ps
CPU time 6.15 seconds
Started Apr 02 02:07:53 PM PDT 24
Finished Apr 02 02:08:00 PM PDT 24
Peak memory 218780 kb
Host smart-71d419ad-7ee4-474c-b7da-6841b26c969f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988240268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.988240268
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.678169220
Short name T625
Test name
Test status
Simulation time 469713660 ps
CPU time 6.32 seconds
Started Apr 02 02:07:50 PM PDT 24
Finished Apr 02 02:07:56 PM PDT 24
Peak memory 216404 kb
Host smart-3f1c82b4-8469-4f89-ba86-23fd3a3ff3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678169220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.678169220
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3652778481
Short name T567
Test name
Test status
Simulation time 5731379539 ps
CPU time 17.85 seconds
Started Apr 02 02:07:50 PM PDT 24
Finished Apr 02 02:08:08 PM PDT 24
Peak memory 216456 kb
Host smart-0ec573a6-9d64-4b2f-a83d-3ecc78fc5613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652778481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3652778481
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3066859890
Short name T619
Test name
Test status
Simulation time 41873881 ps
CPU time 1.07 seconds
Started Apr 02 02:07:49 PM PDT 24
Finished Apr 02 02:07:51 PM PDT 24
Peak memory 206932 kb
Host smart-7aba54f2-bf24-4f37-82db-61f7d148cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066859890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3066859890
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3783204214
Short name T460
Test name
Test status
Simulation time 567584419 ps
CPU time 0.92 seconds
Started Apr 02 02:07:51 PM PDT 24
Finished Apr 02 02:07:52 PM PDT 24
Peak memory 206752 kb
Host smart-d618e06a-1db9-4eb0-978a-588b06e66368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783204214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3783204214
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.114032333
Short name T267
Test name
Test status
Simulation time 1450276263 ps
CPU time 3.18 seconds
Started Apr 02 02:07:54 PM PDT 24
Finished Apr 02 02:07:57 PM PDT 24
Peak memory 222244 kb
Host smart-8a292256-a565-4d60-b535-ee6a58dcd602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114032333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.114032333
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.547848330
Short name T473
Test name
Test status
Simulation time 12404231 ps
CPU time 0.69 seconds
Started Apr 02 02:03:43 PM PDT 24
Finished Apr 02 02:03:43 PM PDT 24
Peak memory 205232 kb
Host smart-8efd5c52-43b1-49e6-b46b-e2a254ee78ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547848330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.547848330
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1767643560
Short name T186
Test name
Test status
Simulation time 3087487972 ps
CPU time 7.94 seconds
Started Apr 02 02:03:36 PM PDT 24
Finished Apr 02 02:03:44 PM PDT 24
Peak memory 223560 kb
Host smart-f09b3f66-d61f-4b05-b9f4-18d80cb0ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767643560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1767643560
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3826679797
Short name T635
Test name
Test status
Simulation time 19844167 ps
CPU time 0.71 seconds
Started Apr 02 02:03:28 PM PDT 24
Finished Apr 02 02:03:29 PM PDT 24
Peak memory 205440 kb
Host smart-4b87dea2-9948-4347-ab39-490e5b1bf2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826679797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3826679797
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1954619725
Short name T5
Test name
Test status
Simulation time 8225390842 ps
CPU time 117.28 seconds
Started Apr 02 02:03:40 PM PDT 24
Finished Apr 02 02:05:37 PM PDT 24
Peak memory 240736 kb
Host smart-8ad069f5-7a57-40c6-997e-7d920b0c2234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954619725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1954619725
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1110503453
Short name T351
Test name
Test status
Simulation time 4582891029 ps
CPU time 13.77 seconds
Started Apr 02 02:03:37 PM PDT 24
Finished Apr 02 02:03:51 PM PDT 24
Peak memory 232684 kb
Host smart-010ebcc4-07a6-4664-86d3-9f79ac02e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110503453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1110503453
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.796437418
Short name T734
Test name
Test status
Simulation time 251776639 ps
CPU time 1.03 seconds
Started Apr 02 02:03:27 PM PDT 24
Finished Apr 02 02:03:28 PM PDT 24
Peak memory 216788 kb
Host smart-9e1c917a-88e2-4638-80ee-b5eb51e7500b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796437418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.796437418
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.380834635
Short name T2
Test name
Test status
Simulation time 3010474753 ps
CPU time 11.43 seconds
Started Apr 02 02:03:31 PM PDT 24
Finished Apr 02 02:03:43 PM PDT 24
Peak memory 238536 kb
Host smart-35780622-9900-41b9-8214-7235d198de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380834635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.380834635
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1119702434
Short name T574
Test name
Test status
Simulation time 50321090 ps
CPU time 0.68 seconds
Started Apr 02 02:03:31 PM PDT 24
Finished Apr 02 02:03:31 PM PDT 24
Peak memory 216308 kb
Host smart-3c068334-0f63-4185-8e5a-9e1be368e194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119702434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1119702434
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1768508209
Short name T482
Test name
Test status
Simulation time 1512409886 ps
CPU time 11.25 seconds
Started Apr 02 02:03:40 PM PDT 24
Finished Apr 02 02:03:51 PM PDT 24
Peak memory 221528 kb
Host smart-5dd9d985-1269-44b5-8359-6e54059d5ddb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1768508209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1768508209
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2841044205
Short name T49
Test name
Test status
Simulation time 89531425 ps
CPU time 1.14 seconds
Started Apr 02 02:03:43 PM PDT 24
Finished Apr 02 02:03:44 PM PDT 24
Peak memory 235480 kb
Host smart-d2d6aedf-ca74-47e7-824f-a7fd8491eea5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841044205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2841044205
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4164562666
Short name T56
Test name
Test status
Simulation time 43433660708 ps
CPU time 55.26 seconds
Started Apr 02 02:03:31 PM PDT 24
Finished Apr 02 02:04:26 PM PDT 24
Peak memory 216528 kb
Host smart-c041d4ae-f235-4789-874f-5870200fc8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164562666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4164562666
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4099795808
Short name T510
Test name
Test status
Simulation time 2793966817 ps
CPU time 8.06 seconds
Started Apr 02 02:03:33 PM PDT 24
Finished Apr 02 02:03:41 PM PDT 24
Peak memory 216408 kb
Host smart-3c0538ce-30ab-49ab-80df-70a832505fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099795808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4099795808
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1741934587
Short name T752
Test name
Test status
Simulation time 161380316 ps
CPU time 1.95 seconds
Started Apr 02 02:03:33 PM PDT 24
Finished Apr 02 02:03:35 PM PDT 24
Peak memory 216332 kb
Host smart-5ce621e9-9c8c-470b-b6e7-679aa8a09ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741934587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1741934587
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.921927723
Short name T452
Test name
Test status
Simulation time 36472328 ps
CPU time 0.85 seconds
Started Apr 02 02:03:30 PM PDT 24
Finished Apr 02 02:03:31 PM PDT 24
Peak memory 206688 kb
Host smart-9b167c96-8b4c-4a86-ae25-ac01108e0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921927723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.921927723
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1391054023
Short name T612
Test name
Test status
Simulation time 15224873 ps
CPU time 0.72 seconds
Started Apr 02 02:08:14 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 205280 kb
Host smart-362f5963-c888-418f-ac9e-7f5bb7497554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391054023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1391054023
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1923000583
Short name T514
Test name
Test status
Simulation time 886339465 ps
CPU time 3.76 seconds
Started Apr 02 02:08:04 PM PDT 24
Finished Apr 02 02:08:08 PM PDT 24
Peak memory 223172 kb
Host smart-e8c886db-021d-47f2-a209-b024a4d26af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923000583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1923000583
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2843929753
Short name T741
Test name
Test status
Simulation time 61031516 ps
CPU time 0.78 seconds
Started Apr 02 02:08:00 PM PDT 24
Finished Apr 02 02:08:01 PM PDT 24
Peak memory 206492 kb
Host smart-b6d23200-7f98-4ec3-a319-a35d6bb67728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843929753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2843929753
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2985501564
Short name T303
Test name
Test status
Simulation time 52458427005 ps
CPU time 147.79 seconds
Started Apr 02 02:08:04 PM PDT 24
Finished Apr 02 02:10:32 PM PDT 24
Peak memory 251968 kb
Host smart-619824e9-91e9-4673-99d2-72094ef8b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985501564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2985501564
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.746030911
Short name T250
Test name
Test status
Simulation time 1651536505 ps
CPU time 14.24 seconds
Started Apr 02 02:08:08 PM PDT 24
Finished Apr 02 02:08:22 PM PDT 24
Peak memory 223048 kb
Host smart-a18cfbd8-1165-4e7e-a84e-38d9d7006e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746030911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.746030911
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4232801201
Short name T269
Test name
Test status
Simulation time 36413609937 ps
CPU time 20.6 seconds
Started Apr 02 02:08:07 PM PDT 24
Finished Apr 02 02:08:27 PM PDT 24
Peak memory 223564 kb
Host smart-14fb7912-cd19-4194-b0e6-597b51d92119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232801201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4232801201
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2018695174
Short name T609
Test name
Test status
Simulation time 303994308 ps
CPU time 4.07 seconds
Started Apr 02 02:08:06 PM PDT 24
Finished Apr 02 02:08:10 PM PDT 24
Peak memory 219084 kb
Host smart-915256c9-aec4-4c3f-9094-24de73a7960b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2018695174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2018695174
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.141899863
Short name T162
Test name
Test status
Simulation time 42429675 ps
CPU time 0.88 seconds
Started Apr 02 02:08:10 PM PDT 24
Finished Apr 02 02:08:10 PM PDT 24
Peak memory 205752 kb
Host smart-f47ead75-3d17-46cc-88da-39e70b6e9827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141899863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.141899863
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2592164798
Short name T631
Test name
Test status
Simulation time 42183465217 ps
CPU time 39.85 seconds
Started Apr 02 02:08:03 PM PDT 24
Finished Apr 02 02:08:44 PM PDT 24
Peak memory 216456 kb
Host smart-cca45a3e-3bfd-4f71-b772-48d06256719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592164798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2592164798
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3353467936
Short name T542
Test name
Test status
Simulation time 3773303311 ps
CPU time 11.29 seconds
Started Apr 02 02:08:04 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 216428 kb
Host smart-4f3fd992-45ed-428b-8410-3fe544470e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353467936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3353467936
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3821298500
Short name T751
Test name
Test status
Simulation time 742475411 ps
CPU time 2.1 seconds
Started Apr 02 02:08:03 PM PDT 24
Finished Apr 02 02:08:05 PM PDT 24
Peak memory 216516 kb
Host smart-a8d09581-aa18-4760-8d75-641307267c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821298500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3821298500
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1959800096
Short name T582
Test name
Test status
Simulation time 328044909 ps
CPU time 0.9 seconds
Started Apr 02 02:08:03 PM PDT 24
Finished Apr 02 02:08:04 PM PDT 24
Peak memory 206728 kb
Host smart-83525890-6dff-463d-b3cd-8007197b45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959800096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1959800096
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.843530722
Short name T281
Test name
Test status
Simulation time 8948566168 ps
CPU time 29.18 seconds
Started Apr 02 02:08:05 PM PDT 24
Finished Apr 02 02:08:35 PM PDT 24
Peak memory 224516 kb
Host smart-d64e4045-9d4c-47fb-a56f-a3849ff678c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843530722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.843530722
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2252391504
Short name T564
Test name
Test status
Simulation time 14116291 ps
CPU time 0.7 seconds
Started Apr 02 02:08:20 PM PDT 24
Finished Apr 02 02:08:21 PM PDT 24
Peak memory 205340 kb
Host smart-6413562d-316f-4212-bc4b-357cfd1be0b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252391504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2252391504
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.195411887
Short name T424
Test name
Test status
Simulation time 13321099 ps
CPU time 0.74 seconds
Started Apr 02 02:08:13 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 206396 kb
Host smart-3019d9bd-30c9-41eb-bdac-ff9c8ded9806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195411887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.195411887
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3611343198
Short name T736
Test name
Test status
Simulation time 5090859124 ps
CPU time 16.34 seconds
Started Apr 02 02:08:16 PM PDT 24
Finished Apr 02 02:08:33 PM PDT 24
Peak memory 233844 kb
Host smart-1ca8223a-6c76-4148-b8a6-b2ff305eb1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611343198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3611343198
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.679032095
Short name T270
Test name
Test status
Simulation time 9579773546 ps
CPU time 33.68 seconds
Started Apr 02 02:08:11 PM PDT 24
Finished Apr 02 02:08:45 PM PDT 24
Peak memory 223224 kb
Host smart-71321983-6213-48ac-bff6-74be599e66f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679032095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.679032095
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.836305047
Short name T249
Test name
Test status
Simulation time 749045990 ps
CPU time 3.34 seconds
Started Apr 02 02:08:13 PM PDT 24
Finished Apr 02 02:08:17 PM PDT 24
Peak memory 219156 kb
Host smart-f1fc7bdf-7fe3-40e7-9bb6-0f8a72035c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836305047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.836305047
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2827072419
Short name T213
Test name
Test status
Simulation time 554200970 ps
CPU time 5.94 seconds
Started Apr 02 02:08:12 PM PDT 24
Finished Apr 02 02:08:20 PM PDT 24
Peak memory 224304 kb
Host smart-c261a6c6-397f-4c7b-b009-2669c2e152b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827072419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2827072419
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1000399014
Short name T62
Test name
Test status
Simulation time 27739901487 ps
CPU time 22.08 seconds
Started Apr 02 02:08:14 PM PDT 24
Finished Apr 02 02:08:36 PM PDT 24
Peak memory 236112 kb
Host smart-a1ef6c3d-9427-4824-8cad-74d2cde2e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000399014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1000399014
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4069461261
Short name T569
Test name
Test status
Simulation time 1867791517 ps
CPU time 17.07 seconds
Started Apr 02 02:08:18 PM PDT 24
Finished Apr 02 02:08:35 PM PDT 24
Peak memory 220536 kb
Host smart-08d15ab6-4dfe-46a7-a11b-7f8038296126
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069461261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4069461261
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1722660428
Short name T576
Test name
Test status
Simulation time 37896675 ps
CPU time 0.89 seconds
Started Apr 02 02:08:19 PM PDT 24
Finished Apr 02 02:08:20 PM PDT 24
Peak memory 206520 kb
Host smart-0b1dd332-c4e6-4ba2-b162-703efd11279d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722660428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1722660428
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1316341703
Short name T750
Test name
Test status
Simulation time 2444720752 ps
CPU time 8.87 seconds
Started Apr 02 02:08:11 PM PDT 24
Finished Apr 02 02:08:20 PM PDT 24
Peak memory 216492 kb
Host smart-d4bf7707-23bf-44ab-bef6-d826aab86359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316341703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1316341703
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.271874312
Short name T716
Test name
Test status
Simulation time 36801940302 ps
CPU time 28.24 seconds
Started Apr 02 02:08:11 PM PDT 24
Finished Apr 02 02:08:39 PM PDT 24
Peak memory 216404 kb
Host smart-c7ea6457-1cef-4970-ae5a-6c3318f0a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271874312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.271874312
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.936581356
Short name T392
Test name
Test status
Simulation time 54395161 ps
CPU time 1.37 seconds
Started Apr 02 02:08:13 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 216392 kb
Host smart-5b662fe4-8eeb-42e4-b416-e0acb39e0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936581356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.936581356
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3300778779
Short name T546
Test name
Test status
Simulation time 82270756 ps
CPU time 0.75 seconds
Started Apr 02 02:08:13 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 205760 kb
Host smart-bc98bebb-96f8-49b7-a798-dd82bf466387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300778779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3300778779
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1143495445
Short name T409
Test name
Test status
Simulation time 27665363 ps
CPU time 0.66 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:08:27 PM PDT 24
Peak memory 205320 kb
Host smart-4203ccec-b5a2-4b51-b78f-4bee17755549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143495445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1143495445
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1206985330
Short name T715
Test name
Test status
Simulation time 27506576 ps
CPU time 0.72 seconds
Started Apr 02 02:08:19 PM PDT 24
Finished Apr 02 02:08:20 PM PDT 24
Peak memory 205436 kb
Host smart-d777cadf-f968-40be-985f-216d93193969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206985330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1206985330
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2135365671
Short name T743
Test name
Test status
Simulation time 9504198533 ps
CPU time 121.44 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:10:28 PM PDT 24
Peak memory 240352 kb
Host smart-d00db45b-5001-4769-851a-291eed083ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135365671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2135365671
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3828174643
Short name T447
Test name
Test status
Simulation time 6002249687 ps
CPU time 6.21 seconds
Started Apr 02 02:08:26 PM PDT 24
Finished Apr 02 02:08:32 PM PDT 24
Peak memory 223064 kb
Host smart-48546d80-1b48-43d0-b222-93d6280905ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3828174643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3828174643
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2477982888
Short name T381
Test name
Test status
Simulation time 7195439574 ps
CPU time 31 seconds
Started Apr 02 02:08:19 PM PDT 24
Finished Apr 02 02:08:50 PM PDT 24
Peak memory 216496 kb
Host smart-8e409566-9b82-4fb3-8e79-1c73fafca568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477982888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2477982888
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1600331533
Short name T104
Test name
Test status
Simulation time 9209784997 ps
CPU time 8.59 seconds
Started Apr 02 02:08:21 PM PDT 24
Finished Apr 02 02:08:30 PM PDT 24
Peak memory 216412 kb
Host smart-7ac2038b-e3b2-4b8e-891b-6e4d1a63c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600331533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1600331533
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2808617259
Short name T60
Test name
Test status
Simulation time 425348351 ps
CPU time 3.41 seconds
Started Apr 02 02:08:27 PM PDT 24
Finished Apr 02 02:08:31 PM PDT 24
Peak memory 216436 kb
Host smart-d59cc606-d8be-4523-8b64-fdb9a1c6d914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808617259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2808617259
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1907353916
Short name T445
Test name
Test status
Simulation time 222093021 ps
CPU time 1 seconds
Started Apr 02 02:08:23 PM PDT 24
Finished Apr 02 02:08:25 PM PDT 24
Peak memory 206680 kb
Host smart-85d47ad3-22d8-42a4-95ef-5c436679496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907353916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1907353916
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3949380401
Short name T561
Test name
Test status
Simulation time 16999906 ps
CPU time 0.7 seconds
Started Apr 02 02:08:38 PM PDT 24
Finished Apr 02 02:08:39 PM PDT 24
Peak memory 204780 kb
Host smart-26e642a3-47d3-4bff-a779-853331867983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949380401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3949380401
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4087554634
Short name T168
Test name
Test status
Simulation time 8151594558 ps
CPU time 20.44 seconds
Started Apr 02 02:08:33 PM PDT 24
Finished Apr 02 02:08:54 PM PDT 24
Peak memory 224528 kb
Host smart-a48ca9af-e92c-4afa-965c-7cdc90e30883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087554634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4087554634
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.380392751
Short name T648
Test name
Test status
Simulation time 66119625 ps
CPU time 0.75 seconds
Started Apr 02 02:08:32 PM PDT 24
Finished Apr 02 02:08:32 PM PDT 24
Peak memory 206472 kb
Host smart-5309f5e2-9d38-46f0-93c4-36e49457167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380392751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.380392751
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1229579349
Short name T193
Test name
Test status
Simulation time 239978671 ps
CPU time 3.16 seconds
Started Apr 02 02:08:30 PM PDT 24
Finished Apr 02 02:08:33 PM PDT 24
Peak memory 222788 kb
Host smart-f2dfc04a-98c7-4c58-9878-78e7150fc11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229579349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1229579349
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.418709500
Short name T321
Test name
Test status
Simulation time 3778060565 ps
CPU time 18.94 seconds
Started Apr 02 02:08:30 PM PDT 24
Finished Apr 02 02:08:49 PM PDT 24
Peak memory 232048 kb
Host smart-6651fb3f-bfcc-4f37-b452-3533c7f255a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418709500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.418709500
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2518323209
Short name T160
Test name
Test status
Simulation time 42602239 ps
CPU time 0.92 seconds
Started Apr 02 02:08:38 PM PDT 24
Finished Apr 02 02:08:39 PM PDT 24
Peak memory 206836 kb
Host smart-2031d254-5e5f-4639-80dd-e2a02e2a5be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518323209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2518323209
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3934431747
Short name T55
Test name
Test status
Simulation time 13368863374 ps
CPU time 34.03 seconds
Started Apr 02 02:08:31 PM PDT 24
Finished Apr 02 02:09:05 PM PDT 24
Peak memory 216468 kb
Host smart-bec4410b-1e54-418a-bfb3-bd332be0042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934431747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3934431747
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2050823091
Short name T547
Test name
Test status
Simulation time 51965890261 ps
CPU time 36.09 seconds
Started Apr 02 02:08:31 PM PDT 24
Finished Apr 02 02:09:08 PM PDT 24
Peak memory 216452 kb
Host smart-e48ebd80-7902-4664-95d0-24743bd17fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050823091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2050823091
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1051633666
Short name T406
Test name
Test status
Simulation time 436208347 ps
CPU time 3.44 seconds
Started Apr 02 02:08:29 PM PDT 24
Finished Apr 02 02:08:33 PM PDT 24
Peak memory 216408 kb
Host smart-df438f28-c9c5-4f25-be17-0a0edb54dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051633666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1051633666
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.351371007
Short name T479
Test name
Test status
Simulation time 280779903 ps
CPU time 0.77 seconds
Started Apr 02 02:08:39 PM PDT 24
Finished Apr 02 02:08:40 PM PDT 24
Peak memory 205720 kb
Host smart-65e44d23-378a-4f82-b08a-41852f27806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351371007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.351371007
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.186300397
Short name T260
Test name
Test status
Simulation time 678561691 ps
CPU time 4.58 seconds
Started Apr 02 02:08:36 PM PDT 24
Finished Apr 02 02:08:43 PM PDT 24
Peak memory 218832 kb
Host smart-b432d06a-4d8a-44e4-8391-6a77ce450940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186300397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.186300397
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3368798008
Short name T643
Test name
Test status
Simulation time 25919422 ps
CPU time 0.68 seconds
Started Apr 02 02:08:46 PM PDT 24
Finished Apr 02 02:08:47 PM PDT 24
Peak memory 205380 kb
Host smart-65efae71-2373-4509-b2bf-45b1d00921cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368798008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3368798008
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4150976574
Short name T533
Test name
Test status
Simulation time 22475076 ps
CPU time 0.76 seconds
Started Apr 02 02:08:37 PM PDT 24
Finished Apr 02 02:08:38 PM PDT 24
Peak memory 206476 kb
Host smart-a755ce22-f05a-47e7-9e8b-89d68b19efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150976574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4150976574
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2885821255
Short name T296
Test name
Test status
Simulation time 8426111567 ps
CPU time 109.97 seconds
Started Apr 02 02:08:44 PM PDT 24
Finished Apr 02 02:10:35 PM PDT 24
Peak memory 249280 kb
Host smart-dfef44b9-237c-45b5-aa3f-4620a84859cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885821255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2885821255
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.293814075
Short name T173
Test name
Test status
Simulation time 1623799964 ps
CPU time 21.95 seconds
Started Apr 02 02:08:40 PM PDT 24
Finished Apr 02 02:09:02 PM PDT 24
Peak memory 219816 kb
Host smart-3dbd493a-6ffb-41dd-abbd-4ce98c55a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293814075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.293814075
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1076008583
Short name T216
Test name
Test status
Simulation time 1593507740 ps
CPU time 2.88 seconds
Started Apr 02 02:08:41 PM PDT 24
Finished Apr 02 02:08:44 PM PDT 24
Peak memory 218948 kb
Host smart-b8d6ac17-29b0-4899-a387-f9de3a81316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076008583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1076008583
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1115566108
Short name T661
Test name
Test status
Simulation time 721979700 ps
CPU time 3.96 seconds
Started Apr 02 02:08:44 PM PDT 24
Finished Apr 02 02:08:49 PM PDT 24
Peak memory 222916 kb
Host smart-07be8c32-d9e7-4e11-be0f-8479d6056bac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1115566108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1115566108
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2694833831
Short name T462
Test name
Test status
Simulation time 19701882358 ps
CPU time 17.53 seconds
Started Apr 02 02:08:38 PM PDT 24
Finished Apr 02 02:08:56 PM PDT 24
Peak memory 216444 kb
Host smart-86a39718-baf0-456b-bcfa-be0c0d65e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694833831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2694833831
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1385863703
Short name T671
Test name
Test status
Simulation time 396350890 ps
CPU time 3.03 seconds
Started Apr 02 02:08:40 PM PDT 24
Finished Apr 02 02:08:43 PM PDT 24
Peak memory 216352 kb
Host smart-c6c343ac-bb99-4168-bf8b-4d9e83964de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385863703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1385863703
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.503558162
Short name T608
Test name
Test status
Simulation time 38600969 ps
CPU time 0.71 seconds
Started Apr 02 02:08:36 PM PDT 24
Finished Apr 02 02:08:38 PM PDT 24
Peak memory 205772 kb
Host smart-1feaccea-dd46-4ed2-a899-f881f2362d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503558162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.503558162
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.441318183
Short name T577
Test name
Test status
Simulation time 14377927 ps
CPU time 0.7 seconds
Started Apr 02 02:08:56 PM PDT 24
Finished Apr 02 02:08:57 PM PDT 24
Peak memory 205308 kb
Host smart-30e1e164-b801-4ba6-95dd-d5f46b18b5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441318183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.441318183
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2683453256
Short name T497
Test name
Test status
Simulation time 31712332 ps
CPU time 0.74 seconds
Started Apr 02 02:08:48 PM PDT 24
Finished Apr 02 02:08:49 PM PDT 24
Peak memory 205376 kb
Host smart-9e8f63a4-8935-4e26-8c08-f2b43733fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683453256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2683453256
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1965927877
Short name T681
Test name
Test status
Simulation time 608352273 ps
CPU time 3.22 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:08:54 PM PDT 24
Peak memory 220112 kb
Host smart-434be490-c62d-4e8a-82ed-bb8c558c57aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1965927877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1965927877
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1649146854
Short name T684
Test name
Test status
Simulation time 34848098312 ps
CPU time 19.82 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:09:11 PM PDT 24
Peak memory 216480 kb
Host smart-6c0149e6-c94b-4644-ad36-5e42e71f3538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649146854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1649146854
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2265932719
Short name T413
Test name
Test status
Simulation time 1507562883 ps
CPU time 7.7 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:08:59 PM PDT 24
Peak memory 216344 kb
Host smart-4ac2432a-96fd-49df-86a6-61c36dc467fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265932719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2265932719
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1464221951
Short name T484
Test name
Test status
Simulation time 464039323 ps
CPU time 2.09 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:08:53 PM PDT 24
Peak memory 216444 kb
Host smart-daf64c88-5036-4b8b-ba18-c1a211006468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464221951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1464221951
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3742556745
Short name T464
Test name
Test status
Simulation time 39095833 ps
CPU time 0.9 seconds
Started Apr 02 02:08:51 PM PDT 24
Finished Apr 02 02:08:52 PM PDT 24
Peak memory 206716 kb
Host smart-fda46888-fb73-4af9-91bf-760b8365ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742556745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3742556745
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3684493042
Short name T184
Test name
Test status
Simulation time 328960950 ps
CPU time 5.09 seconds
Started Apr 02 02:08:52 PM PDT 24
Finished Apr 02 02:08:58 PM PDT 24
Peak memory 223016 kb
Host smart-bfd00b8d-f46f-4a81-b517-1dcda7d49a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684493042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3684493042
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1349215060
Short name T679
Test name
Test status
Simulation time 60704393 ps
CPU time 0.69 seconds
Started Apr 02 02:09:10 PM PDT 24
Finished Apr 02 02:09:12 PM PDT 24
Peak memory 204728 kb
Host smart-4abd2919-c728-4e41-abde-6b1c14f2476a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349215060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1349215060
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2425240695
Short name T481
Test name
Test status
Simulation time 20565320 ps
CPU time 0.77 seconds
Started Apr 02 02:08:55 PM PDT 24
Finished Apr 02 02:08:56 PM PDT 24
Peak memory 206816 kb
Host smart-75484d9e-392f-40b1-ac9a-e4fa63d6f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425240695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2425240695
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4150000917
Short name T320
Test name
Test status
Simulation time 2502380690 ps
CPU time 17.67 seconds
Started Apr 02 02:09:02 PM PDT 24
Finished Apr 02 02:09:20 PM PDT 24
Peak memory 235836 kb
Host smart-6194734b-a65a-47b3-8338-10638cbaba58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150000917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4150000917
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2556213668
Short name T238
Test name
Test status
Simulation time 3840975272 ps
CPU time 12.51 seconds
Started Apr 02 02:09:02 PM PDT 24
Finished Apr 02 02:09:15 PM PDT 24
Peak memory 232876 kb
Host smart-72553e3b-481b-4b4f-9ef8-9b8013644031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556213668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2556213668
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.679455345
Short name T594
Test name
Test status
Simulation time 564881310 ps
CPU time 7.71 seconds
Started Apr 02 02:09:07 PM PDT 24
Finished Apr 02 02:09:15 PM PDT 24
Peak memory 220196 kb
Host smart-ba015bcf-9db6-4a23-b224-ed3821a697a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=679455345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.679455345
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.652210152
Short name T668
Test name
Test status
Simulation time 44414065 ps
CPU time 0.88 seconds
Started Apr 02 02:09:08 PM PDT 24
Finished Apr 02 02:09:09 PM PDT 24
Peak memory 206840 kb
Host smart-cdfa9275-cab8-45b0-9185-5ee374ba06dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652210152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.652210152
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4167761497
Short name T695
Test name
Test status
Simulation time 3476066509 ps
CPU time 4.98 seconds
Started Apr 02 02:08:59 PM PDT 24
Finished Apr 02 02:09:04 PM PDT 24
Peak memory 216480 kb
Host smart-5a6617fa-c3b4-46a4-b875-4518e510d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167761497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4167761497
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1496302517
Short name T433
Test name
Test status
Simulation time 975722462 ps
CPU time 7.22 seconds
Started Apr 02 02:08:59 PM PDT 24
Finished Apr 02 02:09:07 PM PDT 24
Peak memory 216364 kb
Host smart-7d410280-6782-4963-80c6-c7358ac218ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496302517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1496302517
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3074039133
Short name T521
Test name
Test status
Simulation time 42911217 ps
CPU time 1.44 seconds
Started Apr 02 02:08:59 PM PDT 24
Finished Apr 02 02:09:01 PM PDT 24
Peak memory 216384 kb
Host smart-420c9499-2495-44ee-8cdf-a29a60928014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074039133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3074039133
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.578163660
Short name T540
Test name
Test status
Simulation time 44584845 ps
CPU time 0.8 seconds
Started Apr 02 02:09:00 PM PDT 24
Finished Apr 02 02:09:01 PM PDT 24
Peak memory 205652 kb
Host smart-91b11958-84b3-4a02-8f79-4b8ccf44582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578163660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.578163660
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3957661696
Short name T599
Test name
Test status
Simulation time 11876658 ps
CPU time 0.67 seconds
Started Apr 02 02:09:14 PM PDT 24
Finished Apr 02 02:09:19 PM PDT 24
Peak memory 205280 kb
Host smart-6987f76c-f7ea-46e4-bca8-e5fd218efd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957661696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3957661696
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.221279123
Short name T454
Test name
Test status
Simulation time 379361535 ps
CPU time 3.51 seconds
Started Apr 02 02:09:10 PM PDT 24
Finished Apr 02 02:09:14 PM PDT 24
Peak memory 223144 kb
Host smart-b4c2d329-cb4c-48da-94e4-c35c0d2e814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221279123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.221279123
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3694109312
Short name T566
Test name
Test status
Simulation time 41015367 ps
CPU time 0.73 seconds
Started Apr 02 02:09:10 PM PDT 24
Finished Apr 02 02:09:12 PM PDT 24
Peak memory 206452 kb
Host smart-004f2763-5286-4d83-b2b3-7b06a6626010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694109312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3694109312
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2757953806
Short name T299
Test name
Test status
Simulation time 46447901223 ps
CPU time 66.86 seconds
Started Apr 02 02:09:14 PM PDT 24
Finished Apr 02 02:10:25 PM PDT 24
Peak memory 253760 kb
Host smart-735b4b83-d5f0-4f13-a733-f2ebd7bdbbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757953806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2757953806
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2734019906
Short name T265
Test name
Test status
Simulation time 4434050006 ps
CPU time 13.5 seconds
Started Apr 02 02:09:12 PM PDT 24
Finished Apr 02 02:09:26 PM PDT 24
Peak memory 224732 kb
Host smart-5d2fefe0-fed5-4266-9628-6f9578a573f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734019906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2734019906
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3935925190
Short name T346
Test name
Test status
Simulation time 841367819 ps
CPU time 4.66 seconds
Started Apr 02 02:09:11 PM PDT 24
Finished Apr 02 02:09:16 PM PDT 24
Peak memory 232388 kb
Host smart-391582dd-dba5-421b-b2bb-5305b0fb920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935925190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3935925190
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1905700410
Short name T412
Test name
Test status
Simulation time 73315013 ps
CPU time 3.47 seconds
Started Apr 02 02:09:11 PM PDT 24
Finished Apr 02 02:09:15 PM PDT 24
Peak memory 221872 kb
Host smart-4be8d33c-ca29-4354-825c-1c66dfbe9ef9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905700410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1905700410
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.966804779
Short name T747
Test name
Test status
Simulation time 1925384005 ps
CPU time 23.19 seconds
Started Apr 02 02:09:10 PM PDT 24
Finished Apr 02 02:09:34 PM PDT 24
Peak memory 216540 kb
Host smart-4c658390-b7aa-4194-b0e3-cd8a2a92fd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966804779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.966804779
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3339635700
Short name T646
Test name
Test status
Simulation time 32517713275 ps
CPU time 20.43 seconds
Started Apr 02 02:09:06 PM PDT 24
Finished Apr 02 02:09:27 PM PDT 24
Peak memory 216452 kb
Host smart-95cca104-7722-4bf3-92e4-a503d3518e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339635700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3339635700
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2154243659
Short name T17
Test name
Test status
Simulation time 426063257 ps
CPU time 2.56 seconds
Started Apr 02 02:09:11 PM PDT 24
Finished Apr 02 02:09:14 PM PDT 24
Peak memory 216440 kb
Host smart-89c40756-2c4a-420a-b807-e3b70e6e43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154243659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2154243659
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1400983695
Short name T730
Test name
Test status
Simulation time 26827747 ps
CPU time 0.78 seconds
Started Apr 02 02:09:05 PM PDT 24
Finished Apr 02 02:09:06 PM PDT 24
Peak memory 205672 kb
Host smart-ddc10c34-f979-413a-96d6-42b898a15829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400983695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1400983695
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3734765773
Short name T470
Test name
Test status
Simulation time 13371350 ps
CPU time 0.7 seconds
Started Apr 02 02:09:27 PM PDT 24
Finished Apr 02 02:09:28 PM PDT 24
Peak memory 205320 kb
Host smart-8f1847e6-f855-4bc2-969c-18a82650b889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734765773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3734765773
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1078902030
Short name T23
Test name
Test status
Simulation time 1348414352 ps
CPU time 4.54 seconds
Started Apr 02 02:09:22 PM PDT 24
Finished Apr 02 02:09:27 PM PDT 24
Peak memory 219616 kb
Host smart-91cf097b-b755-4c42-bda1-12d8c060ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078902030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1078902030
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2192963016
Short name T602
Test name
Test status
Simulation time 16522804 ps
CPU time 0.78 seconds
Started Apr 02 02:09:25 PM PDT 24
Finished Apr 02 02:09:26 PM PDT 24
Peak memory 205468 kb
Host smart-c0890b85-e1bb-4e72-a072-be203a5b76e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192963016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2192963016
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.749759327
Short name T311
Test name
Test status
Simulation time 5465247608 ps
CPU time 81.38 seconds
Started Apr 02 02:09:19 PM PDT 24
Finished Apr 02 02:10:41 PM PDT 24
Peak memory 254700 kb
Host smart-3d6388ee-90c1-41a4-9ddc-73d38693fdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749759327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.749759327
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4151973769
Short name T699
Test name
Test status
Simulation time 3007542992 ps
CPU time 22.51 seconds
Started Apr 02 02:09:18 PM PDT 24
Finished Apr 02 02:09:42 PM PDT 24
Peak memory 218868 kb
Host smart-806e8f46-bf50-4367-9abd-9e969f4d2795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151973769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4151973769
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4223043814
Short name T68
Test name
Test status
Simulation time 5566564129 ps
CPU time 7.08 seconds
Started Apr 02 02:09:17 PM PDT 24
Finished Apr 02 02:09:26 PM PDT 24
Peak memory 223268 kb
Host smart-5757a140-25fa-42cc-acea-024facfabb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223043814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4223043814
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4096068510
Short name T176
Test name
Test status
Simulation time 1146862690 ps
CPU time 2.79 seconds
Started Apr 02 02:09:17 PM PDT 24
Finished Apr 02 02:09:22 PM PDT 24
Peak memory 220344 kb
Host smart-1f21138c-234a-4fad-a1a9-968ef9ecdbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096068510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4096068510
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1912124234
Short name T571
Test name
Test status
Simulation time 283878507 ps
CPU time 3.32 seconds
Started Apr 02 02:09:21 PM PDT 24
Finished Apr 02 02:09:24 PM PDT 24
Peak memory 219912 kb
Host smart-1312b722-1513-4992-9f36-b63722fcd880
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1912124234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1912124234
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2458626137
Short name T673
Test name
Test status
Simulation time 74859264 ps
CPU time 0.94 seconds
Started Apr 02 02:09:20 PM PDT 24
Finished Apr 02 02:09:22 PM PDT 24
Peak memory 206496 kb
Host smart-19252adf-f86b-4e00-9b79-4f23024b2116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458626137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2458626137
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3665349411
Short name T386
Test name
Test status
Simulation time 1653208774 ps
CPU time 19.16 seconds
Started Apr 02 02:09:15 PM PDT 24
Finished Apr 02 02:09:37 PM PDT 24
Peak memory 216420 kb
Host smart-7780141c-80ca-43b7-bbdb-e155b617a9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665349411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3665349411
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.292377508
Short name T528
Test name
Test status
Simulation time 986636747 ps
CPU time 4.77 seconds
Started Apr 02 02:09:13 PM PDT 24
Finished Apr 02 02:09:23 PM PDT 24
Peak memory 216408 kb
Host smart-5075c09e-b8c3-4031-8471-1b1283b7c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292377508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.292377508
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2755051642
Short name T396
Test name
Test status
Simulation time 785012784 ps
CPU time 2.07 seconds
Started Apr 02 02:09:17 PM PDT 24
Finished Apr 02 02:09:21 PM PDT 24
Peak memory 216736 kb
Host smart-35a19472-446d-49c1-af97-01e9ecb31940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755051642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2755051642
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2085751383
Short name T630
Test name
Test status
Simulation time 61581700 ps
CPU time 0.89 seconds
Started Apr 02 02:09:18 PM PDT 24
Finished Apr 02 02:09:20 PM PDT 24
Peak memory 206752 kb
Host smart-128d2abc-8db9-4d21-865b-47bad2738401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085751383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2085751383
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1226953956
Short name T721
Test name
Test status
Simulation time 24704320 ps
CPU time 0.7 seconds
Started Apr 02 02:09:32 PM PDT 24
Finished Apr 02 02:09:34 PM PDT 24
Peak memory 205672 kb
Host smart-b1641b26-73fc-42e9-8a6a-ddc3f19d1db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226953956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1226953956
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3139921484
Short name T678
Test name
Test status
Simulation time 413268258 ps
CPU time 4.44 seconds
Started Apr 02 02:09:32 PM PDT 24
Finished Apr 02 02:09:37 PM PDT 24
Peak memory 218480 kb
Host smart-2a56af53-6b10-4443-b530-1207d269c255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139921484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3139921484
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3691865035
Short name T727
Test name
Test status
Simulation time 163465698 ps
CPU time 0.73 seconds
Started Apr 02 02:09:27 PM PDT 24
Finished Apr 02 02:09:28 PM PDT 24
Peak memory 206388 kb
Host smart-20eb04c9-5726-4ab2-b389-fb31410ddd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691865035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3691865035
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1297637592
Short name T262
Test name
Test status
Simulation time 1586056330 ps
CPU time 6.71 seconds
Started Apr 02 02:09:28 PM PDT 24
Finished Apr 02 02:09:36 PM PDT 24
Peak memory 216848 kb
Host smart-30ca3026-1441-4ad4-9408-20c52a97a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297637592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1297637592
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.501122187
Short name T58
Test name
Test status
Simulation time 2687304605 ps
CPU time 5.52 seconds
Started Apr 02 02:09:26 PM PDT 24
Finished Apr 02 02:09:31 PM PDT 24
Peak memory 232320 kb
Host smart-ba6617e4-e759-47b4-829e-0e1a1e5f7768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501122187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.501122187
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1413725230
Short name T593
Test name
Test status
Simulation time 1231726738 ps
CPU time 3.86 seconds
Started Apr 02 02:09:28 PM PDT 24
Finished Apr 02 02:09:31 PM PDT 24
Peak memory 220160 kb
Host smart-cf52eb32-e0a6-40a0-9e61-4785a1483bde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1413725230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1413725230
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1450649238
Short name T378
Test name
Test status
Simulation time 9635390066 ps
CPU time 50.67 seconds
Started Apr 02 02:09:25 PM PDT 24
Finished Apr 02 02:10:16 PM PDT 24
Peak memory 216472 kb
Host smart-64228112-be1f-43dc-b29d-96d7cce63aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450649238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1450649238
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3304818063
Short name T704
Test name
Test status
Simulation time 11892581077 ps
CPU time 13.54 seconds
Started Apr 02 02:09:24 PM PDT 24
Finished Apr 02 02:09:38 PM PDT 24
Peak memory 216356 kb
Host smart-47c69cae-2457-44c4-9ccc-55b6bda94c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304818063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3304818063
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1380656792
Short name T744
Test name
Test status
Simulation time 205650909 ps
CPU time 1.51 seconds
Started Apr 02 02:09:26 PM PDT 24
Finished Apr 02 02:09:27 PM PDT 24
Peak memory 216472 kb
Host smart-11c8a6e9-0bc0-4918-af04-3c5ccf5dd567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380656792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1380656792
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1066152190
Short name T700
Test name
Test status
Simulation time 37247515 ps
CPU time 0.68 seconds
Started Apr 02 02:09:25 PM PDT 24
Finished Apr 02 02:09:25 PM PDT 24
Peak memory 205736 kb
Host smart-0807be74-b641-49f9-afe5-c57bc01fde7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066152190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1066152190
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.369722383
Short name T522
Test name
Test status
Simulation time 17312732 ps
CPU time 0.71 seconds
Started Apr 02 02:03:55 PM PDT 24
Finished Apr 02 02:03:57 PM PDT 24
Peak memory 205700 kb
Host smart-1d14675e-601f-4f8c-bcb6-fb03a4c6f673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369722383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.369722383
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2431340475
Short name T589
Test name
Test status
Simulation time 38198799 ps
CPU time 0.77 seconds
Started Apr 02 02:03:44 PM PDT 24
Finished Apr 02 02:03:44 PM PDT 24
Peak memory 206448 kb
Host smart-a65e8cf2-9de2-468b-89ed-c44cea994f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431340475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2431340475
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2093036549
Short name T328
Test name
Test status
Simulation time 1328460918 ps
CPU time 4.77 seconds
Started Apr 02 02:03:47 PM PDT 24
Finished Apr 02 02:03:52 PM PDT 24
Peak memory 221560 kb
Host smart-585b729a-8b29-45d5-84e2-c72bb006870c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093036549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2093036549
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2321579278
Short name T717
Test name
Test status
Simulation time 119375036 ps
CPU time 1.12 seconds
Started Apr 02 02:03:46 PM PDT 24
Finished Apr 02 02:03:48 PM PDT 24
Peak memory 218052 kb
Host smart-54b14466-0f1b-460d-9ab0-454778176b53
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321579278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2321579278
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1430760827
Short name T285
Test name
Test status
Simulation time 2509797015 ps
CPU time 9.73 seconds
Started Apr 02 02:03:47 PM PDT 24
Finished Apr 02 02:03:57 PM PDT 24
Peak memory 236104 kb
Host smart-0df67f35-fce1-43c8-919a-8fdb6806391a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430760827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1430760827
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1190644552
Short name T94
Test name
Test status
Simulation time 2670231133 ps
CPU time 6.14 seconds
Started Apr 02 02:03:49 PM PDT 24
Finished Apr 02 02:03:55 PM PDT 24
Peak memory 218584 kb
Host smart-93cfa31b-b1af-4d0a-9d5f-d8a66bf19580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190644552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1190644552
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.406296632
Short name T662
Test name
Test status
Simulation time 17655214 ps
CPU time 0.76 seconds
Started Apr 02 02:03:48 PM PDT 24
Finished Apr 02 02:03:49 PM PDT 24
Peak memory 216284 kb
Host smart-04f72594-c843-44b7-ae47-da43335f309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406296632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.406296632
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2562723723
Short name T604
Test name
Test status
Simulation time 1528654469 ps
CPU time 16.84 seconds
Started Apr 02 02:03:50 PM PDT 24
Finished Apr 02 02:04:08 PM PDT 24
Peak memory 221752 kb
Host smart-39f264c4-321d-4b39-b0a2-d62ca5d1b80d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2562723723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2562723723
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1808051127
Short name T50
Test name
Test status
Simulation time 115241258 ps
CPU time 1.21 seconds
Started Apr 02 02:03:55 PM PDT 24
Finished Apr 02 02:03:57 PM PDT 24
Peak memory 236992 kb
Host smart-de3750d6-2a8d-4235-a819-4e0700458fd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808051127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1808051127
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1352299338
Short name T402
Test name
Test status
Simulation time 97376907681 ps
CPU time 48.95 seconds
Started Apr 02 02:03:49 PM PDT 24
Finished Apr 02 02:04:40 PM PDT 24
Peak memory 221500 kb
Host smart-2b281ee3-c866-44fc-8048-7ed42ce55d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352299338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1352299338
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3792924920
Short name T476
Test name
Test status
Simulation time 4676945312 ps
CPU time 9.4 seconds
Started Apr 02 02:03:49 PM PDT 24
Finished Apr 02 02:04:00 PM PDT 24
Peak memory 216368 kb
Host smart-e819582e-04ac-4828-a111-42b46373ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792924920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3792924920
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2669297421
Short name T557
Test name
Test status
Simulation time 366279279 ps
CPU time 2.39 seconds
Started Apr 02 02:03:46 PM PDT 24
Finished Apr 02 02:03:49 PM PDT 24
Peak memory 216444 kb
Host smart-10fd26c4-b420-42e7-a4da-67453ff89fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669297421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2669297421
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3389438279
Short name T615
Test name
Test status
Simulation time 26833111 ps
CPU time 0.7 seconds
Started Apr 02 02:03:47 PM PDT 24
Finished Apr 02 02:03:48 PM PDT 24
Peak memory 205728 kb
Host smart-44e8a15b-6523-47d1-9097-001db01b1709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389438279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3389438279
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3092714833
Short name T654
Test name
Test status
Simulation time 14389712 ps
CPU time 0.68 seconds
Started Apr 02 02:09:47 PM PDT 24
Finished Apr 02 02:09:48 PM PDT 24
Peak memory 205352 kb
Host smart-777cefb3-a58f-4018-9f28-6e8c73c34d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092714833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3092714833
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2804782266
Short name T19
Test name
Test status
Simulation time 20257473 ps
CPU time 0.81 seconds
Started Apr 02 02:09:32 PM PDT 24
Finished Apr 02 02:09:34 PM PDT 24
Peak memory 206480 kb
Host smart-c110961f-48e4-496c-9dc0-1465582a4f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804782266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2804782266
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4233023418
Short name T293
Test name
Test status
Simulation time 9093359733 ps
CPU time 43.11 seconds
Started Apr 02 02:09:48 PM PDT 24
Finished Apr 02 02:10:32 PM PDT 24
Peak memory 241080 kb
Host smart-2f6ccf63-1d3b-4041-8e71-9319c8186aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233023418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4233023418
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3846144232
Short name T478
Test name
Test status
Simulation time 353183711 ps
CPU time 5.01 seconds
Started Apr 02 02:09:38 PM PDT 24
Finished Apr 02 02:09:44 PM PDT 24
Peak memory 218520 kb
Host smart-b1544015-990d-4e4a-aa3b-1e4f37c0ca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846144232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3846144232
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2177035373
Short name T707
Test name
Test status
Simulation time 805332534 ps
CPU time 10.12 seconds
Started Apr 02 02:09:44 PM PDT 24
Finished Apr 02 02:09:55 PM PDT 24
Peak memory 221884 kb
Host smart-5e3d4e85-992a-4972-a8b4-f62322e048cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2177035373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2177035373
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2708308793
Short name T610
Test name
Test status
Simulation time 30385312161 ps
CPU time 13.45 seconds
Started Apr 02 02:09:37 PM PDT 24
Finished Apr 02 02:09:50 PM PDT 24
Peak memory 216444 kb
Host smart-1d50927d-4eab-4784-82eb-2c63543fc6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708308793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2708308793
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3559492564
Short name T712
Test name
Test status
Simulation time 23442416732 ps
CPU time 20.61 seconds
Started Apr 02 02:09:32 PM PDT 24
Finished Apr 02 02:09:52 PM PDT 24
Peak memory 216444 kb
Host smart-822091e3-b402-4391-bf5c-786b42631d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559492564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3559492564
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4085800888
Short name T550
Test name
Test status
Simulation time 89466290 ps
CPU time 1.57 seconds
Started Apr 02 02:09:36 PM PDT 24
Finished Apr 02 02:09:38 PM PDT 24
Peak memory 216392 kb
Host smart-438207c7-6860-426d-ac1d-dcd84a1d9739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085800888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4085800888
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.556591862
Short name T549
Test name
Test status
Simulation time 11805963 ps
CPU time 0.69 seconds
Started Apr 02 02:09:35 PM PDT 24
Finished Apr 02 02:09:36 PM PDT 24
Peak memory 205708 kb
Host smart-9b2e8be4-e77e-4520-8a64-f5658d8a2732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556591862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.556591862
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2572692204
Short name T674
Test name
Test status
Simulation time 21660190 ps
CPU time 0.7 seconds
Started Apr 02 02:09:54 PM PDT 24
Finished Apr 02 02:09:57 PM PDT 24
Peak memory 204776 kb
Host smart-79066ea4-c9c6-410e-95e6-6e28f554c30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572692204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2572692204
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1966447445
Short name T451
Test name
Test status
Simulation time 1320147815 ps
CPU time 7.53 seconds
Started Apr 02 02:09:55 PM PDT 24
Finished Apr 02 02:10:04 PM PDT 24
Peak memory 221616 kb
Host smart-0245357b-b2cf-470e-9fed-966478879628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966447445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1966447445
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.297232991
Short name T620
Test name
Test status
Simulation time 233687546 ps
CPU time 0.75 seconds
Started Apr 02 02:09:47 PM PDT 24
Finished Apr 02 02:09:48 PM PDT 24
Peak memory 206496 kb
Host smart-ea1c4c16-1938-41ce-8f6f-bb756c28456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297232991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.297232991
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.649245392
Short name T702
Test name
Test status
Simulation time 30481130795 ps
CPU time 89.27 seconds
Started Apr 02 02:09:56 PM PDT 24
Finished Apr 02 02:11:27 PM PDT 24
Peak memory 240272 kb
Host smart-d3305be8-597d-4649-bc44-4c911368a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649245392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.649245392
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.820535126
Short name T356
Test name
Test status
Simulation time 1353828375 ps
CPU time 17.13 seconds
Started Apr 02 02:09:53 PM PDT 24
Finished Apr 02 02:10:11 PM PDT 24
Peak memory 224296 kb
Host smart-d3dbdaae-49e0-4ec4-bc14-d11cba2aaeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820535126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.820535126
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4120300285
Short name T653
Test name
Test status
Simulation time 1677721775 ps
CPU time 7.07 seconds
Started Apr 02 02:09:54 PM PDT 24
Finished Apr 02 02:10:03 PM PDT 24
Peak memory 220956 kb
Host smart-86b4a1da-94e9-4719-a486-50ace366a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120300285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4120300285
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1651467347
Short name T275
Test name
Test status
Simulation time 103946440 ps
CPU time 2.87 seconds
Started Apr 02 02:09:53 PM PDT 24
Finished Apr 02 02:09:56 PM PDT 24
Peak memory 222172 kb
Host smart-040cccdf-ae89-4bf5-8cab-1494ed9f72f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651467347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1651467347
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.24695527
Short name T494
Test name
Test status
Simulation time 92750375 ps
CPU time 4.04 seconds
Started Apr 02 02:09:54 PM PDT 24
Finished Apr 02 02:10:00 PM PDT 24
Peak memory 223032 kb
Host smart-203bd840-f4a8-4ab9-89ef-72edb52424b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=24695527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.24695527
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1912345166
Short name T362
Test name
Test status
Simulation time 80583471 ps
CPU time 0.97 seconds
Started Apr 02 02:09:54 PM PDT 24
Finished Apr 02 02:09:57 PM PDT 24
Peak memory 206804 kb
Host smart-b18fe97b-2580-478c-aaf6-e7c117667f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912345166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1912345166
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1948810841
Short name T385
Test name
Test status
Simulation time 98621331827 ps
CPU time 48.66 seconds
Started Apr 02 02:09:46 PM PDT 24
Finished Apr 02 02:10:37 PM PDT 24
Peak memory 216432 kb
Host smart-0025ac63-350f-4032-9fe2-b2c99ceb3062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948810841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1948810841
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2065428819
Short name T649
Test name
Test status
Simulation time 2746870307 ps
CPU time 7.13 seconds
Started Apr 02 02:09:45 PM PDT 24
Finished Apr 02 02:09:53 PM PDT 24
Peak memory 216380 kb
Host smart-d9e1873b-5e22-4d31-b1c4-89ccda6b455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065428819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2065428819
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.480029411
Short name T563
Test name
Test status
Simulation time 187502535 ps
CPU time 7.31 seconds
Started Apr 02 02:09:47 PM PDT 24
Finished Apr 02 02:09:55 PM PDT 24
Peak memory 216352 kb
Host smart-7a73f78f-5c8a-4c6c-8bd5-008c49490e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480029411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.480029411
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1296187308
Short name T20
Test name
Test status
Simulation time 113113447 ps
CPU time 0.7 seconds
Started Apr 02 02:09:46 PM PDT 24
Finished Apr 02 02:09:48 PM PDT 24
Peak memory 205692 kb
Host smart-b2833a93-6ee0-4495-9ba2-8c0582fc938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296187308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1296187308
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3351333091
Short name T180
Test name
Test status
Simulation time 369279195 ps
CPU time 2.97 seconds
Started Apr 02 02:09:53 PM PDT 24
Finished Apr 02 02:09:57 PM PDT 24
Peak memory 218908 kb
Host smart-8a6bab2f-d48b-4e73-83e4-b517892a26ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351333091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3351333091
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1707575134
Short name T414
Test name
Test status
Simulation time 12174741 ps
CPU time 0.69 seconds
Started Apr 02 02:10:04 PM PDT 24
Finished Apr 02 02:10:05 PM PDT 24
Peak memory 205360 kb
Host smart-fa6c969f-dd01-49ee-a553-8d45e46ad551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707575134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1707575134
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2671869349
Short name T420
Test name
Test status
Simulation time 20393010 ps
CPU time 0.76 seconds
Started Apr 02 02:09:58 PM PDT 24
Finished Apr 02 02:09:59 PM PDT 24
Peak memory 206540 kb
Host smart-f2563159-5351-4678-8138-8717865841d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671869349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2671869349
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3270717535
Short name T748
Test name
Test status
Simulation time 9585854921 ps
CPU time 88.15 seconds
Started Apr 02 02:10:01 PM PDT 24
Finished Apr 02 02:11:29 PM PDT 24
Peak memory 252036 kb
Host smart-6c83a655-90af-4438-9081-0d0f3506c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270717535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3270717535
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3234227630
Short name T317
Test name
Test status
Simulation time 440331800 ps
CPU time 3.17 seconds
Started Apr 02 02:10:03 PM PDT 24
Finished Apr 02 02:10:06 PM PDT 24
Peak memory 220376 kb
Host smart-41770acc-ceda-47f6-9f30-b759570f916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234227630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3234227630
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3942708392
Short name T110
Test name
Test status
Simulation time 86851450 ps
CPU time 3.37 seconds
Started Apr 02 02:10:00 PM PDT 24
Finished Apr 02 02:10:04 PM PDT 24
Peak memory 219784 kb
Host smart-98109b62-fb86-4e19-805d-5940e89fdf38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3942708392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3942708392
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3078585767
Short name T448
Test name
Test status
Simulation time 773277019 ps
CPU time 2.09 seconds
Started Apr 02 02:09:57 PM PDT 24
Finished Apr 02 02:10:00 PM PDT 24
Peak memory 216100 kb
Host smart-d1302479-be5c-4dee-be9a-f0b254d636da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078585767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3078585767
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2049040580
Short name T746
Test name
Test status
Simulation time 54342622 ps
CPU time 1.23 seconds
Started Apr 02 02:09:57 PM PDT 24
Finished Apr 02 02:09:59 PM PDT 24
Peak memory 216244 kb
Host smart-285c323e-9db0-4c75-b3f0-a63e50357226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049040580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2049040580
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1417897651
Short name T169
Test name
Test status
Simulation time 205484251 ps
CPU time 0.92 seconds
Started Apr 02 02:09:57 PM PDT 24
Finished Apr 02 02:09:59 PM PDT 24
Peak memory 206760 kb
Host smart-f3f94cbf-3d86-464a-9bd0-0f38a3eb3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417897651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1417897651
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1362934161
Short name T738
Test name
Test status
Simulation time 23525867 ps
CPU time 0.71 seconds
Started Apr 02 02:10:19 PM PDT 24
Finished Apr 02 02:10:20 PM PDT 24
Peak memory 205376 kb
Host smart-04c0efc3-5029-4bc3-8679-5e5a88de326d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362934161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1362934161
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.447277864
Short name T407
Test name
Test status
Simulation time 48777474 ps
CPU time 0.74 seconds
Started Apr 02 02:10:03 PM PDT 24
Finished Apr 02 02:10:04 PM PDT 24
Peak memory 206484 kb
Host smart-062f32f3-363c-4161-96c0-b924141e3c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447277864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.447277864
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3075605771
Short name T360
Test name
Test status
Simulation time 2092319927 ps
CPU time 27.24 seconds
Started Apr 02 02:10:11 PM PDT 24
Finished Apr 02 02:10:38 PM PDT 24
Peak memory 234892 kb
Host smart-697a8788-ba54-4da4-abf3-6541a243058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075605771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3075605771
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1069777841
Short name T237
Test name
Test status
Simulation time 193768935 ps
CPU time 4.71 seconds
Started Apr 02 02:10:09 PM PDT 24
Finished Apr 02 02:10:14 PM PDT 24
Peak memory 235372 kb
Host smart-e7b8d3ab-4351-4f44-800d-331df41d78a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069777841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1069777841
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3894949596
Short name T280
Test name
Test status
Simulation time 63359265 ps
CPU time 2.56 seconds
Started Apr 02 02:10:10 PM PDT 24
Finished Apr 02 02:10:13 PM PDT 24
Peak memory 222984 kb
Host smart-e3f2bc96-b5d6-48ff-8217-129e0e30bb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894949596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3894949596
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3589902948
Short name T655
Test name
Test status
Simulation time 2246903668 ps
CPU time 7.04 seconds
Started Apr 02 02:10:11 PM PDT 24
Finished Apr 02 02:10:19 PM PDT 24
Peak memory 220096 kb
Host smart-bf4a4672-7d9d-4316-8795-8b6726bb1795
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589902948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3589902948
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1246587025
Short name T103
Test name
Test status
Simulation time 1271623222 ps
CPU time 12.39 seconds
Started Apr 02 02:10:04 PM PDT 24
Finished Apr 02 02:10:17 PM PDT 24
Peak memory 216412 kb
Host smart-a32b900c-ba96-4306-b078-482f4a270e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246587025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1246587025
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2011677726
Short name T463
Test name
Test status
Simulation time 1392716071 ps
CPU time 7.4 seconds
Started Apr 02 02:10:05 PM PDT 24
Finished Apr 02 02:10:13 PM PDT 24
Peak memory 216352 kb
Host smart-88481b7a-221d-43b8-8b51-265b51cd1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011677726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2011677726
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1684968751
Short name T520
Test name
Test status
Simulation time 60688944 ps
CPU time 1.53 seconds
Started Apr 02 02:10:08 PM PDT 24
Finished Apr 02 02:10:10 PM PDT 24
Peak memory 216384 kb
Host smart-cee88cff-e7f9-4279-b070-560925a723ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684968751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1684968751
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2273293091
Short name T583
Test name
Test status
Simulation time 61798730 ps
CPU time 0.7 seconds
Started Apr 02 02:10:07 PM PDT 24
Finished Apr 02 02:10:08 PM PDT 24
Peak memory 205604 kb
Host smart-034940a3-91f4-4a35-a3e9-42b681b9e232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273293091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2273293091
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4136723746
Short name T645
Test name
Test status
Simulation time 21817915 ps
CPU time 0.7 seconds
Started Apr 02 02:10:33 PM PDT 24
Finished Apr 02 02:10:34 PM PDT 24
Peak memory 205716 kb
Host smart-62bdd404-080a-4722-9769-85683485bfb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136723746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4136723746
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2628571675
Short name T217
Test name
Test status
Simulation time 5840365831 ps
CPU time 14.28 seconds
Started Apr 02 02:10:26 PM PDT 24
Finished Apr 02 02:10:40 PM PDT 24
Peak memory 223000 kb
Host smart-c657011a-1f19-4db9-90ca-b7abd42ce31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628571675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2628571675
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2363351770
Short name T575
Test name
Test status
Simulation time 13716249 ps
CPU time 0.74 seconds
Started Apr 02 02:10:24 PM PDT 24
Finished Apr 02 02:10:25 PM PDT 24
Peak memory 206804 kb
Host smart-c9a16748-92d7-41f1-a1b9-d100df9f9ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363351770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2363351770
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.11174372
Short name T359
Test name
Test status
Simulation time 4258281833 ps
CPU time 23.47 seconds
Started Apr 02 02:10:26 PM PDT 24
Finished Apr 02 02:10:49 PM PDT 24
Peak memory 253512 kb
Host smart-7ad20e69-db0d-47ce-9ea5-eb3872a1730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11174372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.11174372
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.818143447
Short name T96
Test name
Test status
Simulation time 1380596899 ps
CPU time 6.63 seconds
Started Apr 02 02:10:27 PM PDT 24
Finished Apr 02 02:10:33 PM PDT 24
Peak memory 224496 kb
Host smart-2444930e-3a83-45ba-988f-00bb4c20eb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818143447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.818143447
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2159348039
Short name T120
Test name
Test status
Simulation time 6438258218 ps
CPU time 16.49 seconds
Started Apr 02 02:10:28 PM PDT 24
Finished Apr 02 02:10:45 PM PDT 24
Peak memory 232328 kb
Host smart-092b18e8-7a90-45c3-b3d4-ac49c93843ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159348039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2159348039
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4039504115
Short name T271
Test name
Test status
Simulation time 13674769922 ps
CPU time 9.81 seconds
Started Apr 02 02:10:23 PM PDT 24
Finished Apr 02 02:10:33 PM PDT 24
Peak memory 218888 kb
Host smart-958de5d9-1093-4952-b0c5-d8c6131bd988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039504115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4039504115
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.589518260
Short name T548
Test name
Test status
Simulation time 3194120651 ps
CPU time 6.91 seconds
Started Apr 02 02:10:29 PM PDT 24
Finished Apr 02 02:10:36 PM PDT 24
Peak memory 219300 kb
Host smart-d413b432-8e41-4dcf-8458-9abcc6a62c8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=589518260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.589518260
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1457174924
Short name T607
Test name
Test status
Simulation time 8308061948 ps
CPU time 20.4 seconds
Started Apr 02 02:10:26 PM PDT 24
Finished Apr 02 02:10:47 PM PDT 24
Peak memory 216456 kb
Host smart-2f350ba8-7fb1-4cd2-84d5-855cdd7982d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457174924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1457174924
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.800771233
Short name T6
Test name
Test status
Simulation time 1353833938 ps
CPU time 4.28 seconds
Started Apr 02 02:10:39 PM PDT 24
Finished Apr 02 02:10:43 PM PDT 24
Peak memory 216280 kb
Host smart-8565b92f-9209-4cca-8c47-56e96663114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800771233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.800771233
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.59672923
Short name T672
Test name
Test status
Simulation time 211064609 ps
CPU time 9.15 seconds
Started Apr 02 02:10:22 PM PDT 24
Finished Apr 02 02:10:32 PM PDT 24
Peak memory 216412 kb
Host smart-7e989aaa-6a28-48e6-9219-3c72b81c4ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59672923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.59672923
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2758341687
Short name T584
Test name
Test status
Simulation time 120698717 ps
CPU time 1.03 seconds
Started Apr 02 02:10:23 PM PDT 24
Finished Apr 02 02:10:24 PM PDT 24
Peak memory 206712 kb
Host smart-e1b9cf97-a967-49df-adf7-b8ff0b6bf073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758341687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2758341687
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.322025415
Short name T500
Test name
Test status
Simulation time 31644397 ps
CPU time 0.72 seconds
Started Apr 02 02:10:38 PM PDT 24
Finished Apr 02 02:10:39 PM PDT 24
Peak memory 204800 kb
Host smart-63f57f5a-86de-4e8d-b3e7-c28409d48d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322025415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.322025415
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2939227188
Short name T517
Test name
Test status
Simulation time 30126967 ps
CPU time 0.75 seconds
Started Apr 02 02:10:35 PM PDT 24
Finished Apr 02 02:10:36 PM PDT 24
Peak memory 206496 kb
Host smart-772291df-6e13-4b9d-9b7f-5a9bb3cccd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939227188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2939227188
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2538978944
Short name T353
Test name
Test status
Simulation time 60178025494 ps
CPU time 63.15 seconds
Started Apr 02 02:10:36 PM PDT 24
Finished Apr 02 02:11:40 PM PDT 24
Peak memory 249280 kb
Host smart-9f10089c-4ccf-432b-8259-e6f9f02c07b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538978944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2538978944
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3844409032
Short name T45
Test name
Test status
Simulation time 1527457291 ps
CPU time 5.93 seconds
Started Apr 02 02:10:30 PM PDT 24
Finished Apr 02 02:10:36 PM PDT 24
Peak memory 218492 kb
Host smart-0a4caad6-5077-4d8b-a1c9-ae57e3bd307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844409032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3844409032
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2968513598
Short name T348
Test name
Test status
Simulation time 126373606 ps
CPU time 2.85 seconds
Started Apr 02 02:10:30 PM PDT 24
Finished Apr 02 02:10:33 PM PDT 24
Peak memory 219660 kb
Host smart-7895a26d-e19c-4e8c-b6a8-e70076a3ddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968513598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2968513598
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3220108459
Short name T443
Test name
Test status
Simulation time 412345622 ps
CPU time 4.68 seconds
Started Apr 02 02:10:35 PM PDT 24
Finished Apr 02 02:10:40 PM PDT 24
Peak memory 220652 kb
Host smart-0f51b257-4cd1-4aa9-99eb-0b45516d9c96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3220108459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3220108459
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1164561967
Short name T720
Test name
Test status
Simulation time 3443456300 ps
CPU time 24.71 seconds
Started Apr 02 02:10:32 PM PDT 24
Finished Apr 02 02:10:57 PM PDT 24
Peak memory 216496 kb
Host smart-20e99042-df1f-4401-9d93-5d560be868b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164561967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1164561967
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.685312688
Short name T436
Test name
Test status
Simulation time 1308360277 ps
CPU time 4.24 seconds
Started Apr 02 02:10:30 PM PDT 24
Finished Apr 02 02:10:35 PM PDT 24
Peak memory 216252 kb
Host smart-0b36a576-c07d-4ca6-8ef0-18ec81294af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685312688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.685312688
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3714482538
Short name T461
Test name
Test status
Simulation time 353443252 ps
CPU time 1.09 seconds
Started Apr 02 02:10:32 PM PDT 24
Finished Apr 02 02:10:33 PM PDT 24
Peak memory 207968 kb
Host smart-785b2c7e-d6a2-41c1-958a-33ed29ae28c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714482538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3714482538
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1293236758
Short name T417
Test name
Test status
Simulation time 90288841 ps
CPU time 0.87 seconds
Started Apr 02 02:10:31 PM PDT 24
Finished Apr 02 02:10:32 PM PDT 24
Peak memory 205728 kb
Host smart-3258196c-60b7-4999-a405-8ec0d6b04d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293236758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1293236758
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2800669853
Short name T82
Test name
Test status
Simulation time 13572912801 ps
CPU time 9.74 seconds
Started Apr 02 02:10:29 PM PDT 24
Finished Apr 02 02:10:39 PM PDT 24
Peak memory 218928 kb
Host smart-3a50ebe9-ec2d-4eaa-9ee5-aadd60062fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800669853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2800669853
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2493988438
Short name T446
Test name
Test status
Simulation time 46347077 ps
CPU time 0.71 seconds
Started Apr 02 02:10:56 PM PDT 24
Finished Apr 02 02:10:57 PM PDT 24
Peak memory 205364 kb
Host smart-97f05154-5cdb-45c1-ae37-8b864dc84d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493988438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2493988438
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1658362760
Short name T423
Test name
Test status
Simulation time 43224924 ps
CPU time 0.76 seconds
Started Apr 02 02:10:38 PM PDT 24
Finished Apr 02 02:10:39 PM PDT 24
Peak memory 206452 kb
Host smart-435ea42d-c187-4030-b0f8-1845319ab0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658362760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1658362760
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3411304551
Short name T355
Test name
Test status
Simulation time 54355208414 ps
CPU time 175.16 seconds
Started Apr 02 02:10:46 PM PDT 24
Finished Apr 02 02:13:42 PM PDT 24
Peak memory 249296 kb
Host smart-d0d6fb13-dfbb-4e18-82c9-ffa0c1f2251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411304551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3411304551
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2722812872
Short name T200
Test name
Test status
Simulation time 164625491 ps
CPU time 5.28 seconds
Started Apr 02 02:10:48 PM PDT 24
Finished Apr 02 02:10:54 PM PDT 24
Peak memory 223840 kb
Host smart-a6e43456-ce6b-4f59-aae4-c519546b119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722812872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2722812872
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1112285608
Short name T154
Test name
Test status
Simulation time 412170136 ps
CPU time 4.18 seconds
Started Apr 02 02:10:50 PM PDT 24
Finished Apr 02 02:10:54 PM PDT 24
Peak memory 222940 kb
Host smart-dba4408e-8345-4fdb-bd2f-887ed44161e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1112285608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1112285608
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.375284158
Short name T642
Test name
Test status
Simulation time 6225694706 ps
CPU time 30.99 seconds
Started Apr 02 02:10:43 PM PDT 24
Finished Apr 02 02:11:15 PM PDT 24
Peak memory 216504 kb
Host smart-5d2c9c4b-5ea8-4375-bcba-8dd5a7f94f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375284158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.375284158
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2099119334
Short name T591
Test name
Test status
Simulation time 8817814183 ps
CPU time 17.87 seconds
Started Apr 02 02:10:39 PM PDT 24
Finished Apr 02 02:10:57 PM PDT 24
Peak memory 216432 kb
Host smart-db5fe0b0-c4eb-4e94-8d51-9deaf8236636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099119334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2099119334
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4097633289
Short name T387
Test name
Test status
Simulation time 78838162 ps
CPU time 2.7 seconds
Started Apr 02 02:10:44 PM PDT 24
Finished Apr 02 02:10:46 PM PDT 24
Peak memory 216460 kb
Host smart-51eb57ec-a8cf-428b-b6c2-835a14da30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097633289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4097633289
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.138110664
Short name T572
Test name
Test status
Simulation time 85693674 ps
CPU time 0.74 seconds
Started Apr 02 02:10:44 PM PDT 24
Finished Apr 02 02:10:44 PM PDT 24
Peak memory 205724 kb
Host smart-32fbe53a-5807-4f12-b69f-a3424ddd3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138110664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.138110664
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3197797495
Short name T723
Test name
Test status
Simulation time 40488951 ps
CPU time 0.77 seconds
Started Apr 02 02:11:03 PM PDT 24
Finished Apr 02 02:11:04 PM PDT 24
Peak memory 205300 kb
Host smart-9426132f-0daa-43ae-97cc-6e233b6ddd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197797495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3197797495
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1867991096
Short name T677
Test name
Test status
Simulation time 51126219 ps
CPU time 0.72 seconds
Started Apr 02 02:10:54 PM PDT 24
Finished Apr 02 02:10:55 PM PDT 24
Peak memory 206532 kb
Host smart-73e47e6f-ac0b-4820-a839-2b138f01b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867991096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1867991096
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2278105338
Short name T312
Test name
Test status
Simulation time 1663055846 ps
CPU time 15.23 seconds
Started Apr 02 02:10:59 PM PDT 24
Finished Apr 02 02:11:14 PM PDT 24
Peak memory 234484 kb
Host smart-303437b4-8789-4311-be62-220212c92064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278105338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2278105338
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.893378502
Short name T92
Test name
Test status
Simulation time 737599862 ps
CPU time 17.03 seconds
Started Apr 02 02:11:00 PM PDT 24
Finished Apr 02 02:11:17 PM PDT 24
Peak memory 236504 kb
Host smart-294853d4-ba85-45a1-8a09-1e57185694eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893378502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.893378502
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.427296406
Short name T652
Test name
Test status
Simulation time 15655079727 ps
CPU time 44.75 seconds
Started Apr 02 02:10:59 PM PDT 24
Finished Apr 02 02:11:44 PM PDT 24
Peak memory 232892 kb
Host smart-f902cb33-8ea5-46d0-af2a-537c42e05604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427296406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.427296406
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3998793603
Short name T733
Test name
Test status
Simulation time 828915400 ps
CPU time 4.94 seconds
Started Apr 02 02:11:03 PM PDT 24
Finished Apr 02 02:11:08 PM PDT 24
Peak memory 222820 kb
Host smart-2a0274d3-688e-42d7-94cc-9b1bc59e5855
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3998793603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3998793603
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3998512761
Short name T380
Test name
Test status
Simulation time 3585477258 ps
CPU time 33.74 seconds
Started Apr 02 02:10:53 PM PDT 24
Finished Apr 02 02:11:27 PM PDT 24
Peak memory 216516 kb
Host smart-7514df12-8e05-4b14-966e-270c96e8c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998512761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3998512761
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4244376445
Short name T487
Test name
Test status
Simulation time 221942941 ps
CPU time 1.78 seconds
Started Apr 02 02:10:54 PM PDT 24
Finished Apr 02 02:10:56 PM PDT 24
Peak memory 216168 kb
Host smart-49042f39-2fb4-483c-bfdc-3a7deca1ceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244376445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4244376445
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1772943549
Short name T449
Test name
Test status
Simulation time 79676053 ps
CPU time 1.03 seconds
Started Apr 02 02:10:59 PM PDT 24
Finished Apr 02 02:11:00 PM PDT 24
Peak memory 207944 kb
Host smart-a317e641-a7b1-43b4-a844-69078112583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772943549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1772943549
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3459763341
Short name T710
Test name
Test status
Simulation time 189795968 ps
CPU time 0.78 seconds
Started Apr 02 02:10:54 PM PDT 24
Finished Apr 02 02:10:55 PM PDT 24
Peak memory 205644 kb
Host smart-7cb9cc6d-30ed-4bf0-9e46-dc5a8cacbb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459763341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3459763341
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2285941664
Short name T27
Test name
Test status
Simulation time 53021182 ps
CPU time 0.7 seconds
Started Apr 02 02:11:09 PM PDT 24
Finished Apr 02 02:11:09 PM PDT 24
Peak memory 204780 kb
Host smart-e590b53e-a339-4531-945c-d5db93a63980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285941664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2285941664
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2782535121
Short name T88
Test name
Test status
Simulation time 347086463 ps
CPU time 2.38 seconds
Started Apr 02 02:11:08 PM PDT 24
Finished Apr 02 02:11:11 PM PDT 24
Peak memory 216720 kb
Host smart-8618a5df-b39c-4d79-9902-8f2fcd44c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782535121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2782535121
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2571146693
Short name T562
Test name
Test status
Simulation time 30992942 ps
CPU time 0.7 seconds
Started Apr 02 02:11:05 PM PDT 24
Finished Apr 02 02:11:06 PM PDT 24
Peak memory 205460 kb
Host smart-e325f82c-c02d-41e7-ba0d-0a39a2fdef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571146693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2571146693
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2965763061
Short name T194
Test name
Test status
Simulation time 12746488896 ps
CPU time 12.08 seconds
Started Apr 02 02:11:11 PM PDT 24
Finished Apr 02 02:11:23 PM PDT 24
Peak memory 220576 kb
Host smart-93971d50-c34d-4573-a057-3c009b7f16cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965763061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2965763061
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4061849766
Short name T657
Test name
Test status
Simulation time 399405110 ps
CPU time 3.94 seconds
Started Apr 02 02:11:08 PM PDT 24
Finished Apr 02 02:11:12 PM PDT 24
Peak memory 222896 kb
Host smart-00f7fd6c-d4bb-4712-92e5-342ae767b048
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4061849766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4061849766
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3323511890
Short name T397
Test name
Test status
Simulation time 3057206717 ps
CPU time 30.7 seconds
Started Apr 02 02:11:07 PM PDT 24
Finished Apr 02 02:11:37 PM PDT 24
Peak memory 216416 kb
Host smart-7a94c8f9-c90f-4c26-b9ad-5b101bd5a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323511890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3323511890
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3865685420
Short name T418
Test name
Test status
Simulation time 974684621 ps
CPU time 4.11 seconds
Started Apr 02 02:11:05 PM PDT 24
Finished Apr 02 02:11:10 PM PDT 24
Peak memory 216336 kb
Host smart-e63ddc5b-0f73-4116-ad8e-008326dde267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865685420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3865685420
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1962784933
Short name T167
Test name
Test status
Simulation time 36264702 ps
CPU time 1.71 seconds
Started Apr 02 02:11:10 PM PDT 24
Finished Apr 02 02:11:12 PM PDT 24
Peak memory 216332 kb
Host smart-3bce858b-ff1b-478e-9230-25e68ff11c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962784933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1962784933
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1520985181
Short name T639
Test name
Test status
Simulation time 100404467 ps
CPU time 0.76 seconds
Started Apr 02 02:11:05 PM PDT 24
Finished Apr 02 02:11:06 PM PDT 24
Peak memory 205728 kb
Host smart-41f8cfa9-9165-4c3a-b496-b398b43bb07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520985181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1520985181
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.287417744
Short name T349
Test name
Test status
Simulation time 4158284530 ps
CPU time 5.01 seconds
Started Apr 02 02:11:08 PM PDT 24
Finished Apr 02 02:11:13 PM PDT 24
Peak memory 223508 kb
Host smart-dce3aa48-ae1d-41b1-b5c5-07b333afc92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287417744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.287417744
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1236520318
Short name T512
Test name
Test status
Simulation time 14013037 ps
CPU time 0.72 seconds
Started Apr 02 02:11:28 PM PDT 24
Finished Apr 02 02:11:29 PM PDT 24
Peak memory 204756 kb
Host smart-f6f42cf2-151e-491b-99a1-7e73244f46af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236520318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1236520318
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1877866322
Short name T125
Test name
Test status
Simulation time 28530927 ps
CPU time 0.74 seconds
Started Apr 02 02:11:09 PM PDT 24
Finished Apr 02 02:11:10 PM PDT 24
Peak memory 206848 kb
Host smart-75f081a5-0222-41d3-83f9-accde9db1948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877866322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1877866322
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1362491799
Short name T95
Test name
Test status
Simulation time 7096736811 ps
CPU time 9.79 seconds
Started Apr 02 02:11:18 PM PDT 24
Finished Apr 02 02:11:28 PM PDT 24
Peak memory 223056 kb
Host smart-d2ae5c50-92cd-47f7-9284-52298c2a46cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362491799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1362491799
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.686296463
Short name T203
Test name
Test status
Simulation time 91345077080 ps
CPU time 208.43 seconds
Started Apr 02 02:11:17 PM PDT 24
Finished Apr 02 02:14:46 PM PDT 24
Peak memory 249240 kb
Host smart-e49a2294-8592-41c6-a939-e8b1290df39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686296463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.686296463
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1235684974
Short name T177
Test name
Test status
Simulation time 158156498 ps
CPU time 2.08 seconds
Started Apr 02 02:11:15 PM PDT 24
Finished Apr 02 02:11:18 PM PDT 24
Peak memory 218516 kb
Host smart-96f3f5cc-d40f-4f25-8cf2-de4ebdaf0ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235684974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1235684974
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1943869144
Short name T415
Test name
Test status
Simulation time 94061146 ps
CPU time 3.74 seconds
Started Apr 02 02:11:25 PM PDT 24
Finished Apr 02 02:11:29 PM PDT 24
Peak memory 222836 kb
Host smart-eeeccb34-72f5-4bcb-94af-255af26e8568
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1943869144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1943869144
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2230309586
Short name T383
Test name
Test status
Simulation time 1527715516 ps
CPU time 2.54 seconds
Started Apr 02 02:11:14 PM PDT 24
Finished Apr 02 02:11:16 PM PDT 24
Peak memory 216316 kb
Host smart-fc585b62-c48c-474c-a76e-1980022a9270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230309586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2230309586
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2924355303
Short name T724
Test name
Test status
Simulation time 1483483716 ps
CPU time 5.36 seconds
Started Apr 02 02:11:14 PM PDT 24
Finished Apr 02 02:11:19 PM PDT 24
Peak memory 216308 kb
Host smart-af2f396c-9b20-43b7-9792-c85ef2d8946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924355303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2924355303
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3922294836
Short name T434
Test name
Test status
Simulation time 24182717 ps
CPU time 0.99 seconds
Started Apr 02 02:11:13 PM PDT 24
Finished Apr 02 02:11:14 PM PDT 24
Peak memory 207828 kb
Host smart-a046bb42-d697-4b8d-a673-9c158a761c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922294836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3922294836
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3592099521
Short name T686
Test name
Test status
Simulation time 280343608 ps
CPU time 1.1 seconds
Started Apr 02 02:11:14 PM PDT 24
Finished Apr 02 02:11:15 PM PDT 24
Peak memory 206740 kb
Host smart-15991e17-ec1f-4385-b77e-95a0ad4691b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592099521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3592099521
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3557248542
Short name T408
Test name
Test status
Simulation time 35697663 ps
CPU time 0.69 seconds
Started Apr 02 02:04:08 PM PDT 24
Finished Apr 02 02:04:10 PM PDT 24
Peak memory 205356 kb
Host smart-9737aa10-c859-483d-b051-b504fbda7409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557248542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
557248542
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2485748240
Short name T21
Test name
Test status
Simulation time 22852664 ps
CPU time 0.77 seconds
Started Apr 02 02:03:56 PM PDT 24
Finished Apr 02 02:03:57 PM PDT 24
Peak memory 206812 kb
Host smart-17b91446-fe53-4e22-b6f6-9227b61dfa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485748240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2485748240
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2750145643
Short name T302
Test name
Test status
Simulation time 14855185943 ps
CPU time 63.36 seconds
Started Apr 02 02:04:05 PM PDT 24
Finished Apr 02 02:05:10 PM PDT 24
Peak memory 252736 kb
Host smart-17ecd638-7050-41ff-9911-8f43cc232ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750145643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2750145643
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.127325306
Short name T555
Test name
Test status
Simulation time 15012579273 ps
CPU time 33.46 seconds
Started Apr 02 02:04:01 PM PDT 24
Finished Apr 02 02:04:38 PM PDT 24
Peak memory 224480 kb
Host smart-174ee0e3-ce94-4227-be1a-8f8355c5382b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127325306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.127325306
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2633951723
Short name T329
Test name
Test status
Simulation time 3317407981 ps
CPU time 36.45 seconds
Started Apr 02 02:04:01 PM PDT 24
Finished Apr 02 02:04:41 PM PDT 24
Peak memory 219680 kb
Host smart-8513bbbe-5861-48a7-a8bb-da603434d976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633951723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2633951723
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3492140708
Short name T691
Test name
Test status
Simulation time 17208412 ps
CPU time 0.95 seconds
Started Apr 02 02:03:58 PM PDT 24
Finished Apr 02 02:03:59 PM PDT 24
Peak memory 218068 kb
Host smart-9bd64eaf-e68b-4604-bee6-3fc94c7a2d3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492140708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3492140708
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.663467518
Short name T336
Test name
Test status
Simulation time 263043828 ps
CPU time 2.69 seconds
Started Apr 02 02:04:00 PM PDT 24
Finished Apr 02 02:04:03 PM PDT 24
Peak memory 222688 kb
Host smart-1717abcf-3c3e-4edd-b687-3daf1e69767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663467518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
663467518
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1591053366
Short name T456
Test name
Test status
Simulation time 17606481 ps
CPU time 0.74 seconds
Started Apr 02 02:03:59 PM PDT 24
Finished Apr 02 02:04:00 PM PDT 24
Peak memory 216276 kb
Host smart-65e3f51f-0e66-4dd7-88d5-8296df7e94d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591053366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1591053366
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1963473637
Short name T111
Test name
Test status
Simulation time 5354719564 ps
CPU time 6.07 seconds
Started Apr 02 02:04:05 PM PDT 24
Finished Apr 02 02:04:12 PM PDT 24
Peak memory 220184 kb
Host smart-cd2f1857-f379-4242-a028-b6f1dd56f72d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963473637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1963473637
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2469909928
Short name T384
Test name
Test status
Simulation time 68675503571 ps
CPU time 52.07 seconds
Started Apr 02 02:04:01 PM PDT 24
Finished Apr 02 02:04:57 PM PDT 24
Peak memory 216488 kb
Host smart-ab51235c-c157-4d02-867a-0697b4e03e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469909928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2469909928
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2661241979
Short name T426
Test name
Test status
Simulation time 5161331983 ps
CPU time 5.64 seconds
Started Apr 02 02:03:58 PM PDT 24
Finished Apr 02 02:04:04 PM PDT 24
Peak memory 216396 kb
Host smart-ae5dd430-8bbc-4b4b-8689-46c21c1369fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661241979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2661241979
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1051014100
Short name T393
Test name
Test status
Simulation time 1671210284 ps
CPU time 8.46 seconds
Started Apr 02 02:04:01 PM PDT 24
Finished Apr 02 02:04:12 PM PDT 24
Peak memory 216340 kb
Host smart-01516e29-fddf-4534-aab7-bdab9521bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051014100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1051014100
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3746295297
Short name T633
Test name
Test status
Simulation time 628158064 ps
CPU time 1.16 seconds
Started Apr 02 02:04:01 PM PDT 24
Finished Apr 02 02:04:06 PM PDT 24
Peak memory 206740 kb
Host smart-5d605fb6-b7db-45cd-beff-e527115bfe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746295297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3746295297
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3077522202
Short name T719
Test name
Test status
Simulation time 14997283 ps
CPU time 0.7 seconds
Started Apr 02 02:04:19 PM PDT 24
Finished Apr 02 02:04:20 PM PDT 24
Peak memory 205344 kb
Host smart-39cd4332-1d8b-4d23-a64a-534f800f5a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077522202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
077522202
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2731646028
Short name T441
Test name
Test status
Simulation time 47489853 ps
CPU time 0.73 seconds
Started Apr 02 02:04:08 PM PDT 24
Finished Apr 02 02:04:10 PM PDT 24
Peak memory 206468 kb
Host smart-7a2fd8cb-ea67-44dd-b41b-6deab58fe0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731646028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2731646028
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.518506477
Short name T306
Test name
Test status
Simulation time 13863818924 ps
CPU time 69.07 seconds
Started Apr 02 02:04:15 PM PDT 24
Finished Apr 02 02:05:25 PM PDT 24
Peak memory 232892 kb
Host smart-57892ee1-3f99-4dc4-b7b1-db77426c00f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518506477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.518506477
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1776955743
Short name T565
Test name
Test status
Simulation time 46690475 ps
CPU time 1 seconds
Started Apr 02 02:04:07 PM PDT 24
Finished Apr 02 02:04:10 PM PDT 24
Peak memory 216760 kb
Host smart-b3d505cf-be31-46bf-82ab-25891ed336f0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776955743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1776955743
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2280854993
Short name T342
Test name
Test status
Simulation time 25699741019 ps
CPU time 19.35 seconds
Started Apr 02 02:04:13 PM PDT 24
Finished Apr 02 02:04:33 PM PDT 24
Peak memory 224572 kb
Host smart-82d2abb0-28b4-46c8-bdd5-ad46e72425ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280854993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2280854993
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.643190886
Short name T79
Test name
Test status
Simulation time 29540580317 ps
CPU time 17.01 seconds
Started Apr 02 02:04:12 PM PDT 24
Finished Apr 02 02:04:31 PM PDT 24
Peak memory 232892 kb
Host smart-a8da9f28-0941-4a6b-82bc-bfacde8095af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643190886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.643190886
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.2570034519
Short name T651
Test name
Test status
Simulation time 21796114 ps
CPU time 0.73 seconds
Started Apr 02 02:04:09 PM PDT 24
Finished Apr 02 02:04:11 PM PDT 24
Peak memory 216288 kb
Host smart-a45da090-eb78-42e6-aea8-e35d09d34a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570034519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.2570034519
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1688424770
Short name T725
Test name
Test status
Simulation time 420013268 ps
CPU time 4.12 seconds
Started Apr 02 02:04:16 PM PDT 24
Finished Apr 02 02:04:22 PM PDT 24
Peak memory 222284 kb
Host smart-220f7db9-b17a-4418-80cd-129d737d0518
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1688424770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1688424770
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3910859805
Short name T161
Test name
Test status
Simulation time 132666915 ps
CPU time 1.07 seconds
Started Apr 02 02:04:20 PM PDT 24
Finished Apr 02 02:04:22 PM PDT 24
Peak memory 207048 kb
Host smart-da8c6677-2ee8-421c-acf1-98f324a49edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910859805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3910859805
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3790175132
Short name T624
Test name
Test status
Simulation time 12798329478 ps
CPU time 22.01 seconds
Started Apr 02 02:04:07 PM PDT 24
Finished Apr 02 02:04:31 PM PDT 24
Peak memory 216480 kb
Host smart-cf450ad0-e6de-45bb-91b9-a6e061b8e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790175132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3790175132
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2535293105
Short name T628
Test name
Test status
Simulation time 42341103239 ps
CPU time 15.52 seconds
Started Apr 02 02:04:08 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 216408 kb
Host smart-05fc2ba9-6397-41e0-8b3f-69bc64663451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535293105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2535293105
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3700623631
Short name T722
Test name
Test status
Simulation time 85431642 ps
CPU time 1.53 seconds
Started Apr 02 02:04:08 PM PDT 24
Finished Apr 02 02:04:10 PM PDT 24
Peak memory 216248 kb
Host smart-b84451cc-c323-4df7-b7e9-66e586fcf6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700623631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3700623631
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3343529011
Short name T544
Test name
Test status
Simulation time 401372600 ps
CPU time 0.95 seconds
Started Apr 02 02:04:11 PM PDT 24
Finished Apr 02 02:04:13 PM PDT 24
Peak memory 206212 kb
Host smart-ed416e84-b54e-4c20-aadf-ad1e94ebde82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343529011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3343529011
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3016221175
Short name T490
Test name
Test status
Simulation time 132325960 ps
CPU time 0.73 seconds
Started Apr 02 02:04:27 PM PDT 24
Finished Apr 02 02:04:29 PM PDT 24
Peak memory 205340 kb
Host smart-2c039428-6abb-42cd-98b6-4b83fdf6ecf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016221175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
016221175
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1291144178
Short name T663
Test name
Test status
Simulation time 36853576 ps
CPU time 0.73 seconds
Started Apr 02 02:04:24 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 205420 kb
Host smart-84fb42a3-1258-4541-9431-628e4c41305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291144178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1291144178
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1766758836
Short name T85
Test name
Test status
Simulation time 579503618 ps
CPU time 12.45 seconds
Started Apr 02 02:04:36 PM PDT 24
Finished Apr 02 02:04:51 PM PDT 24
Peak memory 248692 kb
Host smart-010baa6b-aa4d-4e70-bf52-f82975351d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766758836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1766758836
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1435778840
Short name T325
Test name
Test status
Simulation time 826781926 ps
CPU time 5.53 seconds
Started Apr 02 02:04:23 PM PDT 24
Finished Apr 02 02:04:29 PM PDT 24
Peak memory 218720 kb
Host smart-95be87e1-f6e9-4009-b40a-31e9aa70dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435778840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1435778840
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.912194424
Short name T637
Test name
Test status
Simulation time 17579533 ps
CPU time 1.02 seconds
Started Apr 02 02:04:23 PM PDT 24
Finished Apr 02 02:04:24 PM PDT 24
Peak memory 216856 kb
Host smart-44cd5a82-3882-40d6-a57c-4fafd1015e99
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912194424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.912194424
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2729492536
Short name T196
Test name
Test status
Simulation time 858253592 ps
CPU time 5.45 seconds
Started Apr 02 02:04:21 PM PDT 24
Finished Apr 02 02:04:27 PM PDT 24
Peak memory 232776 kb
Host smart-b797db53-a5d2-48bb-94c4-f55803bb4622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729492536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2729492536
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3796409614
Short name T183
Test name
Test status
Simulation time 1367839919 ps
CPU time 7.51 seconds
Started Apr 02 02:04:23 PM PDT 24
Finished Apr 02 02:04:30 PM PDT 24
Peak memory 222664 kb
Host smart-7a7eb2a1-e4ed-4724-8ad0-ded4733768db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796409614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3796409614
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1987813420
Short name T509
Test name
Test status
Simulation time 42339093 ps
CPU time 0.72 seconds
Started Apr 02 02:04:24 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 216300 kb
Host smart-c43aec18-392e-4f10-812b-0c913bbdf53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987813420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1987813420
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4010567185
Short name T742
Test name
Test status
Simulation time 6607491043 ps
CPU time 12.58 seconds
Started Apr 02 02:04:28 PM PDT 24
Finished Apr 02 02:04:41 PM PDT 24
Peak memory 219240 kb
Host smart-d35e6997-f29b-436d-97db-ddc9d419921c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4010567185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4010567185
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1548294486
Short name T390
Test name
Test status
Simulation time 12113492758 ps
CPU time 36.3 seconds
Started Apr 02 02:04:23 PM PDT 24
Finished Apr 02 02:04:59 PM PDT 24
Peak memory 216440 kb
Host smart-e49a3f12-34b9-4c97-924b-7801baddf059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548294486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1548294486
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1596249101
Short name T425
Test name
Test status
Simulation time 37594194195 ps
CPU time 23.23 seconds
Started Apr 02 02:04:25 PM PDT 24
Finished Apr 02 02:04:49 PM PDT 24
Peak memory 216372 kb
Host smart-bdb83396-9a49-4f33-ab1d-3757ce081781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596249101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1596249101
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2132145328
Short name T703
Test name
Test status
Simulation time 709999534 ps
CPU time 3.16 seconds
Started Apr 02 02:04:22 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 216372 kb
Host smart-05417468-7421-47f0-8fe2-b3cfa3f0a925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132145328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2132145328
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2098014625
Short name T650
Test name
Test status
Simulation time 109126753 ps
CPU time 0.93 seconds
Started Apr 02 02:04:25 PM PDT 24
Finished Apr 02 02:04:27 PM PDT 24
Peak memory 206744 kb
Host smart-3e44c344-1b1b-47e6-9329-8d6460372f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098014625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2098014625
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2465512335
Short name T435
Test name
Test status
Simulation time 102880602 ps
CPU time 0.68 seconds
Started Apr 02 02:04:37 PM PDT 24
Finished Apr 02 02:04:40 PM PDT 24
Peak memory 205348 kb
Host smart-7a039269-b322-41e1-8c34-219591e1d81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465512335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
465512335
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4131807926
Short name T87
Test name
Test status
Simulation time 270513991 ps
CPU time 5.43 seconds
Started Apr 02 02:04:37 PM PDT 24
Finished Apr 02 02:04:44 PM PDT 24
Peak memory 222092 kb
Host smart-683f8188-7904-4988-8f2d-149cbe802224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131807926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4131807926
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2504545875
Short name T570
Test name
Test status
Simulation time 42811710 ps
CPU time 0.72 seconds
Started Apr 02 02:04:26 PM PDT 24
Finished Apr 02 02:04:28 PM PDT 24
Peak memory 205460 kb
Host smart-9bff34c7-3644-4544-8aa0-bf3ae9a14a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504545875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2504545875
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2341172019
Short name T358
Test name
Test status
Simulation time 7130043481 ps
CPU time 82.78 seconds
Started Apr 02 02:04:43 PM PDT 24
Finished Apr 02 02:06:08 PM PDT 24
Peak memory 250012 kb
Host smart-aefcb631-9a4e-4adc-bf11-dfe080eefb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341172019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2341172019
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2252760360
Short name T526
Test name
Test status
Simulation time 1115162147 ps
CPU time 3.78 seconds
Started Apr 02 02:04:33 PM PDT 24
Finished Apr 02 02:04:38 PM PDT 24
Peak memory 220948 kb
Host smart-70ba5e09-85c3-46db-bffd-4b437c80b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252760360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2252760360
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3942000382
Short name T506
Test name
Test status
Simulation time 5355393263 ps
CPU time 11.72 seconds
Started Apr 02 02:04:35 PM PDT 24
Finished Apr 02 02:04:47 PM PDT 24
Peak memory 232824 kb
Host smart-c1f0def7-d44f-4653-ba98-c2d529e65978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942000382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3942000382
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3824862497
Short name T605
Test name
Test status
Simulation time 38562054 ps
CPU time 0.99 seconds
Started Apr 02 02:04:36 PM PDT 24
Finished Apr 02 02:04:40 PM PDT 24
Peak memory 216824 kb
Host smart-726731db-5255-4570-845d-d315d8b5760e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824862497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3824862497
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.3882416479
Short name T694
Test name
Test status
Simulation time 19444203 ps
CPU time 0.73 seconds
Started Apr 02 02:04:30 PM PDT 24
Finished Apr 02 02:04:31 PM PDT 24
Peak memory 216268 kb
Host smart-d0c99540-9771-4149-8ad6-934af8e48510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882416479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.3882416479
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.41951483
Short name T475
Test name
Test status
Simulation time 542634067 ps
CPU time 3.71 seconds
Started Apr 02 02:04:37 PM PDT 24
Finished Apr 02 02:04:43 PM PDT 24
Peak memory 222392 kb
Host smart-d94a8b58-16a7-42d4-9bff-eb8cbee50d80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=41951483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct
.41951483
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.406666394
Short name T106
Test name
Test status
Simulation time 2269607256 ps
CPU time 17.96 seconds
Started Apr 02 02:04:31 PM PDT 24
Finished Apr 02 02:04:49 PM PDT 24
Peak memory 216516 kb
Host smart-cc275202-b9a3-4dae-a6fe-e543478dcead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406666394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.406666394
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2893537603
Short name T658
Test name
Test status
Simulation time 269117519 ps
CPU time 2.18 seconds
Started Apr 02 02:04:30 PM PDT 24
Finished Apr 02 02:04:32 PM PDT 24
Peak memory 216176 kb
Host smart-ac11d708-fc59-4232-9e8e-6e892643266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893537603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2893537603
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.857757151
Short name T14
Test name
Test status
Simulation time 96443067 ps
CPU time 1.23 seconds
Started Apr 02 02:04:30 PM PDT 24
Finished Apr 02 02:04:32 PM PDT 24
Peak memory 208000 kb
Host smart-f4d4d43a-884d-4731-bec1-bf00cb1b5e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857757151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.857757151
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4184091164
Short name T556
Test name
Test status
Simulation time 315725629 ps
CPU time 0.99 seconds
Started Apr 02 02:04:32 PM PDT 24
Finished Apr 02 02:04:33 PM PDT 24
Peak memory 206744 kb
Host smart-ea4696c0-3148-449b-af31-026024fd2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184091164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4184091164
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3129779446
Short name T581
Test name
Test status
Simulation time 45765916 ps
CPU time 0.7 seconds
Started Apr 02 02:04:52 PM PDT 24
Finished Apr 02 02:04:54 PM PDT 24
Peak memory 205336 kb
Host smart-63539a8f-ded3-415f-8517-395b2259cb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129779446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
129779446
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2322312681
Short name T580
Test name
Test status
Simulation time 73397546 ps
CPU time 0.76 seconds
Started Apr 02 02:04:42 PM PDT 24
Finished Apr 02 02:04:43 PM PDT 24
Peak memory 206476 kb
Host smart-b52a15dc-a5a0-463a-84f0-0d30d98a869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322312681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2322312681
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2494607694
Short name T553
Test name
Test status
Simulation time 79376273 ps
CPU time 1.04 seconds
Started Apr 02 02:04:42 PM PDT 24
Finished Apr 02 02:04:43 PM PDT 24
Peak memory 216828 kb
Host smart-4d90a45d-120e-42d6-af40-ff373a2ee5e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494607694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2494607694
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1151324345
Short name T345
Test name
Test status
Simulation time 35174692657 ps
CPU time 23.94 seconds
Started Apr 02 02:04:45 PM PDT 24
Finished Apr 02 02:05:11 PM PDT 24
Peak memory 227268 kb
Host smart-351883c3-eab2-4fcd-824f-6f64ef4e18ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151324345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1151324345
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.307383488
Short name T335
Test name
Test status
Simulation time 24122850784 ps
CPU time 20.65 seconds
Started Apr 02 02:04:44 PM PDT 24
Finished Apr 02 02:05:06 PM PDT 24
Peak memory 234260 kb
Host smart-01ad7cf6-03c3-44f0-8224-0face4b0b2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307383488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.307383488
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2589809588
Short name T422
Test name
Test status
Simulation time 20174943 ps
CPU time 0.71 seconds
Started Apr 02 02:04:39 PM PDT 24
Finished Apr 02 02:04:40 PM PDT 24
Peak memory 216288 kb
Host smart-9bcc567f-f9c3-412a-a902-0f0aa72bc16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589809588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2589809588
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.703937964
Short name T680
Test name
Test status
Simulation time 1193227089 ps
CPU time 9.59 seconds
Started Apr 02 02:04:49 PM PDT 24
Finished Apr 02 02:04:58 PM PDT 24
Peak memory 221780 kb
Host smart-304fe74e-94cf-4cc5-a6ec-616daad115b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=703937964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.703937964
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1998671832
Short name T647
Test name
Test status
Simulation time 1423165361 ps
CPU time 7.74 seconds
Started Apr 02 02:04:43 PM PDT 24
Finished Apr 02 02:04:52 PM PDT 24
Peak memory 216416 kb
Host smart-d7aeb8f3-6dd0-4c4f-a75f-321d998356cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998671832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1998671832
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4166798400
Short name T438
Test name
Test status
Simulation time 85523278963 ps
CPU time 19.42 seconds
Started Apr 02 02:04:40 PM PDT 24
Finished Apr 02 02:05:00 PM PDT 24
Peak memory 216384 kb
Host smart-c5479e43-7bc9-4dbe-8564-c9d574e0307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166798400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4166798400
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1794405861
Short name T708
Test name
Test status
Simulation time 607974653 ps
CPU time 1.28 seconds
Started Apr 02 02:04:43 PM PDT 24
Finished Apr 02 02:04:47 PM PDT 24
Peak memory 216360 kb
Host smart-17caae73-1e6d-45a7-a8d4-b62d437c37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794405861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1794405861
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3717430320
Short name T501
Test name
Test status
Simulation time 30257298 ps
CPU time 0.71 seconds
Started Apr 02 02:04:45 PM PDT 24
Finished Apr 02 02:04:46 PM PDT 24
Peak memory 205636 kb
Host smart-675329dd-ddf2-4e1a-9cb7-1ac0925fa8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717430320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3717430320
Directory /workspace/9.spi_device_tpm_sts_read/latest
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