Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1420427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1583907

1

T1

321

T2

1

T3

1921

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2332040	1			T1	1		T2	71		T3	2025
values[0x0]	335898	1			T1	196		T3	435		T16	2
values[0x1]	336396	1			T1	179		T3	495		T16	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1077638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1926696

1

T1

333

T2

29

T3

2126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10990	1			T1	2		T4	1		T5	3
valid_sources[0x01]	9573	1			T2	1		T4	4		T5	7
valid_sources[0x02]	12715	1			T1	2		T16	2		T4	2
valid_sources[0x03]	9132	1			T2	1		T4	6		T5	2
valid_sources[0x04]	9903	1			T1	1		T4	7		T5	3
valid_sources[0x05]	16621	1			T1	1		T4	4		T6	15
valid_sources[0x06]	17327	1			T1	3		T4	3		T5	1
valid_sources[0x07]	9671	1			T1	1		T4	2		T5	2
valid_sources[0x08]	9483	1			T4	4		T5	4		T6	17
valid_sources[0x09]	13276	1			T1	3		T4	5		T5	7
valid_sources[0x0a]	9049	1			T4	6		T5	3		T6	18
valid_sources[0x0b]	10338	1			T1	2		T4	3		T5	6
valid_sources[0x0c]	9409	1			T1	3		T4	2		T5	2
valid_sources[0x0d]	9442	1			T1	3		T4	3		T5	5
valid_sources[0x0e]	12998	1			T1	3		T4	3		T5	18
valid_sources[0x0f]	9428	1			T1	2		T4	2		T5	4
valid_sources[0x10]	9944	1			T1	1		T4	6		T5	1
valid_sources[0x11]	11586	1			T1	2		T4	7		T5	6
valid_sources[0x12]	9519	1			T1	3		T4	9		T5	2
valid_sources[0x13]	9686	1			T1	3		T4	3		T5	3
valid_sources[0x14]	9572	1			T2	1		T4	6		T5	3
valid_sources[0x15]	14576	1			T1	1		T4	4		T6	19
valid_sources[0x16]	10163	1			T4	5		T5	3		T6	14
valid_sources[0x17]	11942	1			T1	1		T4	4		T5	6
valid_sources[0x18]	10263	1			T1	2		T5	1		T6	16
valid_sources[0x19]	27703	1			T1	2		T4	1		T5	5
valid_sources[0x1a]	9807	1			T1	3		T5	11		T6	13
valid_sources[0x1b]	9251	1			T4	3		T5	2		T6	23
valid_sources[0x1c]	23002	1			T1	2		T4	3		T5	6
valid_sources[0x1d]	10495	1			T1	3		T4	3		T5	9
valid_sources[0x1e]	15288	1			T1	3		T4	1		T6	14
valid_sources[0x1f]	9539	1			T1	1		T2	1		T4	4
valid_sources[0x20]	9476	1			T1	2		T4	5		T6	22
valid_sources[0x21]	18047	1			T4	4		T5	1		T6	10
valid_sources[0x22]	8775	1			T4	2		T5	4		T6	10
valid_sources[0x23]	10606	1			T1	1		T4	6		T5	2
valid_sources[0x24]	9531	1			T5	7		T6	15		T7	8
valid_sources[0x25]	10709	1			T1	2		T4	10		T5	1
valid_sources[0x26]	9795	1			T1	1		T2	1		T4	3
valid_sources[0x27]	14710	1			T1	2		T4	4		T5	8
valid_sources[0x28]	14125	1			T1	2		T3	1		T4	4
valid_sources[0x29]	12049	1			T4	4		T5	6		T6	11
valid_sources[0x2a]	9817	1			T4	4		T5	7		T6	14
valid_sources[0x2b]	21091	1			T1	1		T4	6		T6	24
valid_sources[0x2c]	9113	1			T4	6		T5	6		T6	12
valid_sources[0x2d]	10770	1			T1	1		T4	1		T5	3
valid_sources[0x2e]	16876	1			T5	2		T6	30		T7	6
valid_sources[0x2f]	9215	1			T1	3		T4	6		T5	1
valid_sources[0x30]	11884	1			T1	1		T4	8		T5	2
valid_sources[0x31]	12785	1			T1	2		T4	6		T5	3
valid_sources[0x32]	9285	1			T1	2		T4	3		T5	9
valid_sources[0x33]	10566	1			T4	3		T5	1		T6	12
valid_sources[0x34]	9632	1			T1	3		T4	7		T6	13
valid_sources[0x35]	14238	1			T1	2		T4	4		T5	3
valid_sources[0x36]	10889	1			T4	1		T5	10		T6	22
valid_sources[0x37]	11088	1			T1	2		T4	2		T5	5
valid_sources[0x38]	9047	1			T1	1		T4	10		T6	5
valid_sources[0x39]	10818	1			T1	1		T2	1		T4	3
valid_sources[0x3a]	10202	1			T4	3		T6	8		T7	2
valid_sources[0x3b]	12293	1			T1	1		T4	4		T5	3
valid_sources[0x3c]	9353	1			T1	1		T4	6		T5	3
valid_sources[0x3d]	12343	1			T1	3		T4	6		T5	2
valid_sources[0x3e]	18066	1			T1	2		T4	3		T5	4
valid_sources[0x3f]	10390	1			T1	1		T4	3		T5	7
valid_sources[0x40]	11787	1			T1	1		T4	7		T6	17
valid_sources[0x41]	13298	1			T1	3		T4	6		T5	5
valid_sources[0x42]	39044	1			T1	1		T4	1		T5	2
valid_sources[0x43]	10873	1			T4	4		T6	14		T7	3
valid_sources[0x44]	9984	1			T1	3		T4	2		T5	3
valid_sources[0x45]	9677	1			T1	2		T4	3		T5	6
valid_sources[0x46]	12337	1			T1	1		T4	1		T6	16
valid_sources[0x47]	10128	1			T4	4		T5	1		T6	10
valid_sources[0x48]	13087	1			T4	4		T6	21		T7	14
valid_sources[0x49]	10465	1			T1	2		T4	3		T5	2
valid_sources[0x4a]	10063	1			T1	3		T2	3		T4	2
valid_sources[0x4b]	17544	1			T4	4		T5	2		T6	12
valid_sources[0x4c]	9459	1			T1	1		T4	4		T5	6
valid_sources[0x4d]	21931	1			T1	2		T4	4		T5	5
valid_sources[0x4e]	10410	1			T1	2		T4	9		T5	7
valid_sources[0x4f]	9371	1			T1	1		T2	1		T4	3
valid_sources[0x50]	35363	1			T1	1		T4	3		T5	4
valid_sources[0x51]	10529	1			T1	2		T4	5		T6	12
valid_sources[0x52]	9121	1			T1	2		T4	3		T5	4
valid_sources[0x53]	12375	1			T2	2		T4	4		T5	2
valid_sources[0x54]	10553	1			T1	2		T4	1		T5	5
valid_sources[0x55]	9415	1			T1	1		T2	1		T4	3
valid_sources[0x56]	15184	1			T1	2		T3	2954		T4	5
valid_sources[0x57]	12047	1			T4	3		T5	1		T6	10
valid_sources[0x58]	10161	1			T1	1		T4	5		T5	8
valid_sources[0x59]	10026	1			T1	2		T2	3		T4	3
valid_sources[0x5a]	11780	1			T4	5		T5	1		T6	30
valid_sources[0x5b]	8521	1			T1	1		T2	1		T4	2
valid_sources[0x5c]	9110	1			T1	2		T4	2		T6	11
valid_sources[0x5d]	9582	1			T1	3		T2	1		T4	1
valid_sources[0x5e]	9305	1			T1	3		T4	3		T5	3
valid_sources[0x5f]	10124	1			T1	1		T4	3		T5	2
valid_sources[0x60]	9041	1			T1	2		T4	4		T5	4
valid_sources[0x61]	10692	1			T1	4		T4	4		T5	12
valid_sources[0x62]	8950	1			T1	1		T4	2		T6	19
valid_sources[0x63]	9918	1			T1	4		T4	4		T5	2
valid_sources[0x64]	27777	1			T4	4		T5	3		T6	19
valid_sources[0x65]	16839	1			T4	2		T5	2		T6	21
valid_sources[0x66]	9171	1			T1	1		T4	2		T5	10
valid_sources[0x67]	10779	1			T2	1		T4	3		T5	19
valid_sources[0x68]	9059	1			T1	3		T2	4		T5	5
valid_sources[0x69]	10361	1			T4	1		T5	2		T6	14
valid_sources[0x6a]	10255	1			T1	1		T2	2		T4	3
valid_sources[0x6b]	18362	1			T1	2		T4	7		T5	2
valid_sources[0x6c]	8867	1			T1	1		T2	2		T4	3
valid_sources[0x6d]	10940	1			T1	2		T6	18		T7	3
valid_sources[0x6e]	11052	1			T1	1		T2	5		T4	3
valid_sources[0x6f]	8635	1			T4	4		T5	5		T6	15
valid_sources[0x70]	9446	1			T1	1		T4	3		T5	2
valid_sources[0x71]	9673	1			T1	4		T4	3		T5	12
valid_sources[0x72]	11060	1			T1	3		T4	5		T6	9
valid_sources[0x73]	9758	1			T2	1		T4	5		T5	2
valid_sources[0x74]	14019	1			T1	2		T4	6		T5	9
valid_sources[0x75]	10589	1			T1	2		T4	1		T6	17
valid_sources[0x76]	10963	1			T4	1		T6	11		T7	6
valid_sources[0x77]	12342	1			T1	2		T4	5		T5	1
valid_sources[0x78]	11119	1			T1	2		T2	1		T4	4
valid_sources[0x79]	9393	1			T1	4		T4	7		T5	2
valid_sources[0x7a]	13720	1			T1	4		T4	3		T5	7
valid_sources[0x7b]	9649	1			T1	2		T4	2		T5	3
valid_sources[0x7c]	9794	1			T4	7		T5	3		T6	15
valid_sources[0x7d]	9896	1			T1	1		T4	1		T6	19
valid_sources[0x7e]	9437	1			T1	1		T4	5		T5	10
valid_sources[0x7f]	12548	1			T1	6		T4	9		T5	1
valid_sources[0x80]	10393	1			T1	3		T4	2		T5	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

976719

1

T2

1

T3

1000

T4

59

values[0x0]

all_enables

biggest_size

306881

1

T1

171

T3

434

T4

424

values[0x1]

all_enables

biggest_size

300307

1

T1

150

T3

487

T4

458