Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1438119

1

T1

55

T2

70

T3

1034

full_word

1582819

1

T1

321

T2

1

T3

1921

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3020518	1			T1	376		T2	71		T3	2955
auto[TlIntgErrCmd]	145	1			T39	12		T40	11		T125	7
auto[TlIntgErrData]	127	1			T39	3		T40	5		T125	7
auto[TlIntgErrBoth]	148	1			T39	5		T40	14		T125	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333483

1

T1

1

T2

71

T3

2025

auto[1]

687455

1

T1

375

T3

930

T16

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1356523	1			T1	1		T2	70		T3	1025
auto[TlIntgErrNone]	partial	auto[1]	81207	1			T1	54		T3	9		T16	6
auto[TlIntgErrNone]	full_word	auto[0]	976759	1			T2	1		T3	1000		T4	59
auto[TlIntgErrNone]	full_word	auto[1]	606029	1			T1	321		T3	921		T4	882
auto[TlIntgErrCmd]	partial	auto[0]	62	1			T39	7		T40	7		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T39	5		T40	3		T125	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T179	1		T374	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T40	1		T149	1		T373	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T39	1		T40	2		T125	2
auto[TlIntgErrData]	partial	auto[1]	64	1			T39	2		T40	3		T125	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T125	2		T375	1		T376	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T373	1		T179	2		T377	1
auto[TlIntgErrBoth]	partial	auto[0]	72	1			T39	3		T40	7		T125	5
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T39	2		T40	7		T149	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T375	2		T378	1		T379	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T125	1		T149	1		T373	1