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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.12 97.57 92.92 98.61 80.85 95.97 90.92 88.03


Total test records in report: 872
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T156 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1833443983 Apr 04 02:46:20 PM PDT 24 Apr 04 02:46:42 PM PDT 24 5966001184 ps
T178 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2625151235 Apr 04 02:46:52 PM PDT 24 Apr 04 02:47:07 PM PDT 24 13325968896 ps
T780 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2233900387 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:26 PM PDT 24 59429258 ps
T373 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.671445867 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:39 PM PDT 24 1227578895 ps
T105 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2297671711 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:24 PM PDT 24 70106536 ps
T781 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.268388312 Apr 04 02:47:02 PM PDT 24 Apr 04 02:47:03 PM PDT 24 11579949 ps
T782 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2487586065 Apr 04 02:46:20 PM PDT 24 Apr 04 02:46:22 PM PDT 24 28493227 ps
T157 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2237075995 Apr 04 02:46:24 PM PDT 24 Apr 04 02:46:32 PM PDT 24 229679600 ps
T158 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3657726559 Apr 04 02:46:37 PM PDT 24 Apr 04 02:46:39 PM PDT 24 346117019 ps
T179 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1577462839 Apr 04 02:46:49 PM PDT 24 Apr 04 02:47:10 PM PDT 24 5943273892 ps
T375 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2743391357 Apr 04 02:46:51 PM PDT 24 Apr 04 02:47:04 PM PDT 24 1057909666 ps
T180 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3273041620 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:38 PM PDT 24 102744850 ps
T783 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2827540678 Apr 04 02:46:49 PM PDT 24 Apr 04 02:47:08 PM PDT 24 287923841 ps
T181 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3318621960 Apr 04 02:46:37 PM PDT 24 Apr 04 02:46:40 PM PDT 24 114930419 ps
T140 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2874587997 Apr 04 02:46:34 PM PDT 24 Apr 04 02:46:36 PM PDT 24 30585740 ps
T784 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1629173855 Apr 04 02:46:49 PM PDT 24 Apr 04 02:46:50 PM PDT 24 20281346 ps
T785 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2088081551 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:52 PM PDT 24 28705990 ps
T159 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.477357972 Apr 04 02:46:37 PM PDT 24 Apr 04 02:46:39 PM PDT 24 92191481 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2307145504 Apr 04 02:46:37 PM PDT 24 Apr 04 02:46:38 PM PDT 24 21052691 ps
T141 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1807527237 Apr 04 02:46:19 PM PDT 24 Apr 04 02:46:22 PM PDT 24 87841790 ps
T374 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2488754242 Apr 04 02:46:25 PM PDT 24 Apr 04 02:46:38 PM PDT 24 712468295 ps
T786 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3590852021 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:53 PM PDT 24 35861518 ps
T377 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.356397812 Apr 04 02:46:34 PM PDT 24 Apr 04 02:46:41 PM PDT 24 2284762405 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1785651032 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:25 PM PDT 24 262693184 ps
T787 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3607708326 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:56 PM PDT 24 433657219 ps
T162 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1947090083 Apr 04 02:46:48 PM PDT 24 Apr 04 02:46:51 PM PDT 24 99249955 ps
T788 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3968388372 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:52 PM PDT 24 80597728 ps
T789 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.557432910 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:38 PM PDT 24 26413124 ps
T790 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.889741895 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:52 PM PDT 24 52464859 ps
T791 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3152076747 Apr 04 02:47:06 PM PDT 24 Apr 04 02:47:07 PM PDT 24 18915591 ps
T792 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1528129456 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:39 PM PDT 24 291094742 ps
T793 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4183347823 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:53 PM PDT 24 15269964 ps
T794 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2852223644 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:22 PM PDT 24 12338994 ps
T795 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.355831941 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:23 PM PDT 24 31476072 ps
T796 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1102620104 Apr 04 02:46:54 PM PDT 24 Apr 04 02:46:55 PM PDT 24 47583973 ps
T164 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3929486233 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:53 PM PDT 24 86595866 ps
T797 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1452810635 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:24 PM PDT 24 479175655 ps
T798 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.460897596 Apr 04 02:46:39 PM PDT 24 Apr 04 02:46:41 PM PDT 24 195988729 ps
T799 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2428823678 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:27 PM PDT 24 124587488 ps
T800 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2516788986 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:52 PM PDT 24 15044114 ps
T801 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.652107701 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:59 PM PDT 24 4392112096 ps
T802 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3128123698 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:37 PM PDT 24 127296955 ps
T146 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1250508048 Apr 04 02:46:24 PM PDT 24 Apr 04 02:46:28 PM PDT 24 288392141 ps
T803 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2588044015 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:25 PM PDT 24 99393231 ps
T804 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3150347556 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:52 PM PDT 24 66509281 ps
T805 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3376566527 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:38 PM PDT 24 197268462 ps
T148 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3522512613 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:52 PM PDT 24 136117864 ps
T806 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3482018994 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:53 PM PDT 24 13191552 ps
T807 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3370379142 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:52 PM PDT 24 15129793 ps
T378 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3549712658 Apr 04 02:46:41 PM PDT 24 Apr 04 02:46:56 PM PDT 24 1350981928 ps
T808 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1707669655 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:38 PM PDT 24 43863590 ps
T809 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3610786033 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:52 PM PDT 24 12570565 ps
T810 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3726261026 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:53 PM PDT 24 198994154 ps
T811 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3511480793 Apr 04 02:46:34 PM PDT 24 Apr 04 02:46:38 PM PDT 24 117817625 ps
T812 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3762383780 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:41 PM PDT 24 1676078266 ps
T813 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2925166178 Apr 04 02:46:49 PM PDT 24 Apr 04 02:46:52 PM PDT 24 39095240 ps
T106 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2414968096 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:24 PM PDT 24 57730765 ps
T814 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2906920764 Apr 04 02:46:54 PM PDT 24 Apr 04 02:46:55 PM PDT 24 14494635 ps
T815 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.121924266 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:25 PM PDT 24 374078128 ps
T816 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2767706109 Apr 04 02:46:25 PM PDT 24 Apr 04 02:46:27 PM PDT 24 58555427 ps
T379 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.108315217 Apr 04 02:46:38 PM PDT 24 Apr 04 02:46:45 PM PDT 24 107580157 ps
T817 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2397871090 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:55 PM PDT 24 1132753759 ps
T818 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1245349495 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:55 PM PDT 24 229638589 ps
T147 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2008867595 Apr 04 02:46:49 PM PDT 24 Apr 04 02:46:53 PM PDT 24 170647727 ps
T819 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4194304675 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:25 PM PDT 24 971430736 ps
T820 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3539377522 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:53 PM PDT 24 40831299 ps
T821 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1099848323 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:37 PM PDT 24 110206426 ps
T822 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2404231741 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:27 PM PDT 24 348129822 ps
T823 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.923580452 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:30 PM PDT 24 309284101 ps
T824 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1036650514 Apr 04 02:46:38 PM PDT 24 Apr 04 02:46:57 PM PDT 24 310444058 ps
T825 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.83141489 Apr 04 02:46:27 PM PDT 24 Apr 04 02:46:28 PM PDT 24 16992937 ps
T826 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3759444831 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:24 PM PDT 24 343688598 ps
T827 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4055510029 Apr 04 02:46:20 PM PDT 24 Apr 04 02:46:23 PM PDT 24 91312453 ps
T828 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4086508733 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:57 PM PDT 24 237543767 ps
T829 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.47680588 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:49 PM PDT 24 5060394664 ps
T107 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1570203189 Apr 04 02:46:25 PM PDT 24 Apr 04 02:46:26 PM PDT 24 49913585 ps
T830 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.577693675 Apr 04 02:46:34 PM PDT 24 Apr 04 02:46:37 PM PDT 24 81314177 ps
T831 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.294481575 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:36 PM PDT 24 23957449 ps
T832 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3297926890 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:25 PM PDT 24 63345993 ps
T833 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.178801591 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:52 PM PDT 24 26854705 ps
T834 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4033932703 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:54 PM PDT 24 568809708 ps
T835 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.705290841 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:43 PM PDT 24 633118875 ps
T836 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.584714668 Apr 04 02:46:39 PM PDT 24 Apr 04 02:46:42 PM PDT 24 1181626729 ps
T837 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.720091975 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:37 PM PDT 24 22837422 ps
T838 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3192092365 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:04 PM PDT 24 39708485 ps
T839 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4063184394 Apr 04 02:46:33 PM PDT 24 Apr 04 02:46:36 PM PDT 24 108453107 ps
T840 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1926019017 Apr 04 02:46:13 PM PDT 24 Apr 04 02:46:16 PM PDT 24 162991327 ps
T841 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3185873420 Apr 04 02:46:52 PM PDT 24 Apr 04 02:46:53 PM PDT 24 17280084 ps
T842 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.219374106 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:38 PM PDT 24 31297293 ps
T843 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1241048331 Apr 04 02:46:23 PM PDT 24 Apr 04 02:46:31 PM PDT 24 1760718969 ps
T844 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2559658115 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:23 PM PDT 24 11838015 ps
T845 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2063480210 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:53 PM PDT 24 202203085 ps
T846 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.168060118 Apr 04 02:46:24 PM PDT 24 Apr 04 02:46:25 PM PDT 24 15508012 ps
T847 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1466018453 Apr 04 02:47:07 PM PDT 24 Apr 04 02:47:07 PM PDT 24 12218048 ps
T848 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.506078777 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:52 PM PDT 24 46365417 ps
T849 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.643715526 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:25 PM PDT 24 1395316865 ps
T850 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2573012957 Apr 04 02:46:24 PM PDT 24 Apr 04 02:46:25 PM PDT 24 37373699 ps
T851 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3509457112 Apr 04 02:46:19 PM PDT 24 Apr 04 02:46:22 PM PDT 24 372389921 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.45801603 Apr 04 02:46:27 PM PDT 24 Apr 04 02:46:29 PM PDT 24 97906123 ps
T852 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1936176658 Apr 04 02:46:27 PM PDT 24 Apr 04 02:46:27 PM PDT 24 47505829 ps
T853 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.358809620 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:54 PM PDT 24 117428972 ps
T854 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3938924821 Apr 04 02:46:37 PM PDT 24 Apr 04 02:46:40 PM PDT 24 122462612 ps
T855 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3497072678 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:36 PM PDT 24 15110487 ps
T856 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3381010753 Apr 04 02:46:48 PM PDT 24 Apr 04 02:46:48 PM PDT 24 89815206 ps
T857 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3058147482 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:37 PM PDT 24 30130602 ps
T858 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1242265308 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:25 PM PDT 24 224876322 ps
T859 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2717766109 Apr 04 02:46:49 PM PDT 24 Apr 04 02:46:52 PM PDT 24 124651861 ps
T860 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1743647703 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:39 PM PDT 24 129341185 ps
T861 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1644685938 Apr 04 02:46:24 PM PDT 24 Apr 04 02:46:25 PM PDT 24 155072501 ps
T862 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.991089239 Apr 04 02:46:54 PM PDT 24 Apr 04 02:46:55 PM PDT 24 26776122 ps
T863 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1646823474 Apr 04 02:46:22 PM PDT 24 Apr 04 02:46:24 PM PDT 24 148741966 ps
T864 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.925659439 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:38 PM PDT 24 41373982 ps
T865 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1751326551 Apr 04 02:46:20 PM PDT 24 Apr 04 02:46:21 PM PDT 24 40719621 ps
T866 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2411543263 Apr 04 02:46:21 PM PDT 24 Apr 04 02:46:55 PM PDT 24 2088172900 ps
T867 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.60620472 Apr 04 02:46:50 PM PDT 24 Apr 04 02:47:03 PM PDT 24 210161875 ps
T868 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1956879983 Apr 04 02:46:19 PM PDT 24 Apr 04 02:46:20 PM PDT 24 18484213 ps
T376 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.272071335 Apr 04 02:46:34 PM PDT 24 Apr 04 02:46:58 PM PDT 24 1112848703 ps
T869 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.857444926 Apr 04 02:46:51 PM PDT 24 Apr 04 02:46:52 PM PDT 24 63881741 ps
T870 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2009453591 Apr 04 02:46:50 PM PDT 24 Apr 04 02:46:53 PM PDT 24 492596997 ps
T871 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3653755007 Apr 04 02:46:35 PM PDT 24 Apr 04 02:46:44 PM PDT 24 371118228 ps
T372 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2884254576 Apr 04 02:46:36 PM PDT 24 Apr 04 02:46:39 PM PDT 24 169290482 ps
T872 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3386382331 Apr 04 02:46:53 PM PDT 24 Apr 04 02:46:53 PM PDT 24 15386278 ps

Test location /workspace/coverage/default/18.spi_device_intercept.2359015507
Short name T3
Test name
Test status
Simulation time 607549041 ps
CPU time 8.5 seconds
Started Apr 04 12:59:50 PM PDT 24
Finished Apr 04 12:59:58 PM PDT 24
Peak memory 217072 kb
Host smart-05c94d43-7e6d-4191-8f3c-c0ee0218497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359015507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2359015507
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1059650613
Short name T13
Test name
Test status
Simulation time 14413270834 ps
CPU time 24.33 seconds
Started Apr 04 01:02:45 PM PDT 24
Finished Apr 04 01:03:09 PM PDT 24
Peak memory 216652 kb
Host smart-13a5f12e-5658-4c41-95a4-3141b410108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059650613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1059650613
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4033893599
Short name T98
Test name
Test status
Simulation time 32946659407 ps
CPU time 37.54 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:04:01 PM PDT 24
Peak memory 217096 kb
Host smart-8805bfb3-44d9-4f6b-beb8-9069a2db000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033893599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4033893599
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3661597582
Short name T39
Test name
Test status
Simulation time 703271722 ps
CPU time 16.62 seconds
Started Apr 04 02:46:20 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 215428 kb
Host smart-a72496e5-8c7d-481c-9149-24f55ae0af3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661597582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3661597582
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1367057154
Short name T47
Test name
Test status
Simulation time 1892145201 ps
CPU time 18.24 seconds
Started Apr 04 01:04:41 PM PDT 24
Finished Apr 04 01:05:00 PM PDT 24
Peak memory 222544 kb
Host smart-fdce3cbc-28df-49cf-bcda-3ca7eb520824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367057154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1367057154
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2524799162
Short name T389
Test name
Test status
Simulation time 6921155657 ps
CPU time 35.46 seconds
Started Apr 04 01:05:19 PM PDT 24
Finished Apr 04 01:05:56 PM PDT 24
Peak memory 216504 kb
Host smart-3062afa0-7fa0-430c-a862-2f54f2a8ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524799162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2524799162
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.199697480
Short name T34
Test name
Test status
Simulation time 162119570 ps
CPU time 0.95 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:57 PM PDT 24
Peak memory 206676 kb
Host smart-5a391790-d6aa-44af-9dd3-ee8617d36746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199697480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.199697480
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4163170092
Short name T24
Test name
Test status
Simulation time 5077167359 ps
CPU time 26.97 seconds
Started Apr 04 12:56:21 PM PDT 24
Finished Apr 04 12:56:48 PM PDT 24
Peak memory 232968 kb
Host smart-ce78c673-0e37-481a-b33a-2c9b79635c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163170092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4163170092
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2909776213
Short name T110
Test name
Test status
Simulation time 6158930665 ps
CPU time 29.46 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:54 PM PDT 24
Peak memory 216632 kb
Host smart-abb324c0-b8ea-4ef2-9a91-968c6d0e6d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909776213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2909776213
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1991917695
Short name T9
Test name
Test status
Simulation time 1928516080 ps
CPU time 3.75 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:05:44 PM PDT 24
Peak memory 222764 kb
Host smart-3f9de4dd-6ea2-442c-b6c6-8da1fa43822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991917695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1991917695
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3968147385
Short name T484
Test name
Test status
Simulation time 45246416 ps
CPU time 0.72 seconds
Started Apr 04 12:55:42 PM PDT 24
Finished Apr 04 12:55:43 PM PDT 24
Peak memory 216392 kb
Host smart-12068f03-985b-42b7-84f2-22d891a0f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968147385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3968147385
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4031196926
Short name T45
Test name
Test status
Simulation time 2909634689 ps
CPU time 10.63 seconds
Started Apr 04 12:56:52 PM PDT 24
Finished Apr 04 12:57:03 PM PDT 24
Peak memory 237472 kb
Host smart-f5cd131f-1530-4688-9883-645752925e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031196926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4031196926
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_upload.4290540656
Short name T278
Test name
Test status
Simulation time 255702501114 ps
CPU time 43.94 seconds
Started Apr 04 12:58:16 PM PDT 24
Finished Apr 04 12:59:00 PM PDT 24
Peak memory 232964 kb
Host smart-1e6f07be-fba8-4da9-b3cd-d5a90ec94fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290540656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4290540656
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3133541832
Short name T130
Test name
Test status
Simulation time 53791929 ps
CPU time 4.05 seconds
Started Apr 04 02:46:48 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215636 kb
Host smart-ebe68f90-d9d3-42a5-aa9a-41c753f062e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133541832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3133541832
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1053251799
Short name T396
Test name
Test status
Simulation time 34133558850 ps
CPU time 49.21 seconds
Started Apr 04 12:57:48 PM PDT 24
Finished Apr 04 12:58:38 PM PDT 24
Peak memory 216592 kb
Host smart-3b0a6c73-0948-4b23-91a6-ef57bbe82d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053251799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1053251799
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2220083172
Short name T8
Test name
Test status
Simulation time 4799796421 ps
CPU time 24.46 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:43 PM PDT 24
Peak memory 224724 kb
Host smart-a7cb4360-098c-49a9-bc53-e7f408c481e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220083172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2220083172
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3059946528
Short name T27
Test name
Test status
Simulation time 1890065154 ps
CPU time 9.46 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:56 PM PDT 24
Peak memory 224668 kb
Host smart-ad019e32-93ef-4e4f-807a-1094d50acf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059946528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3059946528
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.811110488
Short name T73
Test name
Test status
Simulation time 3920332684 ps
CPU time 11.88 seconds
Started Apr 04 01:05:09 PM PDT 24
Finished Apr 04 01:05:22 PM PDT 24
Peak memory 239528 kb
Host smart-78ef995c-52b6-430f-aad0-9e864cb5ac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811110488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.811110488
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4244822236
Short name T438
Test name
Test status
Simulation time 28033770 ps
CPU time 0.71 seconds
Started Apr 04 01:01:36 PM PDT 24
Finished Apr 04 01:01:37 PM PDT 24
Peak memory 204776 kb
Host smart-d22668b4-ed68-4734-97c7-3c7f8e0955f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244822236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4244822236
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1683104128
Short name T214
Test name
Test status
Simulation time 88821378934 ps
CPU time 21.88 seconds
Started Apr 04 01:00:27 PM PDT 24
Finished Apr 04 01:00:49 PM PDT 24
Peak memory 235172 kb
Host smart-01a2ae6c-96ef-461a-bf29-d148a99bd70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683104128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1683104128
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.714850070
Short name T216
Test name
Test status
Simulation time 9452830565 ps
CPU time 75.83 seconds
Started Apr 04 01:00:28 PM PDT 24
Finished Apr 04 01:01:44 PM PDT 24
Peak memory 222516 kb
Host smart-e1be2b56-5ae7-4349-b7cc-92157bf101c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714850070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.714850070
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.973419540
Short name T531
Test name
Test status
Simulation time 18632408129 ps
CPU time 40.82 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:57 PM PDT 24
Peak memory 216568 kb
Host smart-1cbf1c1a-c887-425c-89c7-b777baa4d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973419540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.973419540
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2425601886
Short name T145
Test name
Test status
Simulation time 30486901 ps
CPU time 1.96 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:51 PM PDT 24
Peak memory 215428 kb
Host smart-3c5a23a6-760a-4ca3-9485-51524f0a537c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425601886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2425601886
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.160909653
Short name T291
Test name
Test status
Simulation time 91422935164 ps
CPU time 20.69 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:04:10 PM PDT 24
Peak memory 224844 kb
Host smart-5762c31d-fee4-467a-9a70-dff9092e5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160909653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.160909653
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3833990435
Short name T133
Test name
Test status
Simulation time 1340252530 ps
CPU time 19.04 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:37 PM PDT 24
Peak memory 220660 kb
Host smart-18cff272-3931-4f88-9986-506edd50226a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833990435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3833990435
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_upload.1103291017
Short name T219
Test name
Test status
Simulation time 26363378415 ps
CPU time 27.67 seconds
Started Apr 04 12:58:25 PM PDT 24
Finished Apr 04 12:58:52 PM PDT 24
Peak memory 224156 kb
Host smart-e79417ec-35f4-42c2-ba43-2d477218606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103291017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1103291017
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1346759652
Short name T187
Test name
Test status
Simulation time 9020245759 ps
CPU time 27.64 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:03:51 PM PDT 24
Peak memory 233988 kb
Host smart-3e372dc5-25fc-4700-9755-286789d4e6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346759652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1346759652
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3928339920
Short name T91
Test name
Test status
Simulation time 12105099718 ps
CPU time 33.75 seconds
Started Apr 04 01:00:34 PM PDT 24
Finished Apr 04 01:01:08 PM PDT 24
Peak memory 236348 kb
Host smart-84b0e923-6407-4076-be40-2cbbd06b1f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928339920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3928339920
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1296069184
Short name T77
Test name
Test status
Simulation time 19214283630 ps
CPU time 9.37 seconds
Started Apr 04 12:58:41 PM PDT 24
Finished Apr 04 12:58:51 PM PDT 24
Peak memory 223752 kb
Host smart-3d931c8f-5bff-4834-ba62-172e826b6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296069184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1296069184
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2613305535
Short name T86
Test name
Test status
Simulation time 239470475885 ps
CPU time 46.48 seconds
Started Apr 04 01:00:45 PM PDT 24
Finished Apr 04 01:01:32 PM PDT 24
Peak memory 232928 kb
Host smart-c384daf8-edd4-423a-981e-1f8bd6dd69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613305535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2613305535
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2099000134
Short name T288
Test name
Test status
Simulation time 10679758101 ps
CPU time 25.14 seconds
Started Apr 04 01:02:03 PM PDT 24
Finished Apr 04 01:02:28 PM PDT 24
Peak memory 224684 kb
Host smart-608f6f09-a7d3-4e35-8722-f17397762a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099000134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2099000134
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2093590381
Short name T232
Test name
Test status
Simulation time 5700944240 ps
CPU time 8.69 seconds
Started Apr 04 01:01:38 PM PDT 24
Finished Apr 04 01:01:47 PM PDT 24
Peak memory 224288 kb
Host smart-3e03a42a-d246-4f41-8ace-7a47b4c4ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093590381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2093590381
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1454643913
Short name T485
Test name
Test status
Simulation time 114081068 ps
CPU time 1.12 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:56:12 PM PDT 24
Peak memory 218180 kb
Host smart-b6fdf812-e46e-49db-a5ed-85b50cc44612
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454643913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1454643913
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.832457184
Short name T387
Test name
Test status
Simulation time 10613227193 ps
CPU time 53.76 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:56:45 PM PDT 24
Peak memory 216612 kb
Host smart-9a30cc54-1d52-4094-81d2-f6d230354aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832457184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.832457184
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3313532846
Short name T337
Test name
Test status
Simulation time 5675801926 ps
CPU time 21.82 seconds
Started Apr 04 12:58:59 PM PDT 24
Finished Apr 04 12:59:21 PM PDT 24
Peak memory 233292 kb
Host smart-1e450290-b280-4529-b8fd-a08666db4ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313532846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3313532846
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2277822937
Short name T260
Test name
Test status
Simulation time 7900000644 ps
CPU time 18.47 seconds
Started Apr 04 01:04:06 PM PDT 24
Finished Apr 04 01:04:25 PM PDT 24
Peak memory 221644 kb
Host smart-e59d4d9b-d29a-4ebd-b8f4-f953464c0618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277822937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2277822937
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3055345457
Short name T239
Test name
Test status
Simulation time 6341821378 ps
CPU time 12.75 seconds
Started Apr 04 12:57:26 PM PDT 24
Finished Apr 04 12:57:39 PM PDT 24
Peak memory 239512 kb
Host smart-6285b2d0-ac52-43f3-b3ee-822e89486b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055345457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3055345457
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.148638915
Short name T49
Test name
Test status
Simulation time 334571663 ps
CPU time 1.14 seconds
Started Apr 04 12:56:01 PM PDT 24
Finished Apr 04 12:56:02 PM PDT 24
Peak memory 235904 kb
Host smart-450081bf-39d4-487a-ac69-c4345a30e88d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148638915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.148638915
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1508341123
Short name T217
Test name
Test status
Simulation time 2465851367 ps
CPU time 6.59 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 12:59:29 PM PDT 24
Peak memory 216956 kb
Host smart-66a9cfdd-4ad3-4441-9ad0-2b4669f05543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508341123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1508341123
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2991687444
Short name T1
Test name
Test status
Simulation time 1232097505 ps
CPU time 6 seconds
Started Apr 04 01:04:27 PM PDT 24
Finished Apr 04 01:04:33 PM PDT 24
Peak memory 216460 kb
Host smart-a6fdb6e8-05a2-4402-b35d-b809b4c4d67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991687444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2991687444
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1287270368
Short name T296
Test name
Test status
Simulation time 841801341 ps
CPU time 10.87 seconds
Started Apr 04 12:58:58 PM PDT 24
Finished Apr 04 12:59:09 PM PDT 24
Peak memory 232868 kb
Host smart-f4de4577-39f2-4fa4-959c-7e78ff27476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287270368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1287270368
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2834847127
Short name T343
Test name
Test status
Simulation time 4052468394 ps
CPU time 29.39 seconds
Started Apr 04 01:02:52 PM PDT 24
Finished Apr 04 01:03:23 PM PDT 24
Peak memory 240632 kb
Host smart-5b813f95-3386-430a-8071-3d6a1e09c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834847127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2834847127
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2636115343
Short name T272
Test name
Test status
Simulation time 5434983996 ps
CPU time 19.92 seconds
Started Apr 04 01:03:54 PM PDT 24
Finished Apr 04 01:04:14 PM PDT 24
Peak memory 234616 kb
Host smart-a3ea0a12-9b2f-4179-a023-b0294ce817ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636115343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2636115343
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3594051109
Short name T102
Test name
Test status
Simulation time 1712871544 ps
CPU time 14.38 seconds
Started Apr 04 01:03:57 PM PDT 24
Finished Apr 04 01:04:11 PM PDT 24
Peak memory 224252 kb
Host smart-e040d859-43b0-43ba-8270-a9b8d5679691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594051109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3594051109
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3223999897
Short name T348
Test name
Test status
Simulation time 14685483377 ps
CPU time 58.85 seconds
Started Apr 04 01:03:01 PM PDT 24
Finished Apr 04 01:04:01 PM PDT 24
Peak memory 224708 kb
Host smart-f8a0c924-2235-493c-b5e0-52e918ab7939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223999897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3223999897
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3867225536
Short name T208
Test name
Test status
Simulation time 2746437964 ps
CPU time 9.97 seconds
Started Apr 04 01:03:01 PM PDT 24
Finished Apr 04 01:03:12 PM PDT 24
Peak memory 233752 kb
Host smart-6d49a797-57fe-42b4-ad35-afddb959fa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867225536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3867225536
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2252380564
Short name T190
Test name
Test status
Simulation time 29676242431 ps
CPU time 19.12 seconds
Started Apr 04 12:56:59 PM PDT 24
Finished Apr 04 12:57:19 PM PDT 24
Peak memory 218640 kb
Host smart-4c5105b3-a926-4c40-af19-12663f401d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252380564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2252380564
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.52729675
Short name T255
Test name
Test status
Simulation time 33295581357 ps
CPU time 91.69 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:57:43 PM PDT 24
Peak memory 240012 kb
Host smart-ebaca3c0-7695-40de-b037-f82c04687c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52729675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.52729675
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1490860590
Short name T318
Test name
Test status
Simulation time 4633931874 ps
CPU time 66.52 seconds
Started Apr 04 12:57:17 PM PDT 24
Finished Apr 04 12:58:24 PM PDT 24
Peak memory 239824 kb
Host smart-12cd3bef-cfe2-4d93-94a1-b8be197e319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490860590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1490860590
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.493636047
Short name T99
Test name
Test status
Simulation time 930906685 ps
CPU time 9.29 seconds
Started Apr 04 12:57:26 PM PDT 24
Finished Apr 04 12:57:35 PM PDT 24
Peak memory 218272 kb
Host smart-70b7f4de-10e1-45cd-ace2-754f0182b9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493636047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.493636047
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.671445867
Short name T373
Test name
Test status
Simulation time 1227578895 ps
CPU time 17.17 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215600 kb
Host smart-2677376d-5848-445a-9136-6cfecf5314ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671445867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.671445867
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1904965918
Short name T112
Test name
Test status
Simulation time 3393023041 ps
CPU time 42.44 seconds
Started Apr 04 12:59:35 PM PDT 24
Finished Apr 04 01:00:18 PM PDT 24
Peak memory 216608 kb
Host smart-01d7a491-387e-4052-920f-78898e324bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904965918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1904965918
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2829810870
Short name T222
Test name
Test status
Simulation time 850226323 ps
CPU time 3.11 seconds
Started Apr 04 12:59:50 PM PDT 24
Finished Apr 04 12:59:53 PM PDT 24
Peak memory 218628 kb
Host smart-a27e32e3-2d70-4cfe-a088-561032bf0b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829810870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2829810870
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1298733760
Short name T185
Test name
Test status
Simulation time 1967718810 ps
CPU time 8.77 seconds
Started Apr 04 01:02:35 PM PDT 24
Finished Apr 04 01:02:44 PM PDT 24
Peak memory 224144 kb
Host smart-015ec1c3-9dbd-4ed7-badb-5c7b84ad9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298733760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1298733760
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_upload.247427832
Short name T211
Test name
Test status
Simulation time 495721998 ps
CPU time 6.05 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:02 PM PDT 24
Peak memory 224752 kb
Host smart-6676a2fe-51da-4a08-8b18-0f93d4c9942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247427832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.247427832
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.740460663
Short name T228
Test name
Test status
Simulation time 35942207165 ps
CPU time 24.94 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:06:05 PM PDT 24
Peak memory 236400 kb
Host smart-2bb6a7cd-2fae-47fd-bb1a-dc046bff5a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740460663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.740460663
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1042399597
Short name T119
Test name
Test status
Simulation time 2128934556 ps
CPU time 24.08 seconds
Started Apr 04 01:01:49 PM PDT 24
Finished Apr 04 01:02:13 PM PDT 24
Peak memory 244248 kb
Host smart-340d488a-e4c3-4ff4-b85e-58fab70e1856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042399597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1042399597
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3274401591
Short name T268
Test name
Test status
Simulation time 6532029995 ps
CPU time 24.37 seconds
Started Apr 04 12:58:18 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 224360 kb
Host smart-0e11395b-5112-4829-80fa-b0757f8bec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274401591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3274401591
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1373376432
Short name T353
Test name
Test status
Simulation time 3322338119 ps
CPU time 8.6 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:01:03 PM PDT 24
Peak memory 224424 kb
Host smart-456f83e3-f309-4fa4-99aa-6df689f71e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373376432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1373376432
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2249198458
Short name T390
Test name
Test status
Simulation time 3275483755 ps
CPU time 33.03 seconds
Started Apr 04 01:01:34 PM PDT 24
Finished Apr 04 01:02:07 PM PDT 24
Peak memory 216568 kb
Host smart-6c23a9c1-22a8-4bd4-bdba-171e758de377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249198458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2249198458
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4172206484
Short name T271
Test name
Test status
Simulation time 6769855131 ps
CPU time 20.5 seconds
Started Apr 04 01:02:35 PM PDT 24
Finished Apr 04 01:02:56 PM PDT 24
Peak memory 220004 kb
Host smart-3d61db83-1ebc-4635-92aa-c21a9f3bb0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172206484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4172206484
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1255051254
Short name T253
Test name
Test status
Simulation time 34858846395 ps
CPU time 21.79 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:04:10 PM PDT 24
Peak memory 232840 kb
Host smart-5450c09e-de0c-4196-8a43-e46ccbbdca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255051254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1255051254
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4210934595
Short name T210
Test name
Test status
Simulation time 1187617478 ps
CPU time 12.17 seconds
Started Apr 04 01:05:09 PM PDT 24
Finished Apr 04 01:05:21 PM PDT 24
Peak memory 220936 kb
Host smart-c2965808-623f-4ccb-b255-779121830ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210934595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4210934595
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2286375748
Short name T242
Test name
Test status
Simulation time 1548682324 ps
CPU time 14.5 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:55 PM PDT 24
Peak memory 223736 kb
Host smart-243557cd-3f31-4865-8307-ee50a64d4392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286375748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2286375748
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.567311189
Short name T341
Test name
Test status
Simulation time 10730784874 ps
CPU time 22.98 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:58:02 PM PDT 24
Peak memory 220268 kb
Host smart-7bdd1a97-d22e-430d-ae2f-f081b85cfb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567311189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.567311189
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1038886413
Short name T122
Test name
Test status
Simulation time 178794519 ps
CPU time 1.25 seconds
Started Apr 04 02:46:33 PM PDT 24
Finished Apr 04 02:46:35 PM PDT 24
Peak memory 215460 kb
Host smart-3246bd35-7ff6-4718-ae62-a13df7eec7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038886413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1038886413
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1380635716
Short name T307
Test name
Test status
Simulation time 7862480327 ps
CPU time 112.1 seconds
Started Apr 04 12:58:18 PM PDT 24
Finished Apr 04 01:00:10 PM PDT 24
Peak memory 239456 kb
Host smart-7308da67-c2ba-46e6-bcb1-85bdfa87c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380635716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1380635716
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4133222913
Short name T297
Test name
Test status
Simulation time 140748566 ps
CPU time 3.54 seconds
Started Apr 04 12:56:31 PM PDT 24
Finished Apr 04 12:56:34 PM PDT 24
Peak memory 222988 kb
Host smart-eff1ee62-9c84-4b61-a32d-b841bba06e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133222913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4133222913
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4247607625
Short name T118
Test name
Test status
Simulation time 107892056 ps
CPU time 3.83 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:30 PM PDT 24
Peak memory 218768 kb
Host smart-e0eae5cd-6dee-4301-b20f-b6bada1e2f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247607625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4247607625
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.292049813
Short name T188
Test name
Test status
Simulation time 1973356609 ps
CPU time 7.13 seconds
Started Apr 04 01:01:04 PM PDT 24
Finished Apr 04 01:01:11 PM PDT 24
Peak memory 216568 kb
Host smart-f1a45d8a-a86d-492d-bcaf-ae7c5ca912c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292049813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.292049813
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.346209753
Short name T35
Test name
Test status
Simulation time 66195768 ps
CPU time 1.13 seconds
Started Apr 04 01:02:43 PM PDT 24
Finished Apr 04 01:02:44 PM PDT 24
Peak memory 207320 kb
Host smart-e8e6cbcf-cc11-4da8-a11c-5141f8b0c026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346209753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.346209753
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1711929155
Short name T10
Test name
Test status
Simulation time 26488670131 ps
CPU time 20.43 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:03:44 PM PDT 24
Peak memory 224764 kb
Host smart-2191a31e-22f6-4c9c-9a8c-175f64058c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711929155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1711929155
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4045687367
Short name T184
Test name
Test status
Simulation time 15829552514 ps
CPU time 39.06 seconds
Started Apr 04 01:04:26 PM PDT 24
Finished Apr 04 01:05:05 PM PDT 24
Peak memory 237488 kb
Host smart-5aee30e2-4941-42ac-b378-65265c14ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045687367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4045687367
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_upload.91336855
Short name T194
Test name
Test status
Simulation time 18347706577 ps
CPU time 15.59 seconds
Started Apr 04 12:57:15 PM PDT 24
Finished Apr 04 12:57:30 PM PDT 24
Peak memory 220168 kb
Host smart-683b4e72-7fab-46f5-aab5-2af7765f98cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91336855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.91336855
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4173499891
Short name T299
Test name
Test status
Simulation time 19268564259 ps
CPU time 11.79 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:58:08 PM PDT 24
Peak memory 218740 kb
Host smart-cd9c73d7-fcf2-46ff-8bd1-24f92b4cb5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173499891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4173499891
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3762624148
Short name T196
Test name
Test status
Simulation time 1045954645 ps
CPU time 13.61 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:22 PM PDT 24
Peak memory 223236 kb
Host smart-0b0d10db-de72-49ab-9a58-4ae6ad11967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762624148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3762624148
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3803140
Short name T72
Test name
Test status
Simulation time 3238326502 ps
CPU time 12.91 seconds
Started Apr 04 12:58:08 PM PDT 24
Finished Apr 04 12:58:21 PM PDT 24
Peak memory 233308 kb
Host smart-58a879bc-cd4c-474e-931a-ef4ec91b0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3803140
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1459578858
Short name T66
Test name
Test status
Simulation time 2200032622 ps
CPU time 17.42 seconds
Started Apr 04 12:58:26 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 216596 kb
Host smart-77022381-2285-4ac3-948d-a6c328340fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459578858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1459578858
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2743391357
Short name T375
Test name
Test status
Simulation time 1057909666 ps
CPU time 12.33 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 215420 kb
Host smart-5ebd8a62-9bcd-4c44-966d-d3eba074ce93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743391357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2743391357
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.234300735
Short name T362
Test name
Test status
Simulation time 15587523816 ps
CPU time 62.61 seconds
Started Apr 04 12:56:21 PM PDT 24
Finished Apr 04 12:57:24 PM PDT 24
Peak memory 233444 kb
Host smart-9918e877-fee0-42e2-adae-3fa0a63ecbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234300735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.234300735
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2962728108
Short name T323
Test name
Test status
Simulation time 13874422816 ps
CPU time 19.15 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 220688 kb
Host smart-e50c2702-5a76-47b6-979d-2b33c7dcbf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962728108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2962728108
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.721753011
Short name T251
Test name
Test status
Simulation time 80037061 ps
CPU time 2.99 seconds
Started Apr 04 12:59:09 PM PDT 24
Finished Apr 04 12:59:12 PM PDT 24
Peak memory 222856 kb
Host smart-295f1854-554e-4ec5-8eb5-0f66c6ee5f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721753011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.721753011
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1913381366
Short name T285
Test name
Test status
Simulation time 2794087542 ps
CPU time 14.34 seconds
Started Apr 04 12:59:08 PM PDT 24
Finished Apr 04 12:59:22 PM PDT 24
Peak memory 222792 kb
Host smart-febd74c1-7262-4ea5-92d6-1ac4c5912545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913381366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1913381366
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_upload.4132678962
Short name T324
Test name
Test status
Simulation time 165116538 ps
CPU time 2.81 seconds
Started Apr 04 12:59:31 PM PDT 24
Finished Apr 04 12:59:34 PM PDT 24
Peak memory 216544 kb
Host smart-c3b3cba2-e3c7-4ac6-93ad-ad7333ace6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132678962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4132678962
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3291567082
Short name T87
Test name
Test status
Simulation time 1568159746 ps
CPU time 5.21 seconds
Started Apr 04 01:00:06 PM PDT 24
Finished Apr 04 01:00:12 PM PDT 24
Peak memory 224588 kb
Host smart-cafa11cb-641c-42f3-a6ae-3233391ad4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291567082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3291567082
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.487528655
Short name T289
Test name
Test status
Simulation time 1494292309 ps
CPU time 7.61 seconds
Started Apr 04 01:00:44 PM PDT 24
Finished Apr 04 01:00:52 PM PDT 24
Peak memory 219340 kb
Host smart-ab0e61ca-5a9f-445f-9b41-9fb7fc69a29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487528655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.487528655
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.570093683
Short name T71
Test name
Test status
Simulation time 83322283 ps
CPU time 2.23 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:20 PM PDT 24
Peak memory 218724 kb
Host smart-00f21d5d-73d4-4d73-a74e-bfb627bd3aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570093683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.570093683
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2472781023
Short name T292
Test name
Test status
Simulation time 471129663 ps
CPU time 8.26 seconds
Started Apr 04 01:02:02 PM PDT 24
Finished Apr 04 01:02:11 PM PDT 24
Peak memory 224716 kb
Host smart-639a779a-29cd-473c-9b8f-0fd0bd3933f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472781023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2472781023
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2107244285
Short name T83
Test name
Test status
Simulation time 1008372292 ps
CPU time 7.89 seconds
Started Apr 04 01:02:19 PM PDT 24
Finished Apr 04 01:02:27 PM PDT 24
Peak memory 237880 kb
Host smart-93a8666d-9774-4a14-a9ae-97cd9d637f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107244285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2107244285
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2877171282
Short name T85
Test name
Test status
Simulation time 1512461361 ps
CPU time 8.93 seconds
Started Apr 04 01:02:34 PM PDT 24
Finished Apr 04 01:02:43 PM PDT 24
Peak memory 223964 kb
Host smart-4a7c19cb-3e75-4651-8457-20d954a51150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877171282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2877171282
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.557751974
Short name T248
Test name
Test status
Simulation time 45692518272 ps
CPU time 26.29 seconds
Started Apr 04 01:02:34 PM PDT 24
Finished Apr 04 01:03:01 PM PDT 24
Peak memory 220492 kb
Host smart-d0db7968-c4ce-4dfc-b9ae-57942847cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557751974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.557751974
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4097863255
Short name T283
Test name
Test status
Simulation time 12571647471 ps
CPU time 18.4 seconds
Started Apr 04 01:02:51 PM PDT 24
Finished Apr 04 01:03:10 PM PDT 24
Peak memory 232880 kb
Host smart-184c2dad-6e47-402a-ad44-618f4de069b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097863255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4097863255
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.341622415
Short name T201
Test name
Test status
Simulation time 205163729 ps
CPU time 3.87 seconds
Started Apr 04 01:03:21 PM PDT 24
Finished Apr 04 01:03:27 PM PDT 24
Peak memory 218728 kb
Host smart-4a27fef4-173f-4dde-ab80-c2c9a153c054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341622415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.341622415
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.4219551305
Short name T246
Test name
Test status
Simulation time 288303070 ps
CPU time 5.24 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:19 PM PDT 24
Peak memory 224040 kb
Host smart-dbce373d-845f-4c02-8f93-ebedbda6cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219551305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4219551305
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2148843188
Short name T84
Test name
Test status
Simulation time 9170858026 ps
CPU time 16.35 seconds
Started Apr 04 01:04:00 PM PDT 24
Finished Apr 04 01:04:17 PM PDT 24
Peak memory 239112 kb
Host smart-80f7c893-8a60-4bae-a8ee-ba860dc2e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148843188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2148843188
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2729989596
Short name T198
Test name
Test status
Simulation time 8091021299 ps
CPU time 95.8 seconds
Started Apr 04 12:57:08 PM PDT 24
Finished Apr 04 12:58:45 PM PDT 24
Peak memory 232160 kb
Host smart-5519fba2-ce1f-43e7-a425-98db104e5163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729989596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2729989596
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1634917669
Short name T128
Test name
Test status
Simulation time 2503964550 ps
CPU time 19.2 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:59 PM PDT 24
Peak memory 219248 kb
Host smart-84e6a59e-1c17-4506-b757-097dd8911566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634917669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1634917669
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.478573175
Short name T90
Test name
Test status
Simulation time 5139473503 ps
CPU time 23.94 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:06:05 PM PDT 24
Peak memory 222596 kb
Host smart-dceaeeaf-25b3-49ed-8939-ea410a33168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478573175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.478573175
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.930459152
Short name T274
Test name
Test status
Simulation time 445739349 ps
CPU time 3.7 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:20 PM PDT 24
Peak memory 218592 kb
Host smart-f269bc2b-4e34-4a13-9bb3-793c0a3b29bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930459152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
930459152
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2721590541
Short name T265
Test name
Test status
Simulation time 9875827256 ps
CPU time 19.03 seconds
Started Apr 04 01:02:36 PM PDT 24
Finished Apr 04 01:02:55 PM PDT 24
Peak memory 222628 kb
Host smart-941fcb4a-279e-4200-97b1-ff0d1b600abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721590541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2721590541
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1577462839
Short name T179
Test name
Test status
Simulation time 5943273892 ps
CPU time 20.88 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:47:10 PM PDT 24
Peak memory 215388 kb
Host smart-300b7e2a-cffc-44ef-9e7d-90f2ea3ee0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577462839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1577462839
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3464854811
Short name T213
Test name
Test status
Simulation time 1108682168 ps
CPU time 4.99 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:55:56 PM PDT 24
Peak memory 224728 kb
Host smart-a3b28a3f-86a7-4439-9c5c-dd1b578b8439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464854811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3464854811
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_intercept.630577558
Short name T267
Test name
Test status
Simulation time 638328057 ps
CPU time 3.78 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:21 PM PDT 24
Peak memory 222640 kb
Host smart-9b3676fc-8361-495a-a8c6-7e42d3cf439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630577558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.630577558
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2917490790
Short name T349
Test name
Test status
Simulation time 1537838334 ps
CPU time 4.65 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:22 PM PDT 24
Peak memory 223064 kb
Host smart-d669bd8d-90ab-4e64-b7be-b2f983ea556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917490790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2917490790
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.313417136
Short name T81
Test name
Test status
Simulation time 6606618624 ps
CPU time 11.62 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:36 PM PDT 24
Peak memory 222924 kb
Host smart-c497ff09-dc65-4108-b8ec-8241ab1c587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313417136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.313417136
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3203690339
Short name T344
Test name
Test status
Simulation time 8979791220 ps
CPU time 13.9 seconds
Started Apr 04 12:58:41 PM PDT 24
Finished Apr 04 12:58:56 PM PDT 24
Peak memory 232732 kb
Host smart-e84eac2b-2099-4931-b115-1b93d86f72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203690339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3203690339
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_upload.778597938
Short name T257
Test name
Test status
Simulation time 7611430567 ps
CPU time 13.89 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 12:58:56 PM PDT 24
Peak memory 240916 kb
Host smart-2fbabdee-1811-4c24-af28-e0bfcd68f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778597938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.778597938
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2928710241
Short name T12
Test name
Test status
Simulation time 3258999536 ps
CPU time 8.79 seconds
Started Apr 04 12:59:00 PM PDT 24
Finished Apr 04 12:59:09 PM PDT 24
Peak memory 217124 kb
Host smart-21cc15db-043c-40e7-8531-3e16c97f6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928710241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2928710241
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2232035112
Short name T121
Test name
Test status
Simulation time 4638401079 ps
CPU time 14.4 seconds
Started Apr 04 12:59:07 PM PDT 24
Finished Apr 04 12:59:21 PM PDT 24
Peak memory 219060 kb
Host smart-d21de3c0-e71a-4ec1-9167-b89b2855f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232035112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2232035112
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2389648890
Short name T345
Test name
Test status
Simulation time 1140198259 ps
CPU time 13.66 seconds
Started Apr 04 12:59:09 PM PDT 24
Finished Apr 04 12:59:23 PM PDT 24
Peak memory 219164 kb
Host smart-6e86f5bc-6ca6-4d37-a3fc-b327ee412c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389648890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2389648890
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.22470897
Short name T298
Test name
Test status
Simulation time 791147882 ps
CPU time 3.57 seconds
Started Apr 04 12:59:14 PM PDT 24
Finished Apr 04 12:59:17 PM PDT 24
Peak memory 223112 kb
Host smart-d68d0356-26c0-4e9a-90a5-d49eaedc260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22470897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.22470897
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3313267688
Short name T254
Test name
Test status
Simulation time 127298941 ps
CPU time 3.14 seconds
Started Apr 04 12:59:22 PM PDT 24
Finished Apr 04 12:59:25 PM PDT 24
Peak memory 223292 kb
Host smart-d751c0b7-51bb-4cdc-9329-d2bfbf9f9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313267688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3313267688
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1161550922
Short name T88
Test name
Test status
Simulation time 1076764199 ps
CPU time 5.85 seconds
Started Apr 04 12:59:35 PM PDT 24
Finished Apr 04 12:59:41 PM PDT 24
Peak memory 221220 kb
Host smart-acf1e340-0225-4468-b7e7-1a701009f289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161550922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1161550922
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2562070799
Short name T325
Test name
Test status
Simulation time 589911348 ps
CPU time 5.56 seconds
Started Apr 04 12:59:33 PM PDT 24
Finished Apr 04 12:59:39 PM PDT 24
Peak memory 222252 kb
Host smart-01a29ee7-485c-4455-9fb8-3fe839a660c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562070799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2562070799
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4094383813
Short name T328
Test name
Test status
Simulation time 13986203144 ps
CPU time 25.99 seconds
Started Apr 04 12:59:49 PM PDT 24
Finished Apr 04 01:00:15 PM PDT 24
Peak memory 233000 kb
Host smart-6f8ea818-7d1b-4fb4-922e-bd992c7c51e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094383813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4094383813
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2569830788
Short name T351
Test name
Test status
Simulation time 11225517831 ps
CPU time 12.81 seconds
Started Apr 04 12:59:41 PM PDT 24
Finished Apr 04 12:59:54 PM PDT 24
Peak memory 221604 kb
Host smart-c0ff5370-f79b-42df-8ab5-bfc9d42b9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569830788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2569830788
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.643887592
Short name T269
Test name
Test status
Simulation time 528509490 ps
CPU time 2.46 seconds
Started Apr 04 12:59:58 PM PDT 24
Finished Apr 04 01:00:01 PM PDT 24
Peak memory 216520 kb
Host smart-91210857-e0ff-48c3-87dd-6d9223a2c4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643887592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.643887592
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1211607782
Short name T243
Test name
Test status
Simulation time 466534816 ps
CPU time 6.68 seconds
Started Apr 04 12:56:31 PM PDT 24
Finished Apr 04 12:56:38 PM PDT 24
Peak memory 224564 kb
Host smart-7e603564-9b2d-4b89-bf17-404e99898ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211607782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1211607782
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_upload.1125523903
Short name T258
Test name
Test status
Simulation time 1596087161 ps
CPU time 6.39 seconds
Started Apr 04 01:00:06 PM PDT 24
Finished Apr 04 01:00:13 PM PDT 24
Peak memory 220112 kb
Host smart-fe1fd2c4-4074-434f-9da2-049c78a16a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125523903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1125523903
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3359214910
Short name T224
Test name
Test status
Simulation time 172346609 ps
CPU time 3.36 seconds
Started Apr 04 01:00:26 PM PDT 24
Finished Apr 04 01:00:30 PM PDT 24
Peak memory 224568 kb
Host smart-63e67fd4-3a76-4449-b78a-dd245dc427e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359214910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3359214910
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2179260897
Short name T193
Test name
Test status
Simulation time 12989780498 ps
CPU time 20.21 seconds
Started Apr 04 01:00:33 PM PDT 24
Finished Apr 04 01:00:53 PM PDT 24
Peak memory 232892 kb
Host smart-3cac1dd7-6849-42ac-be67-6519938a3ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179260897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2179260897
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1059392017
Short name T273
Test name
Test status
Simulation time 506800516 ps
CPU time 3.04 seconds
Started Apr 04 01:01:04 PM PDT 24
Finished Apr 04 01:01:07 PM PDT 24
Peak memory 223120 kb
Host smart-2ef61bc2-0068-48fd-8d9e-100c53bcc608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059392017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1059392017
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_upload.2806130608
Short name T4
Test name
Test status
Simulation time 4859102764 ps
CPU time 5.86 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:24 PM PDT 24
Peak memory 223580 kb
Host smart-9b7c24f3-8482-42f0-b24d-6db6e353f488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806130608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2806130608
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2352460072
Short name T189
Test name
Test status
Simulation time 581255884 ps
CPU time 7.21 seconds
Started Apr 04 01:01:47 PM PDT 24
Finished Apr 04 01:01:54 PM PDT 24
Peak memory 218244 kb
Host smart-91332f09-f117-43d7-a402-18e1723295b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352460072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2352460072
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1774243468
Short name T294
Test name
Test status
Simulation time 221117182 ps
CPU time 4 seconds
Started Apr 04 01:01:47 PM PDT 24
Finished Apr 04 01:01:51 PM PDT 24
Peak memory 222920 kb
Host smart-dbceca6d-3362-41bc-86f9-7a01a6f5c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774243468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1774243468
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1981035222
Short name T303
Test name
Test status
Simulation time 13192658533 ps
CPU time 7.43 seconds
Started Apr 04 12:56:50 PM PDT 24
Finished Apr 04 12:56:58 PM PDT 24
Peak memory 232904 kb
Host smart-d78098bb-45a1-4eb3-ac39-dff2a3924fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981035222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1981035222
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1901169669
Short name T209
Test name
Test status
Simulation time 661958778 ps
CPU time 2.31 seconds
Started Apr 04 01:02:02 PM PDT 24
Finished Apr 04 01:02:05 PM PDT 24
Peak memory 218648 kb
Host smart-df5d3076-1d9e-4c0c-8594-af74fa28e56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901169669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1901169669
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4087145739
Short name T76
Test name
Test status
Simulation time 31652473222 ps
CPU time 13.1 seconds
Started Apr 04 01:02:36 PM PDT 24
Finished Apr 04 01:02:49 PM PDT 24
Peak memory 234892 kb
Host smart-f0b5b082-7b7a-4d5d-9ae3-31521e1f1214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087145739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4087145739
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.152615288
Short name T80
Test name
Test status
Simulation time 1712844340 ps
CPU time 6.28 seconds
Started Apr 04 01:03:02 PM PDT 24
Finished Apr 04 01:03:08 PM PDT 24
Peak memory 216980 kb
Host smart-6b04c7bb-1d10-4659-aa44-31bc32c69519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152615288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.152615288
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_intercept.677734347
Short name T276
Test name
Test status
Simulation time 162499990 ps
CPU time 2.7 seconds
Started Apr 04 01:03:12 PM PDT 24
Finished Apr 04 01:03:15 PM PDT 24
Peak memory 221064 kb
Host smart-f705b3bc-7fc3-405b-9d62-d5b48b61101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677734347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.677734347
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1434594572
Short name T352
Test name
Test status
Simulation time 465785349 ps
CPU time 7.64 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:21 PM PDT 24
Peak memory 237792 kb
Host smart-404936ca-9346-48c7-95b4-f2ecba7ee8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434594572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1434594572
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.745844842
Short name T277
Test name
Test status
Simulation time 4558780696 ps
CPU time 17.1 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:04:04 PM PDT 24
Peak memory 233072 kb
Host smart-264f0081-838f-446b-928d-4baeb6697b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745844842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.745844842
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_upload.1356946487
Short name T290
Test name
Test status
Simulation time 1796858109 ps
CPU time 6.48 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:03:54 PM PDT 24
Peak memory 223168 kb
Host smart-06cde4fb-2bb3-4635-9282-56b578e8d0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356946487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1356946487
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_upload.2977298886
Short name T226
Test name
Test status
Simulation time 4012431884 ps
CPU time 11.78 seconds
Started Apr 04 01:03:55 PM PDT 24
Finished Apr 04 01:04:07 PM PDT 24
Peak memory 224744 kb
Host smart-e9a9e520-9568-436c-a35d-7566139f4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977298886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2977298886
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1172894927
Short name T338
Test name
Test status
Simulation time 13557355744 ps
CPU time 10.4 seconds
Started Apr 04 12:56:59 PM PDT 24
Finished Apr 04 12:57:10 PM PDT 24
Peak memory 217080 kb
Host smart-e4892bf5-bf4f-4073-8921-dc9d3f15e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172894927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1172894927
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2998246188
Short name T321
Test name
Test status
Simulation time 4087633556 ps
CPU time 37.53 seconds
Started Apr 04 01:04:04 PM PDT 24
Finished Apr 04 01:04:41 PM PDT 24
Peak memory 225352 kb
Host smart-47f14b97-5511-485c-81ad-a5d2f822c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998246188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2998246188
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1881320752
Short name T235
Test name
Test status
Simulation time 1915638468 ps
CPU time 6.57 seconds
Started Apr 04 01:04:19 PM PDT 24
Finished Apr 04 01:04:25 PM PDT 24
Peak memory 222408 kb
Host smart-e8139306-9663-450b-9605-3aa855b66571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881320752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1881320752
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3014418917
Short name T279
Test name
Test status
Simulation time 8493073765 ps
CPU time 26.12 seconds
Started Apr 04 01:04:26 PM PDT 24
Finished Apr 04 01:04:52 PM PDT 24
Peak memory 232916 kb
Host smart-45d72b91-2f8f-4faf-aa26-15137b584702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014418917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3014418917
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3268326841
Short name T236
Test name
Test status
Simulation time 356696617 ps
CPU time 5.98 seconds
Started Apr 04 01:04:54 PM PDT 24
Finished Apr 04 01:05:01 PM PDT 24
Peak memory 222864 kb
Host smart-fcc554ad-0b57-4553-a5c7-1751815edbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268326841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3268326841
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2011279677
Short name T229
Test name
Test status
Simulation time 341181302 ps
CPU time 2.63 seconds
Started Apr 04 01:06:03 PM PDT 24
Finished Apr 04 01:06:05 PM PDT 24
Peak memory 218632 kb
Host smart-cb193b87-78f2-4a19-a0e2-c1cb5c41f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011279677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2011279677
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3032653916
Short name T207
Test name
Test status
Simulation time 1420869532 ps
CPU time 15.32 seconds
Started Apr 04 01:05:49 PM PDT 24
Finished Apr 04 01:06:04 PM PDT 24
Peak memory 231404 kb
Host smart-b1c27957-6a39-4212-a48e-5901f5ade86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032653916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3032653916
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2236157272
Short name T354
Test name
Test status
Simulation time 9359731397 ps
CPU time 10.25 seconds
Started Apr 04 12:57:40 PM PDT 24
Finished Apr 04 12:57:50 PM PDT 24
Peak memory 222868 kb
Host smart-c1093d69-f655-4e01-8a19-866ae3100862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236157272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2236157272
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1284574736
Short name T313
Test name
Test status
Simulation time 12352942656 ps
CPU time 40.59 seconds
Started Apr 04 12:58:07 PM PDT 24
Finished Apr 04 12:58:48 PM PDT 24
Peak memory 236448 kb
Host smart-d86381d0-a093-4225-b771-16a8c3cdfaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284574736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1284574736
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3617324774
Short name T350
Test name
Test status
Simulation time 187564187 ps
CPU time 2.96 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:12 PM PDT 24
Peak memory 222156 kb
Host smart-94bcb45b-83d7-4f23-bc38-c5e70d90cde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617324774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3617324774
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1383971527
Short name T426
Test name
Test status
Simulation time 12655931 ps
CPU time 0.77 seconds
Started Apr 04 12:55:44 PM PDT 24
Finished Apr 04 12:55:45 PM PDT 24
Peak memory 205604 kb
Host smart-229c08ac-eb9b-4c50-a2eb-01d78a81a065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383971527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1383971527
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2386118940
Short name T143
Test name
Test status
Simulation time 506673247 ps
CPU time 5.19 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:29 PM PDT 24
Peak memory 215252 kb
Host smart-9af1cbbe-e80f-4c1e-8fbb-3d833f30968c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386118940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
386118940
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2297671711
Short name T105
Test name
Test status
Simulation time 70106536 ps
CPU time 1.34 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:24 PM PDT 24
Peak memory 206968 kb
Host smart-b5f055cc-5f17-4b6a-9511-e074c1da4811
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297671711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2297671711
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2237075995
Short name T157
Test name
Test status
Simulation time 229679600 ps
CPU time 7.62 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:32 PM PDT 24
Peak memory 207216 kb
Host smart-a4af1172-bc8b-4905-b395-43b832a12fc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237075995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2237075995
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3434487555
Short name T770
Test name
Test status
Simulation time 753856776 ps
CPU time 11.3 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:34 PM PDT 24
Peak memory 215276 kb
Host smart-407d7878-89d0-4c00-8790-82e32870a4c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434487555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3434487555
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1886128335
Short name T152
Test name
Test status
Simulation time 486681908 ps
CPU time 3.59 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 216624 kb
Host smart-c21dfcc4-4c56-4c90-9479-3ec833886ce4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886128335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1886128335
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1751326551
Short name T865
Test name
Test status
Simulation time 40719621 ps
CPU time 1.28 seconds
Started Apr 04 02:46:20 PM PDT 24
Finished Apr 04 02:46:21 PM PDT 24
Peak memory 215264 kb
Host smart-c9ad641e-e712-4284-bcf5-09108c744b31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751326551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
751326551
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.296951933
Short name T774
Test name
Test status
Simulation time 15539495 ps
CPU time 0.68 seconds
Started Apr 04 02:46:12 PM PDT 24
Finished Apr 04 02:46:15 PM PDT 24
Peak memory 203736 kb
Host smart-8f71200e-c018-41b4-adcd-cc0492522796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296951933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.296951933
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4055510029
Short name T827
Test name
Test status
Simulation time 91312453 ps
CPU time 2 seconds
Started Apr 04 02:46:20 PM PDT 24
Finished Apr 04 02:46:23 PM PDT 24
Peak memory 215368 kb
Host smart-8f50320c-7a7d-48ac-b61d-661d843024f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055510029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4055510029
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2573012957
Short name T850
Test name
Test status
Simulation time 37373699 ps
CPU time 0.65 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 203684 kb
Host smart-ba16d438-57e1-4c0d-aaa0-40f8505ec910
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573012957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2573012957
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4277500219
Short name T170
Test name
Test status
Simulation time 272288954 ps
CPU time 1.91 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 207200 kb
Host smart-c9b37c6d-6a51-41aa-ab44-99a2e61a1308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277500219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4277500219
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1926019017
Short name T840
Test name
Test status
Simulation time 162991327 ps
CPU time 1.56 seconds
Started Apr 04 02:46:13 PM PDT 24
Finished Apr 04 02:46:16 PM PDT 24
Peak memory 215548 kb
Host smart-418866a0-0860-489d-8f7d-015df04f2b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926019017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
926019017
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3243197313
Short name T149
Test name
Test status
Simulation time 2009360191 ps
CPU time 14.66 seconds
Started Apr 04 02:46:11 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 215372 kb
Host smart-32ad0d07-9db8-45ca-a9d7-3b6838d2abbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243197313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3243197313
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1833443983
Short name T156
Test name
Test status
Simulation time 5966001184 ps
CPU time 20.98 seconds
Started Apr 04 02:46:20 PM PDT 24
Finished Apr 04 02:46:42 PM PDT 24
Peak memory 215384 kb
Host smart-c012ee32-ec36-40e7-a12f-2c2994f19bc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833443983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1833443983
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2411543263
Short name T866
Test name
Test status
Simulation time 2088172900 ps
CPU time 34.68 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 207240 kb
Host smart-342d943e-db9c-4fed-a01f-c26a23bece5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411543263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2411543263
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.45801603
Short name T108
Test name
Test status
Simulation time 97906123 ps
CPU time 1.47 seconds
Started Apr 04 02:46:27 PM PDT 24
Finished Apr 04 02:46:29 PM PDT 24
Peak memory 207116 kb
Host smart-6f66cac8-e360-4368-88df-dae1da35fb2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45801603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
hw_reset.45801603
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.534910742
Short name T151
Test name
Test status
Simulation time 866348432 ps
CPU time 2.76 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 217036 kb
Host smart-1d303478-d71a-4c13-8ec7-f8ad5c1ad10c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534910742 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.534910742
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3509457112
Short name T851
Test name
Test status
Simulation time 372389921 ps
CPU time 2.36 seconds
Started Apr 04 02:46:19 PM PDT 24
Finished Apr 04 02:46:22 PM PDT 24
Peak memory 215364 kb
Host smart-eb30a10b-e70b-475f-a8af-c1691811f20a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509457112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
509457112
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2856369197
Short name T759
Test name
Test status
Simulation time 16969122 ps
CPU time 0.76 seconds
Started Apr 04 02:46:27 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 203416 kb
Host smart-5a7f35d2-be46-42b9-9b74-0525aa97ad48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856369197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
856369197
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1785651032
Short name T161
Test name
Test status
Simulation time 262693184 ps
CPU time 1.65 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215336 kb
Host smart-204a1b87-91df-4ddf-a02e-a9a1e4c2b8f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785651032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1785651032
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.149436786
Short name T767
Test name
Test status
Simulation time 39676763 ps
CPU time 0.71 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:22 PM PDT 24
Peak memory 203744 kb
Host smart-0378fdd7-8bb8-46ce-b51a-44c6b0f8aef6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149436786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.149436786
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2428823678
Short name T799
Test name
Test status
Simulation time 124587488 ps
CPU time 3.7 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 215248 kb
Host smart-e2cbc16d-f2b9-4a49-aa6d-c971e5a07bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428823678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2428823678
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.577693675
Short name T830
Test name
Test status
Simulation time 81314177 ps
CPU time 2.5 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 216616 kb
Host smart-26eb7636-3b92-46cb-b0b9-877438617589
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577693675 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.577693675
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.477357972
Short name T159
Test name
Test status
Simulation time 92191481 ps
CPU time 2.56 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215440 kb
Host smart-9b88b243-851e-4ac4-a586-6354bf086237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477357972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.477357972
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.294481575
Short name T831
Test name
Test status
Simulation time 23957449 ps
CPU time 0.71 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:36 PM PDT 24
Peak memory 203412 kb
Host smart-bbff1193-4c93-4362-b356-973eb02b5df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294481575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.294481575
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.584714668
Short name T836
Test name
Test status
Simulation time 1181626729 ps
CPU time 2.86 seconds
Started Apr 04 02:46:39 PM PDT 24
Finished Apr 04 02:46:42 PM PDT 24
Peak memory 215388 kb
Host smart-fd3046bf-daa8-4120-8050-a3b600d8423b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584714668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.584714668
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.925659439
Short name T864
Test name
Test status
Simulation time 41373982 ps
CPU time 1.38 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 207172 kb
Host smart-321d1df4-6f96-4df4-87f2-9755ebde707b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925659439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.925659439
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.705290841
Short name T835
Test name
Test status
Simulation time 633118875 ps
CPU time 7.29 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:43 PM PDT 24
Peak memory 215536 kb
Host smart-2197a1b4-5da2-4d8e-8d13-3a683e97be96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705290841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.705290841
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2916679241
Short name T176
Test name
Test status
Simulation time 58257688 ps
CPU time 1.79 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 215420 kb
Host smart-e38c8eea-0da4-441a-bd2a-5b4933555bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916679241 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2916679241
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.522989428
Short name T165
Test name
Test status
Simulation time 191423716 ps
CPU time 1.33 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 215356 kb
Host smart-35208999-301a-4c7f-8169-c205a3cfcd14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522989428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.522989428
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.444900475
Short name T768
Test name
Test status
Simulation time 79390065 ps
CPU time 0.74 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:35 PM PDT 24
Peak memory 203404 kb
Host smart-76bb700d-1a64-4ab8-9384-86eb7eece7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444900475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.444900475
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2612253457
Short name T167
Test name
Test status
Simulation time 654067342 ps
CPU time 4.27 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:40 PM PDT 24
Peak memory 215168 kb
Host smart-9267af77-373f-4039-9b0f-8b7c67985efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612253457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2612253457
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3653755007
Short name T871
Test name
Test status
Simulation time 371118228 ps
CPU time 8.25 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:44 PM PDT 24
Peak memory 215276 kb
Host smart-a07a108b-ba81-44f4-b2c2-b52864a0e35d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653755007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3653755007
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2350775628
Short name T123
Test name
Test status
Simulation time 132667612 ps
CPU time 3.84 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 217508 kb
Host smart-75dde504-2701-43b2-9d85-0f34bc4305e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350775628 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2350775628
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3938924821
Short name T854
Test name
Test status
Simulation time 122462612 ps
CPU time 3.01 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:40 PM PDT 24
Peak memory 215320 kb
Host smart-58354aec-987f-4a6d-9c5e-3589fe25f6e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938924821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3938924821
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.720091975
Short name T837
Test name
Test status
Simulation time 22837422 ps
CPU time 0.73 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 203700 kb
Host smart-c1d8c9c3-974d-4124-86bc-8121ca2b1f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720091975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.720091975
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4063184394
Short name T839
Test name
Test status
Simulation time 108453107 ps
CPU time 2.99 seconds
Started Apr 04 02:46:33 PM PDT 24
Finished Apr 04 02:46:36 PM PDT 24
Peak memory 215348 kb
Host smart-ff3a2498-3570-4a24-adb1-0ff485e701d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063184394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4063184394
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2884254576
Short name T372
Test name
Test status
Simulation time 169290482 ps
CPU time 2.83 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215440 kb
Host smart-1d46815b-ff82-4d7a-a1d0-fcd2dca436e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884254576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2884254576
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.272071335
Short name T376
Test name
Test status
Simulation time 1112848703 ps
CPU time 23.76 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:58 PM PDT 24
Peak memory 215336 kb
Host smart-a1860d68-ad42-427d-b0b3-42bb79e3ab1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272071335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.272071335
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.787438615
Short name T124
Test name
Test status
Simulation time 188476290 ps
CPU time 2.47 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 216468 kb
Host smart-a9c69085-3cc1-4417-99f8-5001f647e43c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787438615 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.787438615
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3657726559
Short name T158
Test name
Test status
Simulation time 346117019 ps
CPU time 2.52 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215316 kb
Host smart-91749757-82b1-47e8-a96c-c9f5f37f1264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657726559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3657726559
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3058147482
Short name T857
Test name
Test status
Simulation time 30130602 ps
CPU time 0.73 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 203488 kb
Host smart-17b672a0-55da-4d88-ad88-523ca44c1361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058147482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3058147482
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.557432910
Short name T789
Test name
Test status
Simulation time 26413124 ps
CPU time 1.64 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 215404 kb
Host smart-eb1f56bd-39ef-4e19-a937-13ed99564400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557432910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.557432910
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2023356269
Short name T144
Test name
Test status
Simulation time 198341612 ps
CPU time 1.83 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 216652 kb
Host smart-1ac163d1-d728-4fd5-ba29-ae793d6357ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023356269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2023356269
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.652107701
Short name T801
Test name
Test status
Simulation time 4392112096 ps
CPU time 23.61 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:59 PM PDT 24
Peak memory 215544 kb
Host smart-31baa038-4d5c-4132-a007-5a8ea4d65686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652107701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.652107701
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2250507781
Short name T177
Test name
Test status
Simulation time 452701061 ps
CPU time 1.79 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:51 PM PDT 24
Peak memory 215436 kb
Host smart-25414776-fc01-44af-bb29-f82b7812c26c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250507781 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2250507781
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1947090083
Short name T162
Test name
Test status
Simulation time 99249955 ps
CPU time 2.92 seconds
Started Apr 04 02:46:48 PM PDT 24
Finished Apr 04 02:46:51 PM PDT 24
Peak memory 215412 kb
Host smart-932c7ff2-e1d5-40f2-84d5-ba6ddfeabc0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947090083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1947090083
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1629173855
Short name T784
Test name
Test status
Simulation time 20281346 ps
CPU time 0.7 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:50 PM PDT 24
Peak memory 203348 kb
Host smart-e8084838-3f92-47f8-93fc-e10db20284d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629173855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1629173855
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1128183581
Short name T171
Test name
Test status
Simulation time 2542297429 ps
CPU time 4.3 seconds
Started Apr 04 02:46:56 PM PDT 24
Finished Apr 04 02:47:00 PM PDT 24
Peak memory 215452 kb
Host smart-40e740d9-1972-4ffa-ba5f-e74f1ee03428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128183581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1128183581
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.529533692
Short name T40
Test name
Test status
Simulation time 376540930 ps
CPU time 19.51 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 215248 kb
Host smart-f38d34e3-cecc-4acd-a798-762c0217d984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529533692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.529533692
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.506078777
Short name T848
Test name
Test status
Simulation time 46365417 ps
CPU time 1.77 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215464 kb
Host smart-59edd860-1e4f-4170-be0e-8d598220af0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506078777 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.506078777
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2397871090
Short name T817
Test name
Test status
Simulation time 1132753759 ps
CPU time 1.97 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 215400 kb
Host smart-e4e2fef1-8e62-4ab7-8f58-101bedbaedd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397871090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2397871090
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3381010753
Short name T856
Test name
Test status
Simulation time 89815206 ps
CPU time 0.69 seconds
Started Apr 04 02:46:48 PM PDT 24
Finished Apr 04 02:46:48 PM PDT 24
Peak memory 203436 kb
Host smart-005c200b-1250-45d9-9a03-07c0d30bea59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381010753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3381010753
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2063480210
Short name T845
Test name
Test status
Simulation time 202203085 ps
CPU time 2.9 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 215144 kb
Host smart-6b5ec221-7a17-4ae6-80a0-d8a07bce867d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063480210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2063480210
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2717766109
Short name T859
Test name
Test status
Simulation time 124651861 ps
CPU time 3.48 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215460 kb
Host smart-3fa91230-3d94-4819-a3b5-a21b51d7732e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717766109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2717766109
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2009453591
Short name T870
Test name
Test status
Simulation time 492596997 ps
CPU time 3.61 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 215592 kb
Host smart-d244c0c1-5d0f-44b1-9b09-926ae8000835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009453591 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2009453591
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2925166178
Short name T813
Test name
Test status
Simulation time 39095240 ps
CPU time 2.41 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215340 kb
Host smart-e0951c37-7338-42aa-afd0-09f0a065d814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925166178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2925166178
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.857444926
Short name T869
Test name
Test status
Simulation time 63881741 ps
CPU time 0.71 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203428 kb
Host smart-bf5db9d6-cdca-407a-9a93-b351f0245e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857444926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.857444926
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2734927437
Short name T175
Test name
Test status
Simulation time 148143553 ps
CPU time 2.03 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 215292 kb
Host smart-0b52e57a-8367-4483-b5c3-a0a38015ca20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734927437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2734927437
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3522512613
Short name T148
Test name
Test status
Simulation time 136117864 ps
CPU time 1.65 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215440 kb
Host smart-f68db980-34cd-434d-bd1d-8deb7a3d1b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522512613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3522512613
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.60620472
Short name T867
Test name
Test status
Simulation time 210161875 ps
CPU time 12.7 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:47:03 PM PDT 24
Peak memory 215296 kb
Host smart-6f0dbab5-b392-41a1-99a6-280e39c5de64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60620472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.60620472
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3150347556
Short name T804
Test name
Test status
Simulation time 66509281 ps
CPU time 1.82 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215480 kb
Host smart-a813f93b-5e7b-4379-8d21-ec03a68d9608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150347556 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3150347556
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.126600496
Short name T775
Test name
Test status
Simulation time 166489342 ps
CPU time 0.72 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:51 PM PDT 24
Peak memory 203640 kb
Host smart-5990c333-a2e1-4c0c-95f0-2ffe960f1456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126600496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.126600496
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3607708326
Short name T787
Test name
Test status
Simulation time 433657219 ps
CPU time 2.94 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:56 PM PDT 24
Peak memory 215328 kb
Host smart-05f3e857-ebaf-4b28-bc07-88b6b3303ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607708326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3607708326
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2008867595
Short name T147
Test name
Test status
Simulation time 170647727 ps
CPU time 4.15 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 216412 kb
Host smart-d3e4d6b2-b128-4d05-8baa-c1819e1824bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008867595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2008867595
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2827540678
Short name T783
Test name
Test status
Simulation time 287923841 ps
CPU time 19.35 seconds
Started Apr 04 02:46:49 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 215300 kb
Host smart-ef6bcf39-0098-4de7-84fb-b2010cfa42ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827540678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2827540678
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3968388372
Short name T788
Test name
Test status
Simulation time 80597728 ps
CPU time 1.82 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 215372 kb
Host smart-eba61906-7db2-4fdf-87be-4e1eb38c7da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968388372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3968388372
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1245349495
Short name T818
Test name
Test status
Simulation time 229638589 ps
CPU time 1.9 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 207120 kb
Host smart-5bdb115b-32f6-407e-8e23-3409f9834106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245349495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1245349495
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.358809620
Short name T853
Test name
Test status
Simulation time 117428972 ps
CPU time 0.73 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:54 PM PDT 24
Peak memory 203468 kb
Host smart-42541df1-beac-4f3a-9a04-9ee8cba20c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358809620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.358809620
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4086508733
Short name T828
Test name
Test status
Simulation time 237543767 ps
CPU time 3.95 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:57 PM PDT 24
Peak memory 215400 kb
Host smart-587b1c51-7c37-4c2a-b2e6-51c8b1a4d14b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086508733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4086508733
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3726261026
Short name T810
Test name
Test status
Simulation time 198994154 ps
CPU time 2.14 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 215444 kb
Host smart-35c19b77-f016-4923-8254-c1591a593952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726261026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3726261026
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3011994951
Short name T150
Test name
Test status
Simulation time 328210592 ps
CPU time 2.68 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 216828 kb
Host smart-be748df6-40b4-4726-a8b2-03fa8ffff1be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011994951 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3011994951
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3929486233
Short name T164
Test name
Test status
Simulation time 86595866 ps
CPU time 1.4 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 207220 kb
Host smart-4b144cca-3c3b-4acc-bb68-defba479ca18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929486233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3929486233
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3482018994
Short name T806
Test name
Test status
Simulation time 13191552 ps
CPU time 0.75 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203384 kb
Host smart-452c899e-5244-4ecf-8508-9598af54072a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482018994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3482018994
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4033932703
Short name T834
Test name
Test status
Simulation time 568809708 ps
CPU time 2.85 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:54 PM PDT 24
Peak memory 215324 kb
Host smart-fb4e0f47-0696-41d2-9acf-c17d01240b31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033932703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4033932703
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3852126105
Short name T142
Test name
Test status
Simulation time 27652531 ps
CPU time 1.82 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:54 PM PDT 24
Peak memory 215476 kb
Host smart-97d968e5-254b-43d4-87e4-31d120b11b10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852126105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3852126105
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2625151235
Short name T178
Test name
Test status
Simulation time 13325968896 ps
CPU time 15.18 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 215424 kb
Host smart-bc1d9c3a-a072-4851-b599-7059a1ec93ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625151235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2625151235
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.923580452
Short name T823
Test name
Test status
Simulation time 309284101 ps
CPU time 8.5 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:30 PM PDT 24
Peak memory 215388 kb
Host smart-fb1aafb9-fcd9-4e75-8882-fc9861ef523a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923580452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.923580452
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.47680588
Short name T829
Test name
Test status
Simulation time 5060394664 ps
CPU time 25.59 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:49 PM PDT 24
Peak memory 207152 kb
Host smart-02d8a479-2006-4de4-9d76-18cad056af69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47680588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.47680588
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1646823474
Short name T863
Test name
Test status
Simulation time 148741966 ps
CPU time 1.45 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:24 PM PDT 24
Peak memory 207096 kb
Host smart-26fffd29-e7f1-4efe-a8f2-9be1c085fcaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646823474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1646823474
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.643715526
Short name T849
Test name
Test status
Simulation time 1395316865 ps
CPU time 3.53 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 216612 kb
Host smart-9e3c57a5-e23e-454e-bd93-9b7e8e148e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643715526 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.643715526
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2537100572
Short name T155
Test name
Test status
Simulation time 109306524 ps
CPU time 1.32 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:23 PM PDT 24
Peak memory 207032 kb
Host smart-3a6b42f4-ce11-4b10-92b2-afaf8a910731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537100572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
537100572
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1956879983
Short name T868
Test name
Test status
Simulation time 18484213 ps
CPU time 0.69 seconds
Started Apr 04 02:46:19 PM PDT 24
Finished Apr 04 02:46:20 PM PDT 24
Peak memory 203424 kb
Host smart-e57b34d0-4393-4ed2-9b30-075c8218cb81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956879983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
956879983
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.355831941
Short name T795
Test name
Test status
Simulation time 31476072 ps
CPU time 1.35 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:23 PM PDT 24
Peak memory 215300 kb
Host smart-9e4138ac-34ca-4ff7-97d1-227c1729edfb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355831941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.355831941
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2559658115
Short name T844
Test name
Test status
Simulation time 11838015 ps
CPU time 0.66 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:23 PM PDT 24
Peak memory 203776 kb
Host smart-a161889d-577d-49f2-8ee7-3aa6c255670f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559658115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2559658115
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1561808027
Short name T38
Test name
Test status
Simulation time 470592124 ps
CPU time 2.78 seconds
Started Apr 04 02:46:27 PM PDT 24
Finished Apr 04 02:46:30 PM PDT 24
Peak memory 215324 kb
Host smart-d2454c07-3d10-4e20-a9f4-17ef2d267937
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561808027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1561808027
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1250508048
Short name T146
Test name
Test status
Simulation time 288392141 ps
CPU time 4.31 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:28 PM PDT 24
Peak memory 215476 kb
Host smart-d9379800-0320-469a-8810-b2dd3d275636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250508048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
250508048
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.178801591
Short name T833
Test name
Test status
Simulation time 26854705 ps
CPU time 0.7 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203456 kb
Host smart-af7963bb-328e-46f3-b4db-3411fa3f9ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178801591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.178801591
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3590852021
Short name T786
Test name
Test status
Simulation time 35861518 ps
CPU time 0.73 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203748 kb
Host smart-4e384fbb-271c-4009-9a6e-380496544fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590852021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3590852021
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3384710357
Short name T772
Test name
Test status
Simulation time 24481807 ps
CPU time 0.72 seconds
Started Apr 04 02:46:50 PM PDT 24
Finished Apr 04 02:46:51 PM PDT 24
Peak memory 203392 kb
Host smart-c01881fc-1fa3-462d-8900-93acaf568d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384710357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3384710357
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3370379142
Short name T807
Test name
Test status
Simulation time 15129793 ps
CPU time 0.73 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203384 kb
Host smart-ec1ccf38-2f3f-4392-816a-bea70eb2c8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370379142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3370379142
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.354967926
Short name T182
Test name
Test status
Simulation time 27822698 ps
CPU time 0.72 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203384 kb
Host smart-257325a7-461b-418c-ba12-8a29113350ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354967926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.354967926
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3951840272
Short name T777
Test name
Test status
Simulation time 14544962 ps
CPU time 0.79 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203432 kb
Host smart-b7f8b3e4-fdd6-415c-8b66-033a02d6cf05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951840272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3951840272
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2088081551
Short name T785
Test name
Test status
Simulation time 28705990 ps
CPU time 0.75 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203456 kb
Host smart-68b6b627-d223-4b2c-bb65-9aa2a6c6fecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088081551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2088081551
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3610786033
Short name T809
Test name
Test status
Simulation time 12570565 ps
CPU time 0.74 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203448 kb
Host smart-de652f18-196b-406f-ba98-e5777d890c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610786033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3610786033
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4183347823
Short name T793
Test name
Test status
Simulation time 15269964 ps
CPU time 0.75 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203452 kb
Host smart-323ef4da-1ecd-47dd-a12f-68b6fa8a373a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183347823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4183347823
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2683542145
Short name T762
Test name
Test status
Simulation time 101334980 ps
CPU time 0.66 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203396 kb
Host smart-51d0bcb5-4aea-45f0-9ff2-fdec0609c946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683542145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2683542145
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3762383780
Short name T812
Test name
Test status
Simulation time 1676078266 ps
CPU time 17.64 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:41 PM PDT 24
Peak memory 207168 kb
Host smart-2b19f8c9-df11-4d3c-b00b-d4f1df427dd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762383780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3762383780
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3976651152
Short name T163
Test name
Test status
Simulation time 187815239 ps
CPU time 11.87 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:36 PM PDT 24
Peak memory 206868 kb
Host smart-69171739-1564-418e-853a-ddb41131e740
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976651152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3976651152
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2414968096
Short name T106
Test name
Test status
Simulation time 57730765 ps
CPU time 0.93 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:24 PM PDT 24
Peak memory 206868 kb
Host smart-ded4418d-a841-4ade-a967-7b4ea601c5ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414968096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2414968096
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2487586065
Short name T782
Test name
Test status
Simulation time 28493227 ps
CPU time 1.63 seconds
Started Apr 04 02:46:20 PM PDT 24
Finished Apr 04 02:46:22 PM PDT 24
Peak memory 216408 kb
Host smart-939315e1-e2b5-4564-83c2-a95906731673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487586065 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2487586065
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3759444831
Short name T826
Test name
Test status
Simulation time 343688598 ps
CPU time 2.54 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:24 PM PDT 24
Peak memory 215332 kb
Host smart-20b6ec80-fcc3-48be-bff0-0c09527c1d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759444831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
759444831
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2852223644
Short name T794
Test name
Test status
Simulation time 12338994 ps
CPU time 0.72 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:22 PM PDT 24
Peak memory 203360 kb
Host smart-d3e9454f-19ca-4ced-9024-7b1ea19efaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852223644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
852223644
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1644685938
Short name T861
Test name
Test status
Simulation time 155072501 ps
CPU time 1.33 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215408 kb
Host smart-91d52fab-42ae-4c24-9060-cc2c26f550cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644685938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1644685938
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.83141489
Short name T825
Test name
Test status
Simulation time 16992937 ps
CPU time 0.68 seconds
Started Apr 04 02:46:27 PM PDT 24
Finished Apr 04 02:46:28 PM PDT 24
Peak memory 203444 kb
Host smart-84cc005a-9413-49f7-bbcb-d772b6c5d5d8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83141489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_
walk.83141489
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2588044015
Short name T803
Test name
Test status
Simulation time 99393231 ps
CPU time 1.78 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215372 kb
Host smart-62e61836-e7f3-45d0-b0c1-1355e2e11454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588044015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2588044015
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1242265308
Short name T858
Test name
Test status
Simulation time 224876322 ps
CPU time 1.95 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215368 kb
Host smart-ebc689f9-487d-4d0d-ba20-b943c6ec2211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242265308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
242265308
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2488754242
Short name T374
Test name
Test status
Simulation time 712468295 ps
CPU time 12.51 seconds
Started Apr 04 02:46:25 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 215384 kb
Host smart-9462acd8-27c6-4d35-9512-66d70c0d221b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488754242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2488754242
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3539377522
Short name T820
Test name
Test status
Simulation time 40831299 ps
CPU time 0.74 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203740 kb
Host smart-ae4ef0be-bcf3-4e39-b583-5e21aca70903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539377522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3539377522
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1072319049
Short name T763
Test name
Test status
Simulation time 12645924 ps
CPU time 0.74 seconds
Started Apr 04 02:46:54 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 203420 kb
Host smart-978fc486-5165-4639-a3ec-470aa31929cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072319049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1072319049
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.889741895
Short name T790
Test name
Test status
Simulation time 52464859 ps
CPU time 0.73 seconds
Started Apr 04 02:46:51 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203428 kb
Host smart-927b0b03-ba55-47d2-94f2-942bb96f1a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889741895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.889741895
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3386382331
Short name T872
Test name
Test status
Simulation time 15386278 ps
CPU time 0.73 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203756 kb
Host smart-9ff372a2-8de6-4846-8b02-b5fe36010dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386382331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3386382331
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.991089239
Short name T862
Test name
Test status
Simulation time 26776122 ps
CPU time 0.73 seconds
Started Apr 04 02:46:54 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 203424 kb
Host smart-cc76fb1b-5de4-4254-9780-7e5fba886092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991089239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.991089239
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2516788986
Short name T800
Test name
Test status
Simulation time 15044114 ps
CPU time 0.73 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:52 PM PDT 24
Peak memory 203376 kb
Host smart-ffaebe46-d1e1-4133-898a-ed49f1552365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516788986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2516788986
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2531077099
Short name T776
Test name
Test status
Simulation time 45392181 ps
CPU time 0.73 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203496 kb
Host smart-84ebc329-ae03-46f0-a416-68f88f1e6989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531077099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2531077099
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2458883508
Short name T764
Test name
Test status
Simulation time 26401946 ps
CPU time 0.79 seconds
Started Apr 04 02:46:53 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203740 kb
Host smart-37d269c2-9b25-4337-997b-04b29b1c7716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458883508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2458883508
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2906920764
Short name T814
Test name
Test status
Simulation time 14494635 ps
CPU time 0.76 seconds
Started Apr 04 02:46:54 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 203412 kb
Host smart-9026d738-6289-4c70-9e4a-e8041bd8eba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906920764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2906920764
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3185873420
Short name T841
Test name
Test status
Simulation time 17280084 ps
CPU time 0.76 seconds
Started Apr 04 02:46:52 PM PDT 24
Finished Apr 04 02:46:53 PM PDT 24
Peak memory 203444 kb
Host smart-e2e276dc-c62c-4e79-87dc-ce95c696962f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185873420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3185873420
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.550007846
Short name T154
Test name
Test status
Simulation time 858983044 ps
CPU time 13.61 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:35 PM PDT 24
Peak memory 215400 kb
Host smart-00160e64-1307-4ebc-97bf-99d61b571979
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550007846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.550007846
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2660151936
Short name T773
Test name
Test status
Simulation time 3612766351 ps
CPU time 37.42 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:47:00 PM PDT 24
Peak memory 207280 kb
Host smart-f83d15ce-e6ac-4025-a084-6e54379d48a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660151936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2660151936
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1570203189
Short name T107
Test name
Test status
Simulation time 49913585 ps
CPU time 0.9 seconds
Started Apr 04 02:46:25 PM PDT 24
Finished Apr 04 02:46:26 PM PDT 24
Peak memory 206748 kb
Host smart-aa287266-4993-4585-a36b-0c91d493d9b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570203189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1570203189
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2233900387
Short name T780
Test name
Test status
Simulation time 59429258 ps
CPU time 2.71 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:26 PM PDT 24
Peak memory 216820 kb
Host smart-1001f037-5221-4795-9688-d87ded75b416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233900387 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2233900387
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4194304675
Short name T819
Test name
Test status
Simulation time 971430736 ps
CPU time 2.08 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215400 kb
Host smart-d40b73da-0d99-4199-bb1c-af644a5e40a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194304675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
194304675
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3297926890
Short name T832
Test name
Test status
Simulation time 63345993 ps
CPU time 0.67 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 203640 kb
Host smart-1eae05fa-d359-494a-af5b-cd829cc2bbc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297926890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
297926890
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2767706109
Short name T816
Test name
Test status
Simulation time 58555427 ps
CPU time 1.8 seconds
Started Apr 04 02:46:25 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 215408 kb
Host smart-c5ebf722-4c7b-4054-924f-874afa5ba86d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767706109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2767706109
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1936176658
Short name T852
Test name
Test status
Simulation time 47505829 ps
CPU time 0.66 seconds
Started Apr 04 02:46:27 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 203776 kb
Host smart-94219a45-0108-4ebb-b258-7636ced4166f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936176658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1936176658
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1452810635
Short name T797
Test name
Test status
Simulation time 479175655 ps
CPU time 1.95 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:24 PM PDT 24
Peak memory 207216 kb
Host smart-3190a4e7-0e6e-4919-93fe-7d9e890aeea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452810635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1452810635
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1807527237
Short name T141
Test name
Test status
Simulation time 87841790 ps
CPU time 2.64 seconds
Started Apr 04 02:46:19 PM PDT 24
Finished Apr 04 02:46:22 PM PDT 24
Peak memory 215408 kb
Host smart-a14ffc9c-4b78-4564-bbad-cc401131b0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807527237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
807527237
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.469015252
Short name T125
Test name
Test status
Simulation time 1105316172 ps
CPU time 13.23 seconds
Started Apr 04 02:46:22 PM PDT 24
Finished Apr 04 02:46:35 PM PDT 24
Peak memory 215560 kb
Host smart-bba590b0-3b2a-4026-936f-f13b3b736b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469015252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.469015252
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1102620104
Short name T796
Test name
Test status
Simulation time 47583973 ps
CPU time 0.76 seconds
Started Apr 04 02:46:54 PM PDT 24
Finished Apr 04 02:46:55 PM PDT 24
Peak memory 203472 kb
Host smart-372945c1-4d97-45be-b9ea-d48761101809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102620104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1102620104
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3057097084
Short name T761
Test name
Test status
Simulation time 14440545 ps
CPU time 0.76 seconds
Started Apr 04 02:47:08 PM PDT 24
Finished Apr 04 02:47:09 PM PDT 24
Peak memory 203360 kb
Host smart-fd70a590-0426-437c-9074-749f829d0946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057097084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3057097084
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1466018453
Short name T847
Test name
Test status
Simulation time 12218048 ps
CPU time 0.68 seconds
Started Apr 04 02:47:07 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 203744 kb
Host smart-812712e5-942e-4a72-96e4-2b701f46e1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466018453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1466018453
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.922979889
Short name T779
Test name
Test status
Simulation time 18866605 ps
CPU time 0.71 seconds
Started Apr 04 02:47:04 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 203376 kb
Host smart-a8687412-c128-49e0-9711-b592a215db3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922979889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.922979889
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.339840860
Short name T760
Test name
Test status
Simulation time 14557621 ps
CPU time 0.77 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 203436 kb
Host smart-8af88f53-2ac7-42f7-bce5-02f0e7f5313c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339840860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.339840860
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2833366258
Short name T769
Test name
Test status
Simulation time 50630070 ps
CPU time 0.72 seconds
Started Apr 04 02:47:07 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 203452 kb
Host smart-077aa44e-5896-4ec7-845d-7a5edccfc37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833366258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2833366258
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3192092365
Short name T838
Test name
Test status
Simulation time 39708485 ps
CPU time 0.7 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 203332 kb
Host smart-6effe699-d891-494c-bc04-83ac3d40ee27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192092365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3192092365
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3152076747
Short name T791
Test name
Test status
Simulation time 18915591 ps
CPU time 0.74 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 203380 kb
Host smart-745d672c-980e-459b-b90c-8010515c2dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152076747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3152076747
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.268388312
Short name T781
Test name
Test status
Simulation time 11579949 ps
CPU time 0.74 seconds
Started Apr 04 02:47:02 PM PDT 24
Finished Apr 04 02:47:03 PM PDT 24
Peak memory 203656 kb
Host smart-3b637b60-e88f-4dff-8fed-db2aa5017ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268388312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.268388312
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3938805622
Short name T771
Test name
Test status
Simulation time 34903074 ps
CPU time 0.76 seconds
Started Apr 04 02:47:02 PM PDT 24
Finished Apr 04 02:47:03 PM PDT 24
Peak memory 203444 kb
Host smart-2f1663a8-da6a-42ac-aa3a-bb1fe5a2fc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938805622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3938805622
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3273041620
Short name T180
Test name
Test status
Simulation time 102744850 ps
CPU time 2.81 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 216900 kb
Host smart-feee9286-882f-462f-b824-311dda79b216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273041620 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3273041620
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.121924266
Short name T815
Test name
Test status
Simulation time 374078128 ps
CPU time 2.36 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 215392 kb
Host smart-67d9868b-1af1-42f6-b7e0-de1e167e0650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121924266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.121924266
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.168060118
Short name T846
Test name
Test status
Simulation time 15508012 ps
CPU time 0.75 seconds
Started Apr 04 02:46:24 PM PDT 24
Finished Apr 04 02:46:25 PM PDT 24
Peak memory 203424 kb
Host smart-c6e0cb34-9252-4ebd-8cea-cf4834513df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168060118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.168060118
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1465366749
Short name T166
Test name
Test status
Simulation time 1340084214 ps
CPU time 4.4 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:40 PM PDT 24
Peak memory 215320 kb
Host smart-ac316e52-e7c7-4c48-824b-d0df1695b581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465366749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1465366749
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2404231741
Short name T822
Test name
Test status
Simulation time 348129822 ps
CPU time 4.84 seconds
Started Apr 04 02:46:21 PM PDT 24
Finished Apr 04 02:46:27 PM PDT 24
Peak memory 215484 kb
Host smart-2c75edda-98b8-40cd-8860-42bd5504774a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404231741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
404231741
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1241048331
Short name T843
Test name
Test status
Simulation time 1760718969 ps
CPU time 7.8 seconds
Started Apr 04 02:46:23 PM PDT 24
Finished Apr 04 02:46:31 PM PDT 24
Peak memory 215792 kb
Host smart-49a497a4-a6a8-487e-b5f4-80fd5c875387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241048331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1241048331
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.460897596
Short name T798
Test name
Test status
Simulation time 195988729 ps
CPU time 1.89 seconds
Started Apr 04 02:46:39 PM PDT 24
Finished Apr 04 02:46:41 PM PDT 24
Peak memory 215472 kb
Host smart-911c575b-1398-4a49-8ac9-56511998c203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460897596 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.460897596
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2307145504
Short name T160
Test name
Test status
Simulation time 21052691 ps
CPU time 1.32 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 207104 kb
Host smart-c3e42636-dd4a-4609-bbc7-e358ea85f33f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307145504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
307145504
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2804400029
Short name T766
Test name
Test status
Simulation time 33017777 ps
CPU time 0.73 seconds
Started Apr 04 02:46:41 PM PDT 24
Finished Apr 04 02:46:42 PM PDT 24
Peak memory 203428 kb
Host smart-d0af58f5-b048-44a9-b9a1-4a9dd2040253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804400029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
804400029
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3812732868
Short name T168
Test name
Test status
Simulation time 126437008 ps
CPU time 4.07 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:41 PM PDT 24
Peak memory 215472 kb
Host smart-5360fffe-1ff2-426a-b4a2-d0569200c92c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812732868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3812732868
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1743647703
Short name T860
Test name
Test status
Simulation time 129341185 ps
CPU time 3.89 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215580 kb
Host smart-a95fb85c-84e1-498c-af46-aa39f3e415ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743647703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
743647703
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.356397812
Short name T377
Test name
Test status
Simulation time 2284762405 ps
CPU time 6.79 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:41 PM PDT 24
Peak memory 215452 kb
Host smart-00e8af69-9882-4d2f-a4ad-bf82d1640f84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356397812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.356397812
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1528129456
Short name T792
Test name
Test status
Simulation time 291094742 ps
CPU time 3.64 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 216948 kb
Host smart-71957d4a-6225-41ee-a14b-bfd5c1afbbd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528129456 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1528129456
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1099848323
Short name T821
Test name
Test status
Simulation time 110206426 ps
CPU time 1.88 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 207152 kb
Host smart-6d3b22de-3c68-4c56-8f8e-90241c7d51d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099848323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
099848323
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.530696488
Short name T758
Test name
Test status
Simulation time 42657266 ps
CPU time 0.72 seconds
Started Apr 04 02:46:45 PM PDT 24
Finished Apr 04 02:46:45 PM PDT 24
Peak memory 203412 kb
Host smart-d968e04a-ddf6-44c0-b29b-b44a6f7097c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530696488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.530696488
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3318621960
Short name T181
Test name
Test status
Simulation time 114930419 ps
CPU time 2.73 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:40 PM PDT 24
Peak memory 215412 kb
Host smart-6423f65b-02e2-4412-a047-13773ff67ce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318621960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3318621960
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3511480793
Short name T811
Test name
Test status
Simulation time 117817625 ps
CPU time 3.3 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 215372 kb
Host smart-31e65c39-34e6-421a-9c04-d23ab3e3713c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511480793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
511480793
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.108315217
Short name T379
Test name
Test status
Simulation time 107580157 ps
CPU time 6.56 seconds
Started Apr 04 02:46:38 PM PDT 24
Finished Apr 04 02:46:45 PM PDT 24
Peak memory 215368 kb
Host smart-dbaad9d9-be58-46b0-97d3-0c078f4b5fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108315217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.108315217
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3876729587
Short name T778
Test name
Test status
Simulation time 45627091 ps
CPU time 2.58 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:40 PM PDT 24
Peak memory 216392 kb
Host smart-9654ca8f-21f6-4619-9ead-9025523de444
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876729587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3876729587
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3376566527
Short name T805
Test name
Test status
Simulation time 197268462 ps
CPU time 2.04 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 207220 kb
Host smart-0ff09192-9174-4d4f-8318-bb513be133a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376566527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
376566527
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3497072678
Short name T855
Test name
Test status
Simulation time 15110487 ps
CPU time 0.74 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:36 PM PDT 24
Peak memory 203396 kb
Host smart-2d07671e-c040-450b-acea-260420b9d2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497072678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
497072678
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1472466934
Short name T169
Test name
Test status
Simulation time 48232996 ps
CPU time 2.85 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 215312 kb
Host smart-3697d434-b581-4aa7-b733-16d8a25f70ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472466934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1472466934
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2874587997
Short name T140
Test name
Test status
Simulation time 30585740 ps
CPU time 2.01 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:36 PM PDT 24
Peak memory 215504 kb
Host smart-305429ce-fbff-454f-a776-13abfa69d29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874587997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
874587997
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1036650514
Short name T824
Test name
Test status
Simulation time 310444058 ps
CPU time 18.8 seconds
Started Apr 04 02:46:38 PM PDT 24
Finished Apr 04 02:46:57 PM PDT 24
Peak memory 215372 kb
Host smart-3f70b744-911b-4dd1-b996-1633e489a2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036650514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1036650514
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1707669655
Short name T808
Test name
Test status
Simulation time 43863590 ps
CPU time 1.61 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 215484 kb
Host smart-b57783cb-6993-4a12-a79c-46fa3b4e2677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707669655 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1707669655
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3128123698
Short name T802
Test name
Test status
Simulation time 127296955 ps
CPU time 1.96 seconds
Started Apr 04 02:46:35 PM PDT 24
Finished Apr 04 02:46:37 PM PDT 24
Peak memory 215372 kb
Host smart-03c617b5-6518-4d43-b35c-88e42d1abe67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128123698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
128123698
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1188237251
Short name T765
Test name
Test status
Simulation time 45103118 ps
CPU time 0.78 seconds
Started Apr 04 02:46:37 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 203464 kb
Host smart-bd76c5b2-079d-48ce-ae71-f55c92b8999f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188237251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
188237251
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.219374106
Short name T842
Test name
Test status
Simulation time 31297293 ps
CPU time 1.8 seconds
Started Apr 04 02:46:36 PM PDT 24
Finished Apr 04 02:46:38 PM PDT 24
Peak memory 215164 kb
Host smart-bd25a937-014d-4f86-a35f-ac0bc07f2fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219374106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.219374106
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.516071926
Short name T129
Test name
Test status
Simulation time 625197036 ps
CPU time 3.99 seconds
Started Apr 04 02:46:34 PM PDT 24
Finished Apr 04 02:46:39 PM PDT 24
Peak memory 215476 kb
Host smart-32c4eea9-adf0-4511-9c90-7602b4c0d855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516071926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.516071926
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3549712658
Short name T378
Test name
Test status
Simulation time 1350981928 ps
CPU time 14.7 seconds
Started Apr 04 02:46:41 PM PDT 24
Finished Apr 04 02:46:56 PM PDT 24
Peak memory 221384 kb
Host smart-a3dc556d-1397-4d51-aa2b-3141b48b9879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549712658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3549712658
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3593908474
Short name T509
Test name
Test status
Simulation time 34218201 ps
CPU time 0.73 seconds
Started Apr 04 12:56:02 PM PDT 24
Finished Apr 04 12:56:03 PM PDT 24
Peak memory 204764 kb
Host smart-017f3916-8655-44df-80d1-d4eb6cebe982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593908474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
593908474
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3172082483
Short name T594
Test name
Test status
Simulation time 8295518034 ps
CPU time 13.98 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:56:05 PM PDT 24
Peak memory 218920 kb
Host smart-7aca450f-17c9-4410-b4bf-a02af7fa3761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172082483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3172082483
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4105117539
Short name T234
Test name
Test status
Simulation time 2520243871 ps
CPU time 35.67 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:56:27 PM PDT 24
Peak memory 232300 kb
Host smart-886893c0-a721-4767-a719-d877d200eba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105117539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4105117539
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3280043670
Short name T723
Test name
Test status
Simulation time 86613174 ps
CPU time 1.12 seconds
Started Apr 04 12:55:44 PM PDT 24
Finished Apr 04 12:55:46 PM PDT 24
Peak memory 216968 kb
Host smart-565378bc-ba0b-4c6b-8408-fe3e93574bce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280043670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3280043670
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.406389308
Short name T295
Test name
Test status
Simulation time 63078085071 ps
CPU time 37.9 seconds
Started Apr 04 12:55:50 PM PDT 24
Finished Apr 04 12:56:28 PM PDT 24
Peak memory 249856 kb
Host smart-73e16aa1-dad8-494b-b658-9de572086bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406389308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
406389308
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.398614437
Short name T700
Test name
Test status
Simulation time 567724110 ps
CPU time 8.39 seconds
Started Apr 04 12:56:00 PM PDT 24
Finished Apr 04 12:56:09 PM PDT 24
Peak memory 221856 kb
Host smart-c59790dc-b848-4f7e-ab62-04469192666e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398614437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.398614437
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2994207814
Short name T696
Test name
Test status
Simulation time 2886965592 ps
CPU time 8.27 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:56:00 PM PDT 24
Peak memory 216592 kb
Host smart-93c8eba6-9d06-495f-ad34-6e4b046247d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994207814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2994207814
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2887622352
Short name T404
Test name
Test status
Simulation time 286498744 ps
CPU time 5.11 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:55:56 PM PDT 24
Peak memory 216568 kb
Host smart-19877757-8fc0-42ed-a30b-331028f50063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887622352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2887622352
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3399079086
Short name T546
Test name
Test status
Simulation time 60879422 ps
CPU time 0.81 seconds
Started Apr 04 12:55:52 PM PDT 24
Finished Apr 04 12:55:54 PM PDT 24
Peak memory 205824 kb
Host smart-7bfac4ca-3b76-4356-8e2c-c1a3fa3fe221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399079086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3399079086
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.194438563
Short name T252
Test name
Test status
Simulation time 103159995 ps
CPU time 2.47 seconds
Started Apr 04 12:55:51 PM PDT 24
Finished Apr 04 12:55:54 PM PDT 24
Peak memory 222036 kb
Host smart-e79abeca-0122-412d-82f4-5fe8d702a1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194438563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.194438563
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1571176704
Short name T654
Test name
Test status
Simulation time 18068660 ps
CPU time 0.7 seconds
Started Apr 04 12:56:33 PM PDT 24
Finished Apr 04 12:56:33 PM PDT 24
Peak memory 205380 kb
Host smart-c92f00c8-4920-4aed-bd4e-75855ba4c394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571176704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
571176704
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3395467266
Short name T662
Test name
Test status
Simulation time 34715594 ps
CPU time 0.77 seconds
Started Apr 04 12:56:10 PM PDT 24
Finished Apr 04 12:56:11 PM PDT 24
Peak memory 205512 kb
Host smart-f25ad605-4103-406e-ae8b-3b1c94a1c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395467266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3395467266
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1236375661
Short name T137
Test name
Test status
Simulation time 96330355 ps
CPU time 2.95 seconds
Started Apr 04 12:56:13 PM PDT 24
Finished Apr 04 12:56:16 PM PDT 24
Peak memory 222884 kb
Host smart-87c97796-3d22-4866-9336-7b3ff815cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236375661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1236375661
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1494770648
Short name T256
Test name
Test status
Simulation time 15964577111 ps
CPU time 11.63 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:56:22 PM PDT 24
Peak memory 224836 kb
Host smart-d29c3756-8f0d-462f-b24d-ed0cf544beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494770648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1494770648
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.2362364916
Short name T560
Test name
Test status
Simulation time 47118273 ps
CPU time 0.74 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:56:12 PM PDT 24
Peak memory 216316 kb
Host smart-a16a1459-d25c-4073-909f-33106cddfb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362364916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.2362364916
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2310698140
Short name T753
Test name
Test status
Simulation time 3195426835 ps
CPU time 18.05 seconds
Started Apr 04 12:56:22 PM PDT 24
Finished Apr 04 12:56:41 PM PDT 24
Peak memory 219016 kb
Host smart-89c269c0-739c-4b29-8e85-bca902b1bc0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310698140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2310698140
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4279772404
Short name T48
Test name
Test status
Simulation time 86577733 ps
CPU time 1.23 seconds
Started Apr 04 12:56:21 PM PDT 24
Finished Apr 04 12:56:24 PM PDT 24
Peak memory 236952 kb
Host smart-612f9f60-ab80-429a-9047-4b5f64830d9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279772404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4279772404
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1698156217
Short name T113
Test name
Test status
Simulation time 87520389463 ps
CPU time 55.3 seconds
Started Apr 04 12:56:10 PM PDT 24
Finished Apr 04 12:57:05 PM PDT 24
Peak memory 216592 kb
Host smart-6b9d6b6d-3031-4b7d-be08-bddfe93f9db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698156217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1698156217
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1629701878
Short name T721
Test name
Test status
Simulation time 385094654 ps
CPU time 2.29 seconds
Started Apr 04 12:56:13 PM PDT 24
Finished Apr 04 12:56:15 PM PDT 24
Peak memory 216532 kb
Host smart-20de13f2-63dd-4eb8-af58-f6704dc06e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629701878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1629701878
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2539067364
Short name T419
Test name
Test status
Simulation time 83123113 ps
CPU time 1.45 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:56:13 PM PDT 24
Peak memory 216508 kb
Host smart-de00367d-747e-41c1-abae-fa74cd40542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539067364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2539067364
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3909824888
Short name T489
Test name
Test status
Simulation time 922951558 ps
CPU time 0.85 seconds
Started Apr 04 12:56:11 PM PDT 24
Finished Apr 04 12:56:12 PM PDT 24
Peak memory 205728 kb
Host smart-68e83977-df62-4042-8c01-08ed08e312af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909824888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3909824888
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3838307103
Short name T743
Test name
Test status
Simulation time 14964354 ps
CPU time 0.73 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:25 PM PDT 24
Peak memory 205336 kb
Host smart-91ddf71c-bc7d-427a-8d50-38a2d6fbcf31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838307103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3838307103
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4234150617
Short name T221
Test name
Test status
Simulation time 2420931267 ps
CPU time 8.88 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:26 PM PDT 24
Peak memory 222728 kb
Host smart-cb4d0228-6230-45ed-9366-500b29e1bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234150617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4234150617
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3694129845
Short name T515
Test name
Test status
Simulation time 13587550 ps
CPU time 0.78 seconds
Started Apr 04 12:58:18 PM PDT 24
Finished Apr 04 12:58:18 PM PDT 24
Peak memory 206588 kb
Host smart-47e42909-e85b-49c7-ba33-34c2174d5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694129845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3694129845
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1957920889
Short name T472
Test name
Test status
Simulation time 90529816 ps
CPU time 1.01 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:18 PM PDT 24
Peak memory 216964 kb
Host smart-824a4257-c667-41ba-bd6b-d8f28db65963
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957920889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1957920889
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1375065256
Short name T186
Test name
Test status
Simulation time 1187003988 ps
CPU time 6.22 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:23 PM PDT 24
Peak memory 223068 kb
Host smart-a1cfa12d-642a-465a-9ad7-770c2616c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375065256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1375065256
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2416561110
Short name T682
Test name
Test status
Simulation time 123632454 ps
CPU time 0.72 seconds
Started Apr 04 12:58:15 PM PDT 24
Finished Apr 04 12:58:16 PM PDT 24
Peak memory 216328 kb
Host smart-1b801d89-62f4-4bfd-8aaf-9f5478e1e595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416561110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2416561110
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1813754749
Short name T651
Test name
Test status
Simulation time 112986956 ps
CPU time 4.49 seconds
Started Apr 04 12:58:16 PM PDT 24
Finished Apr 04 12:58:21 PM PDT 24
Peak memory 222916 kb
Host smart-797712b1-4b20-4117-b175-90e80efa22db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1813754749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1813754749
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3916944004
Short name T480
Test name
Test status
Simulation time 309607400 ps
CPU time 1.02 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:25 PM PDT 24
Peak memory 206952 kb
Host smart-680e1456-ca73-4bce-b20f-5d206f933f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916944004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3916944004
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2348428356
Short name T731
Test name
Test status
Simulation time 2917873857 ps
CPU time 31.97 seconds
Started Apr 04 12:58:15 PM PDT 24
Finished Apr 04 12:58:47 PM PDT 24
Peak memory 216560 kb
Host smart-2fbcb23c-5383-4401-9c2a-0913108f308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348428356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2348428356
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1858402433
Short name T605
Test name
Test status
Simulation time 3631518749 ps
CPU time 6.94 seconds
Started Apr 04 12:58:17 PM PDT 24
Finished Apr 04 12:58:24 PM PDT 24
Peak memory 216492 kb
Host smart-cd3c8bfd-d629-4179-a853-4000bc2c183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858402433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1858402433
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1791714175
Short name T67
Test name
Test status
Simulation time 25387743 ps
CPU time 0.97 seconds
Started Apr 04 12:58:18 PM PDT 24
Finished Apr 04 12:58:19 PM PDT 24
Peak memory 207144 kb
Host smart-47c20880-21f2-481f-b2a9-3b6631312cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791714175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1791714175
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2956305643
Short name T655
Test name
Test status
Simulation time 518689234 ps
CPU time 1.14 seconds
Started Apr 04 12:58:15 PM PDT 24
Finished Apr 04 12:58:16 PM PDT 24
Peak memory 206848 kb
Host smart-51d25ec6-9d82-4478-b099-e3c082e5972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956305643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2956305643
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.644114895
Short name T504
Test name
Test status
Simulation time 24855528 ps
CPU time 0.68 seconds
Started Apr 04 12:58:31 PM PDT 24
Finished Apr 04 12:58:32 PM PDT 24
Peak memory 205684 kb
Host smart-0851548f-483b-422f-bc60-1d7f3899e1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644114895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.644114895
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2803661777
Short name T499
Test name
Test status
Simulation time 7959241384 ps
CPU time 33.59 seconds
Started Apr 04 12:58:25 PM PDT 24
Finished Apr 04 12:58:59 PM PDT 24
Peak memory 233068 kb
Host smart-ea32ce73-ef6c-43ac-852d-d085489b1fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803661777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2803661777
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.762847986
Short name T747
Test name
Test status
Simulation time 40354220 ps
CPU time 0.81 seconds
Started Apr 04 12:58:25 PM PDT 24
Finished Apr 04 12:58:26 PM PDT 24
Peak memory 206684 kb
Host smart-9c3903e4-f155-4ed5-a83b-ab6ff179d3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762847986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.762847986
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1673288975
Short name T365
Test name
Test status
Simulation time 1206971751 ps
CPU time 23.26 seconds
Started Apr 04 12:58:27 PM PDT 24
Finished Apr 04 12:58:50 PM PDT 24
Peak memory 249340 kb
Host smart-898ff0d9-e065-4161-9cd5-cf7f6865b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673288975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1673288975
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.227485321
Short name T719
Test name
Test status
Simulation time 380368679 ps
CPU time 2.96 seconds
Started Apr 04 12:58:28 PM PDT 24
Finished Apr 04 12:58:31 PM PDT 24
Peak memory 219304 kb
Host smart-469358c3-08ad-4863-b8c3-06ce39f145b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227485321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.227485321
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1500453561
Short name T356
Test name
Test status
Simulation time 363284523 ps
CPU time 7.53 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:32 PM PDT 24
Peak memory 221096 kb
Host smart-bcbe7244-d4d6-409d-aa91-7468bc3cd193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500453561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1500453561
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2355659290
Short name T487
Test name
Test status
Simulation time 50241748 ps
CPU time 1 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:25 PM PDT 24
Peak memory 216840 kb
Host smart-5aea2ec1-d440-4ba9-994b-92ea284075e4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355659290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2355659290
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.476483073
Short name T462
Test name
Test status
Simulation time 16398142 ps
CPU time 0.75 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:25 PM PDT 24
Peak memory 216352 kb
Host smart-b7d6620b-1b14-49cd-a3f6-ae1281eb3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476483073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.476483073
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.22493958
Short name T131
Test name
Test status
Simulation time 215200474 ps
CPU time 3.93 seconds
Started Apr 04 12:58:25 PM PDT 24
Finished Apr 04 12:58:29 PM PDT 24
Peak memory 220344 kb
Host smart-525d9ac8-bf71-40cb-82a5-5fbece817762
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22493958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.22493958
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2183997521
Short name T629
Test name
Test status
Simulation time 3890498055 ps
CPU time 7.32 seconds
Started Apr 04 12:58:26 PM PDT 24
Finished Apr 04 12:58:33 PM PDT 24
Peak memory 216588 kb
Host smart-91716df5-99c2-40e5-b1be-a2513fabdc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183997521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2183997521
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1649043984
Short name T529
Test name
Test status
Simulation time 102380727 ps
CPU time 2.43 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:27 PM PDT 24
Peak memory 216632 kb
Host smart-343f7542-8902-4904-aa93-a0ea80f04920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649043984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1649043984
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2718617546
Short name T556
Test name
Test status
Simulation time 75092513 ps
CPU time 0.86 seconds
Started Apr 04 12:58:24 PM PDT 24
Finished Apr 04 12:58:25 PM PDT 24
Peak memory 205768 kb
Host smart-7d3f777b-086e-4cf1-846e-16283f571c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718617546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2718617546
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.612292048
Short name T519
Test name
Test status
Simulation time 23275009 ps
CPU time 0.72 seconds
Started Apr 04 12:58:49 PM PDT 24
Finished Apr 04 12:58:50 PM PDT 24
Peak memory 204860 kb
Host smart-6709d32a-f0d0-4665-a739-5464ab6286e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612292048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.612292048
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1104804644
Short name T136
Test name
Test status
Simulation time 308010179 ps
CPU time 2.98 seconds
Started Apr 04 12:58:44 PM PDT 24
Finished Apr 04 12:58:47 PM PDT 24
Peak memory 224312 kb
Host smart-f93a568f-9128-4a0b-ba25-5faf21aaa325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104804644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1104804644
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2466581596
Short name T20
Test name
Test status
Simulation time 23572764 ps
CPU time 0.74 seconds
Started Apr 04 12:58:31 PM PDT 24
Finished Apr 04 12:58:32 PM PDT 24
Peak memory 206568 kb
Host smart-2feade46-5248-4f9b-a37c-a6f3f0c99942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466581596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2466581596
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.623745918
Short name T316
Test name
Test status
Simulation time 38278374023 ps
CPU time 159.38 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 01:01:21 PM PDT 24
Peak memory 250392 kb
Host smart-55f32df7-31c6-4b96-a3a9-681489b5b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623745918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.623745918
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3153325470
Short name T195
Test name
Test status
Simulation time 5178541160 ps
CPU time 19.41 seconds
Started Apr 04 12:58:43 PM PDT 24
Finished Apr 04 12:59:03 PM PDT 24
Peak memory 223464 kb
Host smart-5cdbcd04-8ac2-4868-8eec-9b6d38f69e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153325470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3153325470
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4269088555
Short name T127
Test name
Test status
Simulation time 292928515 ps
CPU time 5.43 seconds
Started Apr 04 12:58:41 PM PDT 24
Finished Apr 04 12:58:47 PM PDT 24
Peak memory 216404 kb
Host smart-fd7f5d95-3952-407a-8801-c1b3c1e2aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269088555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4269088555
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1368588324
Short name T37
Test name
Test status
Simulation time 61494528 ps
CPU time 0.99 seconds
Started Apr 04 12:58:32 PM PDT 24
Finished Apr 04 12:58:33 PM PDT 24
Peak memory 216884 kb
Host smart-4567a612-e026-449f-83d6-926f34f14a1a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368588324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1368588324
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1014184298
Short name T458
Test name
Test status
Simulation time 41892358 ps
CPU time 0.73 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 216368 kb
Host smart-68e7f8e5-adc6-4247-9859-228e9c8b696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014184298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1014184298
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3081635343
Short name T538
Test name
Test status
Simulation time 1372671988 ps
CPU time 15.46 seconds
Started Apr 04 12:58:43 PM PDT 24
Finished Apr 04 12:58:58 PM PDT 24
Peak memory 219564 kb
Host smart-75f57183-49a3-4753-af04-244856ab84f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3081635343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3081635343
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.814459791
Short name T388
Test name
Test status
Simulation time 4154907985 ps
CPU time 5.98 seconds
Started Apr 04 12:58:45 PM PDT 24
Finished Apr 04 12:58:51 PM PDT 24
Peak memory 216632 kb
Host smart-593bf65b-226c-4738-9ffd-5a068aedf0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814459791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.814459791
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4141777605
Short name T21
Test name
Test status
Simulation time 19894720868 ps
CPU time 15.39 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 12:58:57 PM PDT 24
Peak memory 216596 kb
Host smart-ec2df116-3174-4e44-8c4d-19d23ca34719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141777605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4141777605
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1782589336
Short name T555
Test name
Test status
Simulation time 266041544 ps
CPU time 1.52 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 12:58:44 PM PDT 24
Peak memory 208500 kb
Host smart-91c1e479-a315-4058-8700-d52201fcc0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782589336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1782589336
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2229644223
Short name T508
Test name
Test status
Simulation time 503803239 ps
CPU time 1.06 seconds
Started Apr 04 12:58:42 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 206800 kb
Host smart-7f0dfd48-785a-4595-86fa-329278b3508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229644223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2229644223
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4098023779
Short name T728
Test name
Test status
Simulation time 50026425 ps
CPU time 0.69 seconds
Started Apr 04 12:58:58 PM PDT 24
Finished Apr 04 12:59:00 PM PDT 24
Peak memory 205384 kb
Host smart-f715dfc6-57b9-4d75-bcaf-3c3c214b626c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098023779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4098023779
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3411639516
Short name T25
Test name
Test status
Simulation time 154802982 ps
CPU time 2.27 seconds
Started Apr 04 12:58:58 PM PDT 24
Finished Apr 04 12:59:00 PM PDT 24
Peak memory 218992 kb
Host smart-f1b9798f-6b14-4610-bb6a-3af53949c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411639516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3411639516
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.280532012
Short name T665
Test name
Test status
Simulation time 20517545 ps
CPU time 0.8 seconds
Started Apr 04 12:58:48 PM PDT 24
Finished Apr 04 12:58:49 PM PDT 24
Peak memory 206952 kb
Host smart-364b2ba4-430d-4292-888d-8319bdcbd6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280532012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.280532012
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1309776695
Short name T93
Test name
Test status
Simulation time 3564906103 ps
CPU time 49.81 seconds
Started Apr 04 12:58:59 PM PDT 24
Finished Apr 04 12:59:49 PM PDT 24
Peak memory 234152 kb
Host smart-d322e7de-955f-4a7c-b8ae-ba40c560e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309776695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1309776695
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1186663887
Short name T738
Test name
Test status
Simulation time 42338183 ps
CPU time 1.02 seconds
Started Apr 04 12:58:50 PM PDT 24
Finished Apr 04 12:58:51 PM PDT 24
Peak memory 216976 kb
Host smart-970ea6bc-e9b9-4baa-b29f-d5f415214b57
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186663887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1186663887
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3081627375
Short name T672
Test name
Test status
Simulation time 31705687500 ps
CPU time 22.13 seconds
Started Apr 04 12:58:50 PM PDT 24
Finished Apr 04 12:59:12 PM PDT 24
Peak memory 224168 kb
Host smart-f6564d59-b5a0-4939-a270-78272779cdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081627375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3081627375
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.3211462844
Short name T657
Test name
Test status
Simulation time 27080348 ps
CPU time 0.73 seconds
Started Apr 04 12:58:49 PM PDT 24
Finished Apr 04 12:58:50 PM PDT 24
Peak memory 216388 kb
Host smart-50d7e3c8-4531-4282-8ca9-e05877707693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211462844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.3211462844
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1768673971
Short name T593
Test name
Test status
Simulation time 3134461614 ps
CPU time 18.45 seconds
Started Apr 04 12:58:58 PM PDT 24
Finished Apr 04 12:59:16 PM PDT 24
Peak memory 222016 kb
Host smart-ac8b9ca1-9dbc-4594-a867-20317532e7d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1768673971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1768673971
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1057680271
Short name T33
Test name
Test status
Simulation time 182302123 ps
CPU time 0.95 seconds
Started Apr 04 12:58:58 PM PDT 24
Finished Apr 04 12:58:59 PM PDT 24
Peak memory 207032 kb
Host smart-f83fe735-5fa5-4b78-ba28-3849e5856977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057680271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1057680271
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4103345026
Short name T607
Test name
Test status
Simulation time 2349670236 ps
CPU time 30.92 seconds
Started Apr 04 12:58:54 PM PDT 24
Finished Apr 04 12:59:25 PM PDT 24
Peak memory 216464 kb
Host smart-11c284f7-7960-437b-ba2f-e65a4ae9fcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103345026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4103345026
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2073562608
Short name T550
Test name
Test status
Simulation time 1282847537 ps
CPU time 2.5 seconds
Started Apr 04 12:58:51 PM PDT 24
Finished Apr 04 12:58:53 PM PDT 24
Peak memory 208132 kb
Host smart-60957c7c-d6e4-4bf5-8588-6ff47e48f141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073562608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2073562608
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.123045598
Short name T524
Test name
Test status
Simulation time 160022661 ps
CPU time 4.98 seconds
Started Apr 04 12:58:49 PM PDT 24
Finished Apr 04 12:58:55 PM PDT 24
Peak memory 216660 kb
Host smart-7b798156-a4c1-46f3-9c54-d6bffdbfa558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123045598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.123045598
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3652876952
Short name T502
Test name
Test status
Simulation time 30692888 ps
CPU time 0.87 seconds
Started Apr 04 12:58:54 PM PDT 24
Finished Apr 04 12:58:55 PM PDT 24
Peak memory 205732 kb
Host smart-f1c1d6a4-d4b9-4feb-b849-a1087344185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652876952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3652876952
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.661668163
Short name T518
Test name
Test status
Simulation time 47578913 ps
CPU time 0.72 seconds
Started Apr 04 12:59:11 PM PDT 24
Finished Apr 04 12:59:11 PM PDT 24
Peak memory 205344 kb
Host smart-a8a234c6-bbb9-40ae-a400-63bc6c5d84b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661668163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.661668163
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1184291398
Short name T421
Test name
Test status
Simulation time 28824195 ps
CPU time 0.77 seconds
Started Apr 04 12:59:00 PM PDT 24
Finished Apr 04 12:59:01 PM PDT 24
Peak memory 206716 kb
Host smart-9b5230a9-897d-4d03-9b9a-8d0fdc793b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184291398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1184291398
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1593467803
Short name T302
Test name
Test status
Simulation time 12926427087 ps
CPU time 36.81 seconds
Started Apr 04 12:59:07 PM PDT 24
Finished Apr 04 12:59:44 PM PDT 24
Peak memory 233008 kb
Host smart-d3ae44dc-0191-43fc-b463-b261d385eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593467803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1593467803
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2833118930
Short name T463
Test name
Test status
Simulation time 866346048 ps
CPU time 6.43 seconds
Started Apr 04 12:59:09 PM PDT 24
Finished Apr 04 12:59:16 PM PDT 24
Peak memory 224664 kb
Host smart-f94b1707-4a7d-4ea8-9d80-e131330e3321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833118930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2833118930
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.919191901
Short name T677
Test name
Test status
Simulation time 154643512 ps
CPU time 1.07 seconds
Started Apr 04 12:59:01 PM PDT 24
Finished Apr 04 12:59:02 PM PDT 24
Peak memory 216840 kb
Host smart-8404a447-2510-4128-b20e-9558c81b2133
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919191901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.919191901
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1561691657
Short name T43
Test name
Test status
Simulation time 20611258 ps
CPU time 0.72 seconds
Started Apr 04 12:59:02 PM PDT 24
Finished Apr 04 12:59:03 PM PDT 24
Peak memory 216372 kb
Host smart-bc3944a2-f533-4875-81cd-aaf22b635c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561691657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1561691657
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1995154151
Short name T558
Test name
Test status
Simulation time 837850810 ps
CPU time 5.43 seconds
Started Apr 04 12:59:07 PM PDT 24
Finished Apr 04 12:59:13 PM PDT 24
Peak memory 222932 kb
Host smart-b84e8539-f3b7-45f6-bc62-851ec71883c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995154151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1995154151
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1402992514
Short name T57
Test name
Test status
Simulation time 39465751446 ps
CPU time 38.1 seconds
Started Apr 04 12:59:02 PM PDT 24
Finished Apr 04 12:59:40 PM PDT 24
Peak memory 216616 kb
Host smart-18338582-2c2e-4595-9ee7-b6d350ac951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402992514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1402992514
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1488596639
Short name T646
Test name
Test status
Simulation time 823643585 ps
CPU time 3.26 seconds
Started Apr 04 12:59:02 PM PDT 24
Finished Apr 04 12:59:05 PM PDT 24
Peak memory 216516 kb
Host smart-c8661cb3-70ca-4be0-9ff0-7d70f5d24661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488596639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1488596639
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2165321728
Short name T683
Test name
Test status
Simulation time 78036054 ps
CPU time 0.81 seconds
Started Apr 04 12:59:08 PM PDT 24
Finished Apr 04 12:59:09 PM PDT 24
Peak memory 205748 kb
Host smart-72b7139f-3ccb-465e-aca5-07c8c6361b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165321728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2165321728
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2663911219
Short name T115
Test name
Test status
Simulation time 487475909 ps
CPU time 1.11 seconds
Started Apr 04 12:59:07 PM PDT 24
Finished Apr 04 12:59:08 PM PDT 24
Peak memory 206776 kb
Host smart-00d36d9b-bdd9-474b-9ef6-394b60ce99f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663911219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2663911219
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4114261524
Short name T284
Test name
Test status
Simulation time 2637170335 ps
CPU time 6.02 seconds
Started Apr 04 12:59:07 PM PDT 24
Finished Apr 04 12:59:13 PM PDT 24
Peak memory 235312 kb
Host smart-d98e97c9-78a5-4073-adff-71a63533d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114261524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4114261524
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1030809173
Short name T742
Test name
Test status
Simulation time 32190915 ps
CPU time 0.71 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 12:59:24 PM PDT 24
Peak memory 205416 kb
Host smart-04414ecf-1aea-40c2-95fa-ec38ec928391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030809173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1030809173
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.142118181
Short name T599
Test name
Test status
Simulation time 12201291378 ps
CPU time 39.25 seconds
Started Apr 04 12:59:15 PM PDT 24
Finished Apr 04 12:59:54 PM PDT 24
Peak memory 218852 kb
Host smart-82786f50-519d-4af2-ba6d-7e11bd4dfc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142118181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.142118181
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3701888914
Short name T526
Test name
Test status
Simulation time 57626890 ps
CPU time 0.8 seconds
Started Apr 04 12:59:08 PM PDT 24
Finished Apr 04 12:59:09 PM PDT 24
Peak memory 206944 kb
Host smart-d3e1f433-0f9c-42aa-8d71-37b4e6ced476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701888914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3701888914
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1518026698
Short name T603
Test name
Test status
Simulation time 16559852880 ps
CPU time 63.67 seconds
Started Apr 04 12:59:17 PM PDT 24
Finished Apr 04 01:00:20 PM PDT 24
Peak memory 232892 kb
Host smart-aaa395c5-936d-42d3-aa29-b399dcd57ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518026698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1518026698
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3985310414
Short name T754
Test name
Test status
Simulation time 3469891303 ps
CPU time 29.99 seconds
Started Apr 04 12:59:14 PM PDT 24
Finished Apr 04 12:59:44 PM PDT 24
Peak memory 232968 kb
Host smart-33d5205c-ab77-44c3-bb28-1b3f0e62e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985310414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3985310414
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2274141567
Short name T660
Test name
Test status
Simulation time 28758921 ps
CPU time 1.03 seconds
Started Apr 04 12:59:09 PM PDT 24
Finished Apr 04 12:59:11 PM PDT 24
Peak memory 218096 kb
Host smart-667c1300-c05a-4345-955c-facbf992a859
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274141567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2274141567
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3686482703
Short name T340
Test name
Test status
Simulation time 2824083547 ps
CPU time 6.06 seconds
Started Apr 04 12:59:14 PM PDT 24
Finished Apr 04 12:59:21 PM PDT 24
Peak memory 219500 kb
Host smart-1ec125ba-8e9e-476f-8f38-b0fe7da6db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686482703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3686482703
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3850829690
Short name T452
Test name
Test status
Simulation time 46394753 ps
CPU time 0.75 seconds
Started Apr 04 12:59:08 PM PDT 24
Finished Apr 04 12:59:09 PM PDT 24
Peak memory 216356 kb
Host smart-5d859ba4-755a-4817-8036-e0d5f6f5d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850829690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3850829690
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.89362773
Short name T94
Test name
Test status
Simulation time 6546879767 ps
CPU time 17.88 seconds
Started Apr 04 12:59:19 PM PDT 24
Finished Apr 04 12:59:37 PM PDT 24
Peak memory 220444 kb
Host smart-e3b6f3e9-ca03-4f70-b7d2-0a0d59053b69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=89362773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direc
t.89362773
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3518750571
Short name T496
Test name
Test status
Simulation time 1885087938 ps
CPU time 11.77 seconds
Started Apr 04 12:59:08 PM PDT 24
Finished Apr 04 12:59:20 PM PDT 24
Peak memory 216560 kb
Host smart-3b2d6c22-29a3-4828-b63c-15e5fe94d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518750571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3518750571
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.956919082
Short name T470
Test name
Test status
Simulation time 2278899173 ps
CPU time 2.47 seconds
Started Apr 04 12:59:11 PM PDT 24
Finished Apr 04 12:59:13 PM PDT 24
Peak memory 207116 kb
Host smart-b35a23d0-a8dd-498d-9247-9cdcc957a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956919082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.956919082
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1564160934
Short name T417
Test name
Test status
Simulation time 149796232 ps
CPU time 2.71 seconds
Started Apr 04 12:59:15 PM PDT 24
Finished Apr 04 12:59:18 PM PDT 24
Peak memory 216544 kb
Host smart-6c83243a-e2c2-4bf1-907b-e00ec3043e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564160934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1564160934
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3765916345
Short name T714
Test name
Test status
Simulation time 163332585 ps
CPU time 0.86 seconds
Started Apr 04 12:59:18 PM PDT 24
Finished Apr 04 12:59:20 PM PDT 24
Peak memory 205796 kb
Host smart-264fa077-19d6-446c-a794-70f29ec2994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765916345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3765916345
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1393867835
Short name T342
Test name
Test status
Simulation time 1274325821 ps
CPU time 7.38 seconds
Started Apr 04 12:59:14 PM PDT 24
Finished Apr 04 12:59:22 PM PDT 24
Peak memory 216608 kb
Host smart-af6a38cf-1c46-47da-ada6-19b5dfac202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393867835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1393867835
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1592830727
Short name T676
Test name
Test status
Simulation time 28132795 ps
CPU time 0.71 seconds
Started Apr 04 12:59:36 PM PDT 24
Finished Apr 04 12:59:37 PM PDT 24
Peak memory 205452 kb
Host smart-4ea2178d-6fe4-48d6-b993-18bb21f63e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592830727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1592830727
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3724454478
Short name T479
Test name
Test status
Simulation time 17348204 ps
CPU time 0.79 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 12:59:24 PM PDT 24
Peak memory 206632 kb
Host smart-8c8891fe-ab44-4af1-a441-d2055a5e4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724454478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3724454478
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3753904088
Short name T628
Test name
Test status
Simulation time 3505460630 ps
CPU time 56.44 seconds
Started Apr 04 12:59:25 PM PDT 24
Finished Apr 04 01:00:22 PM PDT 24
Peak memory 241240 kb
Host smart-0e6b5849-7736-4832-b2ef-d432bd45979a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753904088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3753904088
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2174732270
Short name T100
Test name
Test status
Simulation time 5420046800 ps
CPU time 80.47 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 01:00:43 PM PDT 24
Peak memory 221868 kb
Host smart-8056301b-646b-4da5-972d-8f988dd5c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174732270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2174732270
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3508309726
Short name T708
Test name
Test status
Simulation time 32336304 ps
CPU time 1.11 seconds
Started Apr 04 12:59:25 PM PDT 24
Finished Apr 04 12:59:26 PM PDT 24
Peak memory 216928 kb
Host smart-3933d9f7-6362-4bf2-a036-82ab5214994f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508309726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3508309726
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2851086655
Short name T78
Test name
Test status
Simulation time 407517312 ps
CPU time 6.68 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 12:59:30 PM PDT 24
Peak memory 220536 kb
Host smart-121e154c-1873-4d9a-a65a-588faf570cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851086655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2851086655
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.846710968
Short name T54
Test name
Test status
Simulation time 35328277 ps
CPU time 0.73 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 12:59:25 PM PDT 24
Peak memory 216224 kb
Host smart-b2bf4d6d-a924-43c8-8e1b-c60c40e423d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846710968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.846710968
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1954164336
Short name T659
Test name
Test status
Simulation time 88975831 ps
CPU time 3.86 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 12:59:27 PM PDT 24
Peak memory 220200 kb
Host smart-004d8962-a785-47f0-aa78-61a68f23a654
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1954164336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1954164336
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1498238146
Short name T552
Test name
Test status
Simulation time 4508037247 ps
CPU time 37.7 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 01:00:02 PM PDT 24
Peak memory 216616 kb
Host smart-fa32bd49-4f50-48d5-b7a5-4f7d3b7f154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498238146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1498238146
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.665730157
Short name T528
Test name
Test status
Simulation time 1880456850 ps
CPU time 5.08 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 12:59:28 PM PDT 24
Peak memory 216516 kb
Host smart-9f249413-c422-41eb-a35c-319a422adcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665730157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.665730157
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.322965503
Short name T415
Test name
Test status
Simulation time 23208392 ps
CPU time 0.85 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 12:59:25 PM PDT 24
Peak memory 206588 kb
Host smart-a0761f46-95a8-4879-8728-94a1ff61551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322965503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.322965503
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3758075487
Short name T735
Test name
Test status
Simulation time 51141044 ps
CPU time 0.81 seconds
Started Apr 04 12:59:24 PM PDT 24
Finished Apr 04 12:59:25 PM PDT 24
Peak memory 205740 kb
Host smart-5bef0b7f-1bc0-4edd-8f74-a1fd67bbdf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758075487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3758075487
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.281800577
Short name T237
Test name
Test status
Simulation time 280703208 ps
CPU time 3.19 seconds
Started Apr 04 12:59:23 PM PDT 24
Finished Apr 04 12:59:26 PM PDT 24
Peak memory 220936 kb
Host smart-5cf5e7a8-2b9c-487c-96d4-bcfd96dea7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281800577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.281800577
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2262926516
Short name T491
Test name
Test status
Simulation time 41743382 ps
CPU time 0.73 seconds
Started Apr 04 12:59:40 PM PDT 24
Finished Apr 04 12:59:41 PM PDT 24
Peak memory 205416 kb
Host smart-e9b3cd11-03b3-458e-8cc7-8a4089b882bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262926516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2262926516
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3083097520
Short name T673
Test name
Test status
Simulation time 21533615 ps
CPU time 0.83 seconds
Started Apr 04 12:59:31 PM PDT 24
Finished Apr 04 12:59:32 PM PDT 24
Peak memory 206588 kb
Host smart-c6896c19-2e9d-4ae7-b6d7-ea42d0015707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083097520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3083097520
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.972271974
Short name T633
Test name
Test status
Simulation time 5318801926 ps
CPU time 29.94 seconds
Started Apr 04 12:59:40 PM PDT 24
Finished Apr 04 01:00:10 PM PDT 24
Peak memory 240020 kb
Host smart-b738df05-dfd0-42a2-837f-98018e4a2434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972271974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.972271974
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3525742822
Short name T183
Test name
Test status
Simulation time 395598636 ps
CPU time 4.48 seconds
Started Apr 04 12:59:36 PM PDT 24
Finished Apr 04 12:59:41 PM PDT 24
Peak memory 222740 kb
Host smart-e4f1f406-802a-44e6-9a6a-352fb76fe42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525742822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3525742822
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.438723656
Short name T621
Test name
Test status
Simulation time 490004914 ps
CPU time 2.54 seconds
Started Apr 04 12:59:32 PM PDT 24
Finished Apr 04 12:59:34 PM PDT 24
Peak memory 223120 kb
Host smart-faa7100a-8337-4ff5-afcc-b159ad1b06da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438723656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.438723656
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1461183752
Short name T648
Test name
Test status
Simulation time 33965822 ps
CPU time 1.1 seconds
Started Apr 04 12:59:36 PM PDT 24
Finished Apr 04 12:59:37 PM PDT 24
Peak memory 216968 kb
Host smart-3d4bb670-79db-4136-8b46-48bf4d94d959
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461183752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1461183752
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2981219927
Short name T561
Test name
Test status
Simulation time 16840328 ps
CPU time 0.73 seconds
Started Apr 04 12:59:32 PM PDT 24
Finished Apr 04 12:59:33 PM PDT 24
Peak memory 216264 kb
Host smart-bc65cc08-ae26-4c99-b39a-b13514f71f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981219927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2981219927
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1352363107
Short name T541
Test name
Test status
Simulation time 610647366 ps
CPU time 5.64 seconds
Started Apr 04 12:59:40 PM PDT 24
Finished Apr 04 12:59:46 PM PDT 24
Peak memory 222976 kb
Host smart-80d9ee2d-ad74-48f5-8275-a7afd9fea10d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352363107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1352363107
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1712330710
Short name T548
Test name
Test status
Simulation time 11125213352 ps
CPU time 18.75 seconds
Started Apr 04 12:59:31 PM PDT 24
Finished Apr 04 12:59:50 PM PDT 24
Peak memory 216656 kb
Host smart-dc3bc2f0-d277-4b40-afb7-a9bebdb13486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712330710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1712330710
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3681433463
Short name T408
Test name
Test status
Simulation time 411292370 ps
CPU time 3.83 seconds
Started Apr 04 12:59:34 PM PDT 24
Finished Apr 04 12:59:38 PM PDT 24
Peak memory 216492 kb
Host smart-429e9e0d-6883-4167-a794-0f3790275048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681433463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3681433463
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2753845321
Short name T520
Test name
Test status
Simulation time 132239674 ps
CPU time 1.12 seconds
Started Apr 04 12:59:31 PM PDT 24
Finished Apr 04 12:59:33 PM PDT 24
Peak memory 206884 kb
Host smart-a45419bc-4c50-4a2d-ae75-774c4cfea3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753845321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2753845321
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1973466593
Short name T475
Test name
Test status
Simulation time 32853409 ps
CPU time 0.7 seconds
Started Apr 04 12:59:50 PM PDT 24
Finished Apr 04 12:59:51 PM PDT 24
Peak memory 205372 kb
Host smart-d743b322-56cd-4f85-a8c8-07f3c20b10bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973466593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1973466593
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.780581481
Short name T15
Test name
Test status
Simulation time 21097745 ps
CPU time 0.8 seconds
Started Apr 04 12:59:40 PM PDT 24
Finished Apr 04 12:59:41 PM PDT 24
Peak memory 206608 kb
Host smart-12841f08-25fb-4d1c-bfdf-2d9c61c7ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780581481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.780581481
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.252265905
Short name T667
Test name
Test status
Simulation time 1967322937 ps
CPU time 35.18 seconds
Started Apr 04 12:59:48 PM PDT 24
Finished Apr 04 01:00:23 PM PDT 24
Peak memory 237476 kb
Host smart-39001fbd-ed96-4496-8f4e-4743fbf2a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252265905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.252265905
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.49296844
Short name T591
Test name
Test status
Simulation time 32465940 ps
CPU time 1.15 seconds
Started Apr 04 12:59:39 PM PDT 24
Finished Apr 04 12:59:41 PM PDT 24
Peak memory 216972 kb
Host smart-05c98b38-d1f2-4546-866a-ad3f55a32c58
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49296844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.49296844
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2886920911
Short name T230
Test name
Test status
Simulation time 10236600767 ps
CPU time 34.75 seconds
Started Apr 04 12:59:39 PM PDT 24
Finished Apr 04 01:00:14 PM PDT 24
Peak memory 227080 kb
Host smart-dc74f6d3-1b84-46dd-9d1c-a575be50d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886920911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2886920911
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.4232476508
Short name T42
Test name
Test status
Simulation time 59321339 ps
CPU time 0.7 seconds
Started Apr 04 12:59:38 PM PDT 24
Finished Apr 04 12:59:39 PM PDT 24
Peak memory 216376 kb
Host smart-14570f2e-e3b8-477b-aaad-a8f271eef0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232476508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.4232476508
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2246328622
Short name T522
Test name
Test status
Simulation time 70865156 ps
CPU time 4.19 seconds
Started Apr 04 12:59:48 PM PDT 24
Finished Apr 04 12:59:53 PM PDT 24
Peak memory 222872 kb
Host smart-eec66f86-ca8b-4cad-aea2-9cf5fdb31664
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246328622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2246328622
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.701560415
Short name T749
Test name
Test status
Simulation time 3887522394 ps
CPU time 19.3 seconds
Started Apr 04 12:59:41 PM PDT 24
Finished Apr 04 01:00:00 PM PDT 24
Peak memory 216552 kb
Host smart-79b7668c-e374-43d7-8076-5012c2a294aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701560415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.701560415
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3263601434
Short name T713
Test name
Test status
Simulation time 2621766755 ps
CPU time 9.57 seconds
Started Apr 04 12:59:40 PM PDT 24
Finished Apr 04 12:59:49 PM PDT 24
Peak memory 216496 kb
Host smart-70f927ca-8055-4600-a075-6f42b5b26a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263601434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3263601434
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2843388287
Short name T394
Test name
Test status
Simulation time 1453976923 ps
CPU time 6.17 seconds
Started Apr 04 12:59:39 PM PDT 24
Finished Apr 04 12:59:46 PM PDT 24
Peak memory 216476 kb
Host smart-c05186d5-f2bd-4ae6-8087-9e6335985265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843388287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2843388287
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1054789046
Short name T568
Test name
Test status
Simulation time 509002318 ps
CPU time 0.83 seconds
Started Apr 04 12:59:39 PM PDT 24
Finished Apr 04 12:59:40 PM PDT 24
Peak memory 205732 kb
Host smart-ec80d11a-0558-4206-a6ee-2cb0fefaf94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054789046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1054789046
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3171509422
Short name T602
Test name
Test status
Simulation time 22681199 ps
CPU time 0.72 seconds
Started Apr 04 01:00:08 PM PDT 24
Finished Apr 04 01:00:08 PM PDT 24
Peak memory 204760 kb
Host smart-e6a4efe4-9024-41b1-b458-f80bdfd34b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171509422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3171509422
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.654546065
Short name T109
Test name
Test status
Simulation time 766960713 ps
CPU time 5.57 seconds
Started Apr 04 12:59:58 PM PDT 24
Finished Apr 04 01:00:03 PM PDT 24
Peak memory 222540 kb
Host smart-c8e0907c-1c43-441d-8ccc-fbc494f811ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654546065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.654546065
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.663072908
Short name T427
Test name
Test status
Simulation time 22676397 ps
CPU time 0.81 seconds
Started Apr 04 12:59:48 PM PDT 24
Finished Apr 04 12:59:49 PM PDT 24
Peak memory 206952 kb
Host smart-dcd71f2c-175e-4734-80d1-9781bb09f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663072908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.663072908
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1839516408
Short name T359
Test name
Test status
Simulation time 1288783581 ps
CPU time 33.37 seconds
Started Apr 04 12:59:58 PM PDT 24
Finished Apr 04 01:00:31 PM PDT 24
Peak memory 240384 kb
Host smart-4f2901f6-e67f-400d-a51c-45954a325ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839516408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1839516408
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3097746382
Short name T326
Test name
Test status
Simulation time 28953800842 ps
CPU time 44.41 seconds
Started Apr 04 12:59:56 PM PDT 24
Finished Apr 04 01:00:40 PM PDT 24
Peak memory 249360 kb
Host smart-cf05c822-9d89-4dad-99e0-28d097957b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097746382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3097746382
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.774784312
Short name T36
Test name
Test status
Simulation time 126755372 ps
CPU time 1.14 seconds
Started Apr 04 12:59:48 PM PDT 24
Finished Apr 04 12:59:49 PM PDT 24
Peak memory 216864 kb
Host smart-bd8a3f48-24fd-4528-a5bc-9a6ac73fb544
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774784312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.774784312
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2714085058
Short name T82
Test name
Test status
Simulation time 76248023383 ps
CPU time 28.4 seconds
Started Apr 04 12:59:56 PM PDT 24
Finished Apr 04 01:00:25 PM PDT 24
Peak memory 240444 kb
Host smart-a1ce937d-873b-41aa-a02d-ef2659b16b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714085058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2714085058
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3587223462
Short name T497
Test name
Test status
Simulation time 26112701 ps
CPU time 0.76 seconds
Started Apr 04 12:59:57 PM PDT 24
Finished Apr 04 12:59:57 PM PDT 24
Peak memory 216392 kb
Host smart-ac74f377-61c2-4b82-bead-e574dde577dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587223462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3587223462
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4181382162
Short name T547
Test name
Test status
Simulation time 861713504 ps
CPU time 9.58 seconds
Started Apr 04 12:59:56 PM PDT 24
Finished Apr 04 01:00:06 PM PDT 24
Peak memory 222088 kb
Host smart-9ef5e56b-b78f-4833-a836-d2aeefd3b98a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181382162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4181382162
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3805343856
Short name T674
Test name
Test status
Simulation time 1430209075 ps
CPU time 11.32 seconds
Started Apr 04 12:59:56 PM PDT 24
Finished Apr 04 01:00:08 PM PDT 24
Peak memory 216660 kb
Host smart-1e4ef5d1-ded6-4d94-8e7e-7e5176fc4a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805343856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3805343856
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3022857486
Short name T476
Test name
Test status
Simulation time 4541488727 ps
CPU time 16.8 seconds
Started Apr 04 12:59:57 PM PDT 24
Finished Apr 04 01:00:14 PM PDT 24
Peak memory 216484 kb
Host smart-79d0f155-6e33-4ea3-ad6a-92782e3bbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022857486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3022857486
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3826054010
Short name T70
Test name
Test status
Simulation time 663070630 ps
CPU time 2.61 seconds
Started Apr 04 12:59:59 PM PDT 24
Finished Apr 04 01:00:01 PM PDT 24
Peak memory 216556 kb
Host smart-8b8f88d4-50c8-4102-a8db-546ae2877220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826054010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3826054010
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2538490715
Short name T498
Test name
Test status
Simulation time 74195826 ps
CPU time 0.93 seconds
Started Apr 04 12:59:56 PM PDT 24
Finished Apr 04 12:59:57 PM PDT 24
Peak memory 206752 kb
Host smart-e1e85f5b-c3b3-4d73-bde8-03724d10a985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538490715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2538490715
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1672748100
Short name T231
Test name
Test status
Simulation time 22393188682 ps
CPU time 31.42 seconds
Started Apr 04 12:59:58 PM PDT 24
Finished Apr 04 01:00:30 PM PDT 24
Peak memory 222920 kb
Host smart-0d291bd8-ba6f-44d9-889e-254664e7a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672748100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1672748100
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2827564523
Short name T554
Test name
Test status
Simulation time 13985343 ps
CPU time 0.75 seconds
Started Apr 04 12:56:41 PM PDT 24
Finished Apr 04 12:56:41 PM PDT 24
Peak memory 205368 kb
Host smart-ce758bb8-0641-41b0-88d3-403ae8a84583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827564523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
827564523
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.600668442
Short name T609
Test name
Test status
Simulation time 64494791 ps
CPU time 0.8 seconds
Started Apr 04 12:56:30 PM PDT 24
Finished Apr 04 12:56:31 PM PDT 24
Peak memory 206940 kb
Host smart-edf25b32-5ba2-4f93-98f8-42348334d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600668442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.600668442
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3698610174
Short name T314
Test name
Test status
Simulation time 5172466409 ps
CPU time 85.94 seconds
Started Apr 04 12:56:40 PM PDT 24
Finished Apr 04 12:58:06 PM PDT 24
Peak memory 252496 kb
Host smart-042bbd84-d6f1-417f-8086-ba4f43c8b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698610174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3698610174
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2538997387
Short name T46
Test name
Test status
Simulation time 1317784167 ps
CPU time 10.9 seconds
Started Apr 04 12:56:30 PM PDT 24
Finished Apr 04 12:56:41 PM PDT 24
Peak memory 218652 kb
Host smart-22d3ec74-fa1d-481e-9f29-72e606c36f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538997387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2538997387
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.171050626
Short name T139
Test name
Test status
Simulation time 2313413993 ps
CPU time 20.69 seconds
Started Apr 04 12:56:30 PM PDT 24
Finished Apr 04 12:56:51 PM PDT 24
Peak memory 220184 kb
Host smart-45a95e9c-ea88-455b-ae7c-b8ebdcc159f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171050626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.171050626
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3667889377
Short name T618
Test name
Test status
Simulation time 64298780 ps
CPU time 1.1 seconds
Started Apr 04 12:56:30 PM PDT 24
Finished Apr 04 12:56:31 PM PDT 24
Peak memory 216960 kb
Host smart-5252c3ba-a8d8-41e1-958b-f0961c072822
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667889377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3667889377
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2940010406
Short name T527
Test name
Test status
Simulation time 18455297 ps
CPU time 0.73 seconds
Started Apr 04 12:56:30 PM PDT 24
Finished Apr 04 12:56:31 PM PDT 24
Peak memory 216272 kb
Host smart-98c9a8b2-bf7e-4531-8aeb-0ef3e92c815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940010406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2940010406
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1189163761
Short name T681
Test name
Test status
Simulation time 170473121 ps
CPU time 4.16 seconds
Started Apr 04 12:56:41 PM PDT 24
Finished Apr 04 12:56:46 PM PDT 24
Peak memory 222924 kb
Host smart-854f9192-53a1-495e-a178-b97ac3c2515b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1189163761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1189163761
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2916360485
Short name T52
Test name
Test status
Simulation time 34145431 ps
CPU time 1 seconds
Started Apr 04 12:56:40 PM PDT 24
Finished Apr 04 12:56:41 PM PDT 24
Peak memory 235420 kb
Host smart-709a658f-d9d5-43c7-be24-b4a951c7f4b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916360485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2916360485
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3002376024
Short name T407
Test name
Test status
Simulation time 971983796 ps
CPU time 8.16 seconds
Started Apr 04 12:56:33 PM PDT 24
Finished Apr 04 12:56:41 PM PDT 24
Peak memory 216568 kb
Host smart-b413384c-1b59-4b52-90b3-e9f56ab2b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002376024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3002376024
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3950854407
Short name T588
Test name
Test status
Simulation time 10212225253 ps
CPU time 9.67 seconds
Started Apr 04 12:56:34 PM PDT 24
Finished Apr 04 12:56:44 PM PDT 24
Peak memory 216552 kb
Host smart-320b6942-0ffa-43ff-aae8-2710b562d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950854407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3950854407
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2343142147
Short name T22
Test name
Test status
Simulation time 324077516 ps
CPU time 2.43 seconds
Started Apr 04 12:56:32 PM PDT 24
Finished Apr 04 12:56:35 PM PDT 24
Peak memory 216636 kb
Host smart-fd181296-a634-4157-b787-9e873b437827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343142147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2343142147
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.31517898
Short name T562
Test name
Test status
Simulation time 311092537 ps
CPU time 0.88 seconds
Started Apr 04 12:56:31 PM PDT 24
Finished Apr 04 12:56:32 PM PDT 24
Peak memory 205856 kb
Host smart-dbf28978-4427-45c6-a69d-c9315ba8e3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31517898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.31517898
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1366048950
Short name T96
Test name
Test status
Simulation time 160860307 ps
CPU time 3.75 seconds
Started Apr 04 12:56:42 PM PDT 24
Finished Apr 04 12:56:46 PM PDT 24
Peak memory 232404 kb
Host smart-2889b598-2671-44ec-81c9-15b8826bb4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366048950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1366048950
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1131820272
Short name T647
Test name
Test status
Simulation time 25244908 ps
CPU time 0.72 seconds
Started Apr 04 01:00:16 PM PDT 24
Finished Apr 04 01:00:17 PM PDT 24
Peak memory 205632 kb
Host smart-9f97a491-9f59-4042-b7bf-efe921c53b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131820272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1131820272
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3065385080
Short name T730
Test name
Test status
Simulation time 214952925 ps
CPU time 3.53 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:11 PM PDT 24
Peak memory 223768 kb
Host smart-d441911f-1451-413f-b6e9-1558229efb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065385080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3065385080
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2370959795
Short name T461
Test name
Test status
Simulation time 16586277 ps
CPU time 0.73 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:08 PM PDT 24
Peak memory 205540 kb
Host smart-ba779e6f-84e5-4a1f-96a7-da55522ee15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370959795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2370959795
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1536914999
Short name T690
Test name
Test status
Simulation time 892772017 ps
CPU time 7 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:14 PM PDT 24
Peak memory 241008 kb
Host smart-d8bfb17e-6e46-44b8-94f3-fb801c35c794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536914999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1536914999
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4015110204
Short name T223
Test name
Test status
Simulation time 388355730 ps
CPU time 6.11 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:13 PM PDT 24
Peak memory 221296 kb
Host smart-b5d3458d-e9ea-4caa-bd81-88b7a4f43c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015110204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4015110204
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2164831627
Short name T206
Test name
Test status
Simulation time 3025617845 ps
CPU time 42.17 seconds
Started Apr 04 01:00:08 PM PDT 24
Finished Apr 04 01:00:50 PM PDT 24
Peak memory 224120 kb
Host smart-eb558b03-5e75-4330-9026-3bf3ea626cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164831627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2164831627
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4115089202
Short name T717
Test name
Test status
Simulation time 3161146435 ps
CPU time 13.28 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:20 PM PDT 24
Peak memory 224168 kb
Host smart-10da9ea9-cd9f-46b6-89cd-60e27a103f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115089202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4115089202
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1042712262
Short name T729
Test name
Test status
Simulation time 3252254744 ps
CPU time 11.32 seconds
Started Apr 04 01:00:08 PM PDT 24
Finished Apr 04 01:00:20 PM PDT 24
Peak memory 221604 kb
Host smart-db86c30c-2a59-4611-ab68-ffa3e7c4b54c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1042712262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1042712262
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3445444013
Short name T383
Test name
Test status
Simulation time 11399264432 ps
CPU time 37.01 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:44 PM PDT 24
Peak memory 216588 kb
Host smart-a90c9f97-31df-4732-bd54-303e56f6ce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445444013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3445444013
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1929929996
Short name T459
Test name
Test status
Simulation time 801425586 ps
CPU time 5.24 seconds
Started Apr 04 01:00:05 PM PDT 24
Finished Apr 04 01:00:11 PM PDT 24
Peak memory 216636 kb
Host smart-9894702c-fcd6-4032-a386-6bb612a8816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929929996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1929929996
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3269001427
Short name T722
Test name
Test status
Simulation time 42156548 ps
CPU time 1.51 seconds
Started Apr 04 01:00:06 PM PDT 24
Finished Apr 04 01:00:08 PM PDT 24
Peak memory 208296 kb
Host smart-6ddaa930-f2e1-47f5-9e0f-f5893d523c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269001427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3269001427
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4042775344
Short name T666
Test name
Test status
Simulation time 83193548 ps
CPU time 0.88 seconds
Started Apr 04 01:00:07 PM PDT 24
Finished Apr 04 01:00:08 PM PDT 24
Peak memory 205872 kb
Host smart-44c9a80a-b595-406e-a96b-e8af4bd38a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042775344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4042775344
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3486705565
Short name T448
Test name
Test status
Simulation time 117172797 ps
CPU time 0.67 seconds
Started Apr 04 01:00:27 PM PDT 24
Finished Apr 04 01:00:29 PM PDT 24
Peak memory 205400 kb
Host smart-cb657efa-234b-4980-a30f-61782d5d6ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486705565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3486705565
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3891518677
Short name T695
Test name
Test status
Simulation time 164687001 ps
CPU time 3.62 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:29 PM PDT 24
Peak memory 217584 kb
Host smart-a2d46901-4502-476d-b7d7-8b7bff3dd01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891518677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3891518677
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2256800357
Short name T689
Test name
Test status
Simulation time 28463750 ps
CPU time 0.77 seconds
Started Apr 04 01:00:16 PM PDT 24
Finished Apr 04 01:00:17 PM PDT 24
Peak memory 206952 kb
Host smart-5f160fda-6fd2-475a-a399-0f478445f8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256800357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2256800357
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1397202098
Short name T576
Test name
Test status
Simulation time 550482911 ps
CPU time 2.7 seconds
Started Apr 04 01:00:18 PM PDT 24
Finished Apr 04 01:00:21 PM PDT 24
Peak memory 222760 kb
Host smart-7e625e44-81d0-4c60-9f35-942991384feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397202098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1397202098
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3480717788
Short name T536
Test name
Test status
Simulation time 2351344972 ps
CPU time 7.7 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:33 PM PDT 24
Peak memory 220112 kb
Host smart-a5a3e860-d317-4a1d-863a-234c9add7c6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3480717788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3480717788
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.166852039
Short name T642
Test name
Test status
Simulation time 9234722822 ps
CPU time 35.04 seconds
Started Apr 04 01:00:16 PM PDT 24
Finished Apr 04 01:00:51 PM PDT 24
Peak memory 216572 kb
Host smart-e76b6bf2-119a-4a6e-997b-b986e6573df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166852039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.166852039
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2006549081
Short name T680
Test name
Test status
Simulation time 45396812680 ps
CPU time 29.03 seconds
Started Apr 04 01:00:18 PM PDT 24
Finished Apr 04 01:00:48 PM PDT 24
Peak memory 216548 kb
Host smart-b715af35-3c2d-4d8f-a27f-375e08027c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006549081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2006549081
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.212879176
Short name T611
Test name
Test status
Simulation time 49791985 ps
CPU time 1.3 seconds
Started Apr 04 01:00:16 PM PDT 24
Finished Apr 04 01:00:17 PM PDT 24
Peak memory 208344 kb
Host smart-72ccce17-f0d9-4dfe-92ea-5723e77ce5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212879176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.212879176
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.877959507
Short name T460
Test name
Test status
Simulation time 204810352 ps
CPU time 1.04 seconds
Started Apr 04 01:00:18 PM PDT 24
Finished Apr 04 01:00:19 PM PDT 24
Peak memory 206880 kb
Host smart-a7754850-05ab-44a6-a6d3-014ddd3f59d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877959507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.877959507
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1797695425
Short name T347
Test name
Test status
Simulation time 1138096377 ps
CPU time 5.9 seconds
Started Apr 04 01:00:27 PM PDT 24
Finished Apr 04 01:00:33 PM PDT 24
Peak memory 238340 kb
Host smart-238b92a1-17b0-46f8-974d-8bb015aac63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797695425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1797695425
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.304075800
Short name T549
Test name
Test status
Simulation time 22483437 ps
CPU time 0.73 seconds
Started Apr 04 01:00:35 PM PDT 24
Finished Apr 04 01:00:36 PM PDT 24
Peak memory 205392 kb
Host smart-4edd7ae6-3891-4224-824d-d3dd2cb6d6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304075800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.304075800
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1190665846
Short name T428
Test name
Test status
Simulation time 54557069 ps
CPU time 0.75 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:26 PM PDT 24
Peak memory 205576 kb
Host smart-0086087f-516f-4669-8d71-fcb8dea47526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190665846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1190665846
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4216783276
Short name T305
Test name
Test status
Simulation time 55251819509 ps
CPU time 86.71 seconds
Started Apr 04 01:00:36 PM PDT 24
Finished Apr 04 01:02:02 PM PDT 24
Peak memory 240908 kb
Host smart-bac358cd-2ea4-4320-a298-f40a9d428abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216783276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4216783276
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3568221640
Short name T138
Test name
Test status
Simulation time 16340302086 ps
CPU time 105.98 seconds
Started Apr 04 01:00:38 PM PDT 24
Finished Apr 04 01:02:24 PM PDT 24
Peak memory 233100 kb
Host smart-edd7b780-8f0c-474f-bbeb-88ad417b3fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568221640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3568221640
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4049661607
Short name T300
Test name
Test status
Simulation time 4348459646 ps
CPU time 16.59 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:42 PM PDT 24
Peak memory 238544 kb
Host smart-dd5e848a-3eda-48be-988e-0daebb11721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049661607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4049661607
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3751426636
Short name T501
Test name
Test status
Simulation time 1822353938 ps
CPU time 4.9 seconds
Started Apr 04 01:00:35 PM PDT 24
Finished Apr 04 01:00:40 PM PDT 24
Peak memory 222832 kb
Host smart-9b8c20ac-181a-4099-8619-41cc9ef03499
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751426636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3751426636
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2009098584
Short name T745
Test name
Test status
Simulation time 6557507371 ps
CPU time 6.51 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:31 PM PDT 24
Peak memory 216560 kb
Host smart-4c202021-b5a8-4f9f-815e-46ba67f7ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009098584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2009098584
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1538153549
Short name T587
Test name
Test status
Simulation time 1789302084 ps
CPU time 7.08 seconds
Started Apr 04 01:00:26 PM PDT 24
Finished Apr 04 01:00:33 PM PDT 24
Peak memory 218864 kb
Host smart-3ca2d1e8-7f08-4337-9854-dee1bd96af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538153549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1538153549
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2265895570
Short name T678
Test name
Test status
Simulation time 74028505 ps
CPU time 0.99 seconds
Started Apr 04 01:00:25 PM PDT 24
Finished Apr 04 01:00:27 PM PDT 24
Peak memory 206872 kb
Host smart-784566c7-f3e7-46f7-b180-ec7c7dd3d165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265895570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2265895570
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3255893660
Short name T551
Test name
Test status
Simulation time 28682997 ps
CPU time 0.71 seconds
Started Apr 04 01:00:56 PM PDT 24
Finished Apr 04 01:00:57 PM PDT 24
Peak memory 204860 kb
Host smart-5211a363-87d8-4a21-89c6-88adf53b69c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255893660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3255893660
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.213595071
Short name T492
Test name
Test status
Simulation time 61676636 ps
CPU time 0.75 seconds
Started Apr 04 01:00:36 PM PDT 24
Finished Apr 04 01:00:37 PM PDT 24
Peak memory 206992 kb
Host smart-d737b2e5-dc63-4686-883f-59b23311cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213595071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.213595071
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1670495033
Short name T635
Test name
Test status
Simulation time 2522567687 ps
CPU time 36.91 seconds
Started Apr 04 01:00:46 PM PDT 24
Finished Apr 04 01:01:23 PM PDT 24
Peak memory 241052 kb
Host smart-873aa3c6-e2b4-41f0-9d85-a3e501d4ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670495033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1670495033
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2610056776
Short name T626
Test name
Test status
Simulation time 6089318994 ps
CPU time 23.87 seconds
Started Apr 04 01:00:45 PM PDT 24
Finished Apr 04 01:01:10 PM PDT 24
Peak memory 218924 kb
Host smart-b8892057-1a03-4120-9307-64869684d93c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610056776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2610056776
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3312789289
Short name T598
Test name
Test status
Simulation time 9226735859 ps
CPU time 49.45 seconds
Started Apr 04 01:00:37 PM PDT 24
Finished Apr 04 01:01:27 PM PDT 24
Peak memory 216732 kb
Host smart-e65ecb47-6a05-4a8d-b207-d98690562a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312789289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3312789289
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3490326203
Short name T643
Test name
Test status
Simulation time 6231298356 ps
CPU time 17.21 seconds
Started Apr 04 01:00:36 PM PDT 24
Finished Apr 04 01:00:53 PM PDT 24
Peak memory 216504 kb
Host smart-e06e63d8-5776-483c-82ee-99b2d3599f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490326203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3490326203
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.300682393
Short name T420
Test name
Test status
Simulation time 56158687 ps
CPU time 0.82 seconds
Started Apr 04 01:00:36 PM PDT 24
Finished Apr 04 01:00:37 PM PDT 24
Peak memory 206572 kb
Host smart-99c7b91a-02b8-4d37-b1d7-df6dd902c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300682393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.300682393
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4293812464
Short name T612
Test name
Test status
Simulation time 194728752 ps
CPU time 1.06 seconds
Started Apr 04 01:00:34 PM PDT 24
Finished Apr 04 01:00:35 PM PDT 24
Peak memory 206756 kb
Host smart-9d9cab60-c81e-466d-b751-1d307a77482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293812464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4293812464
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2323115226
Short name T649
Test name
Test status
Simulation time 46683247 ps
CPU time 0.71 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:00:56 PM PDT 24
Peak memory 204692 kb
Host smart-1cb291c4-d6cc-446f-b74c-4b028fd0cc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323115226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2323115226
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2754102607
Short name T631
Test name
Test status
Simulation time 4035588096 ps
CPU time 11.05 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:01:06 PM PDT 24
Peak memory 233060 kb
Host smart-4a6ca8c2-4b1f-4a53-b5af-90516f0228c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754102607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2754102607
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.344562871
Short name T436
Test name
Test status
Simulation time 25165415 ps
CPU time 0.74 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:00:56 PM PDT 24
Peak memory 205920 kb
Host smart-3851eb9f-8ea5-447b-83ef-c7158551feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344562871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.344562871
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.42317515
Short name T309
Test name
Test status
Simulation time 28647539948 ps
CPU time 107.04 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:02:41 PM PDT 24
Peak memory 250032 kb
Host smart-b3001893-d785-4b34-aa80-8dbab90eac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42317515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.42317515
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.118086922
Short name T59
Test name
Test status
Simulation time 209650489 ps
CPU time 7.14 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:01:02 PM PDT 24
Peak memory 218712 kb
Host smart-7754b068-2873-4af5-a1af-f78d10c493d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118086922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.118086922
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2089004638
Short name T287
Test name
Test status
Simulation time 2765725496 ps
CPU time 9.51 seconds
Started Apr 04 01:00:54 PM PDT 24
Finished Apr 04 01:01:04 PM PDT 24
Peak memory 223344 kb
Host smart-899dee63-097e-4e78-8f0c-08d40db44d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089004638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2089004638
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2926166529
Short name T172
Test name
Test status
Simulation time 438807133 ps
CPU time 3.94 seconds
Started Apr 04 01:00:56 PM PDT 24
Finished Apr 04 01:01:01 PM PDT 24
Peak memory 219284 kb
Host smart-84baf29d-a8d1-40fd-96fd-ca02c2c4dbfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926166529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2926166529
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3936975315
Short name T736
Test name
Test status
Simulation time 190175537 ps
CPU time 2.26 seconds
Started Apr 04 01:00:53 PM PDT 24
Finished Apr 04 01:00:56 PM PDT 24
Peak memory 216568 kb
Host smart-c9c73c6d-3f72-4bd3-846e-934bc12db12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936975315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3936975315
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.129800179
Short name T606
Test name
Test status
Simulation time 7636206249 ps
CPU time 10.63 seconds
Started Apr 04 01:00:55 PM PDT 24
Finished Apr 04 01:01:07 PM PDT 24
Peak memory 216616 kb
Host smart-b5dc0531-8980-4217-a615-af8f61de0d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129800179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.129800179
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.979623299
Short name T669
Test name
Test status
Simulation time 141561755 ps
CPU time 1.53 seconds
Started Apr 04 01:00:55 PM PDT 24
Finished Apr 04 01:00:57 PM PDT 24
Peak memory 216396 kb
Host smart-8e282f03-578f-49ac-bcb6-bd23ede48958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979623299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.979623299
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1650095186
Short name T510
Test name
Test status
Simulation time 164841814 ps
CPU time 0.92 seconds
Started Apr 04 01:00:53 PM PDT 24
Finished Apr 04 01:00:54 PM PDT 24
Peak memory 206880 kb
Host smart-a656bce5-d233-4ae1-a754-fdd33628002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650095186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1650095186
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2216667336
Short name T675
Test name
Test status
Simulation time 11896847 ps
CPU time 0.66 seconds
Started Apr 04 01:01:05 PM PDT 24
Finished Apr 04 01:01:06 PM PDT 24
Peak memory 205384 kb
Host smart-dc98779a-7eb8-4bbc-a832-a0488a86ec6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216667336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2216667336
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1587074085
Short name T757
Test name
Test status
Simulation time 57869296 ps
CPU time 0.76 seconds
Started Apr 04 01:00:55 PM PDT 24
Finished Apr 04 01:00:56 PM PDT 24
Peak memory 205580 kb
Host smart-d24ec318-95c4-46e2-92f7-f36e95fe6cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587074085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1587074085
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2038854491
Short name T630
Test name
Test status
Simulation time 322391277 ps
CPU time 5.4 seconds
Started Apr 04 01:01:07 PM PDT 24
Finished Apr 04 01:01:12 PM PDT 24
Peak memory 218688 kb
Host smart-242b78bd-7569-4c9e-94df-70c6de79482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038854491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2038854491
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3178335550
Short name T473
Test name
Test status
Simulation time 1216324897 ps
CPU time 13.8 seconds
Started Apr 04 01:01:06 PM PDT 24
Finished Apr 04 01:01:20 PM PDT 24
Peak memory 219212 kb
Host smart-a82497d9-19ec-470c-9a26-3b9acf3c85cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3178335550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3178335550
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1324760077
Short name T400
Test name
Test status
Simulation time 7444888831 ps
CPU time 28.73 seconds
Started Apr 04 01:01:07 PM PDT 24
Finished Apr 04 01:01:35 PM PDT 24
Peak memory 216640 kb
Host smart-f3f6cea3-453f-4eb5-8f26-2c865a4da29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324760077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1324760077
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.871442671
Short name T512
Test name
Test status
Simulation time 1110022115 ps
CPU time 7.45 seconds
Started Apr 04 01:01:06 PM PDT 24
Finished Apr 04 01:01:13 PM PDT 24
Peak memory 216288 kb
Host smart-c1891126-8d7a-4431-9e18-32f4d5c262a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871442671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.871442671
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.671355190
Short name T616
Test name
Test status
Simulation time 226569544 ps
CPU time 1.2 seconds
Started Apr 04 01:01:05 PM PDT 24
Finished Apr 04 01:01:07 PM PDT 24
Peak memory 216476 kb
Host smart-1d841bf8-1f73-4ec5-9dd4-1d1bde735b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671355190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.671355190
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.619879256
Short name T511
Test name
Test status
Simulation time 236336690 ps
CPU time 0.89 seconds
Started Apr 04 01:01:06 PM PDT 24
Finished Apr 04 01:01:07 PM PDT 24
Peak memory 205832 kb
Host smart-8bbc9d4d-8013-45f4-ac44-73dbd043b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619879256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.619879256
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.10672469
Short name T29
Test name
Test status
Simulation time 5498014579 ps
CPU time 11.46 seconds
Started Apr 04 01:01:05 PM PDT 24
Finished Apr 04 01:01:17 PM PDT 24
Peak memory 226376 kb
Host smart-30da6a84-4102-4323-9d96-6a5ddfcfc30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10672469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.10672469
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2141188759
Short name T582
Test name
Test status
Simulation time 17661940 ps
CPU time 0.67 seconds
Started Apr 04 01:01:19 PM PDT 24
Finished Apr 04 01:01:20 PM PDT 24
Peak memory 205300 kb
Host smart-b05aedad-57e8-4d3b-9249-ec8cae750ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141188759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2141188759
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3571522904
Short name T486
Test name
Test status
Simulation time 14794350 ps
CPU time 0.76 seconds
Started Apr 04 01:01:04 PM PDT 24
Finished Apr 04 01:01:05 PM PDT 24
Peak memory 205616 kb
Host smart-072e8ec7-7427-450c-9374-65953cb4c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571522904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3571522904
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.170432527
Short name T358
Test name
Test status
Simulation time 1023921227 ps
CPU time 14.07 seconds
Started Apr 04 01:01:21 PM PDT 24
Finished Apr 04 01:01:35 PM PDT 24
Peak memory 232720 kb
Host smart-235c9640-8dc5-4901-a15f-96cae79b7634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170432527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.170432527
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3052443509
Short name T494
Test name
Test status
Simulation time 1979107678 ps
CPU time 21.71 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:40 PM PDT 24
Peak memory 234756 kb
Host smart-25f206c4-7239-4c3e-aff0-d98c7ab1551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052443509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3052443509
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2974797832
Short name T571
Test name
Test status
Simulation time 108376366 ps
CPU time 2.46 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:21 PM PDT 24
Peak memory 216572 kb
Host smart-2e57d1aa-0cc9-43b0-95c7-9e51fd07d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974797832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2974797832
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.503052842
Short name T545
Test name
Test status
Simulation time 5289631884 ps
CPU time 18.43 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:37 PM PDT 24
Peak memory 216496 kb
Host smart-a0f72de3-12fe-4781-912d-3a40e24c19d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503052842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.503052842
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3530263010
Short name T684
Test name
Test status
Simulation time 852627582 ps
CPU time 4.45 seconds
Started Apr 04 01:01:05 PM PDT 24
Finished Apr 04 01:01:10 PM PDT 24
Peak memory 216560 kb
Host smart-9200c165-499a-4f33-9477-4f6259569ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530263010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3530263010
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4198509600
Short name T19
Test name
Test status
Simulation time 111702533 ps
CPU time 1.66 seconds
Started Apr 04 01:01:20 PM PDT 24
Finished Apr 04 01:01:22 PM PDT 24
Peak memory 216936 kb
Host smart-a47c8576-04f6-4a1f-9ddc-d047471aa5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198509600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4198509600
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2206187551
Short name T505
Test name
Test status
Simulation time 129708219 ps
CPU time 0.84 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:19 PM PDT 24
Peak memory 206908 kb
Host smart-4ad00a83-5a96-4737-896e-972831ddf78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206187551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2206187551
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3389303987
Short name T553
Test name
Test status
Simulation time 49556331 ps
CPU time 0.78 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:19 PM PDT 24
Peak memory 206928 kb
Host smart-7712ab0a-0f87-450a-b2d9-6f54e97a213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389303987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3389303987
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2751364248
Short name T191
Test name
Test status
Simulation time 1356241214 ps
CPU time 16.09 seconds
Started Apr 04 01:01:30 PM PDT 24
Finished Apr 04 01:01:46 PM PDT 24
Peak memory 216800 kb
Host smart-cfa9ed93-605d-4d76-a21c-693bb2c2e1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751364248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2751364248
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2784192717
Short name T481
Test name
Test status
Simulation time 2735775726 ps
CPU time 12.8 seconds
Started Apr 04 01:01:29 PM PDT 24
Finished Apr 04 01:01:42 PM PDT 24
Peak memory 231144 kb
Host smart-7e7d6c5e-05fc-4ef7-b870-8bf9cb02c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784192717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2784192717
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2806764178
Short name T262
Test name
Test status
Simulation time 429364505 ps
CPU time 4.33 seconds
Started Apr 04 01:01:28 PM PDT 24
Finished Apr 04 01:01:33 PM PDT 24
Peak memory 223252 kb
Host smart-10aed64c-b56f-44ba-a972-153d8fb455d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806764178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2806764178
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.96238433
Short name T200
Test name
Test status
Simulation time 13641068187 ps
CPU time 39.76 seconds
Started Apr 04 01:01:28 PM PDT 24
Finished Apr 04 01:02:08 PM PDT 24
Peak memory 240868 kb
Host smart-d61ac309-9a9c-43ca-a586-5c9b3ba371b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96238433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.96238433
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2672739047
Short name T645
Test name
Test status
Simulation time 7019288502 ps
CPU time 18.79 seconds
Started Apr 04 01:01:29 PM PDT 24
Finished Apr 04 01:01:48 PM PDT 24
Peak memory 221444 kb
Host smart-21d95f25-bd8c-4711-b126-6118e33155dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2672739047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2672739047
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.762138788
Short name T406
Test name
Test status
Simulation time 9449726054 ps
CPU time 47.09 seconds
Started Apr 04 01:01:17 PM PDT 24
Finished Apr 04 01:02:05 PM PDT 24
Peak memory 216656 kb
Host smart-6d58e67b-ece6-44d9-b252-2edc69646b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762138788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.762138788
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2626174081
Short name T733
Test name
Test status
Simulation time 8052169074 ps
CPU time 17.72 seconds
Started Apr 04 01:01:18 PM PDT 24
Finished Apr 04 01:01:36 PM PDT 24
Peak memory 216664 kb
Host smart-2700ea09-b041-4977-a576-aeed9ed65291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626174081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2626174081
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.306312756
Short name T416
Test name
Test status
Simulation time 552823594 ps
CPU time 2.24 seconds
Started Apr 04 01:01:31 PM PDT 24
Finished Apr 04 01:01:33 PM PDT 24
Peak memory 216572 kb
Host smart-3ed5e8de-cba5-4605-be16-25652c01c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306312756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.306312756
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2261710445
Short name T710
Test name
Test status
Simulation time 96290463 ps
CPU time 0.98 seconds
Started Apr 04 01:01:30 PM PDT 24
Finished Apr 04 01:01:31 PM PDT 24
Peak memory 206848 kb
Host smart-a700e2f3-9087-49c4-9f56-67469750b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261710445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2261710445
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3776331005
Short name T579
Test name
Test status
Simulation time 11569318 ps
CPU time 0.71 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:47 PM PDT 24
Peak memory 205304 kb
Host smart-a50a91c3-2be3-4f31-90f7-125064d138e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776331005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3776331005
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2346863971
Short name T732
Test name
Test status
Simulation time 15707741 ps
CPU time 0.78 seconds
Started Apr 04 01:01:36 PM PDT 24
Finished Apr 04 01:01:37 PM PDT 24
Peak memory 206480 kb
Host smart-5e267248-806c-4f72-b538-f61ad5e38db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346863971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2346863971
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3597298392
Short name T301
Test name
Test status
Simulation time 1129040465 ps
CPU time 23.2 seconds
Started Apr 04 01:01:38 PM PDT 24
Finished Apr 04 01:02:02 PM PDT 24
Peak memory 234000 kb
Host smart-f328c877-e927-4f37-ae6c-2af78e99ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597298392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3597298392
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1054532322
Short name T339
Test name
Test status
Simulation time 12760213319 ps
CPU time 128.32 seconds
Started Apr 04 01:01:35 PM PDT 24
Finished Apr 04 01:03:43 PM PDT 24
Peak memory 238140 kb
Host smart-fd6cf6a8-9799-48c1-a3c1-fac8fa0438fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054532322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1054532322
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4155332488
Short name T333
Test name
Test status
Simulation time 7474257243 ps
CPU time 8.7 seconds
Started Apr 04 01:01:37 PM PDT 24
Finished Apr 04 01:01:45 PM PDT 24
Peak memory 233808 kb
Host smart-67b8df9d-3f41-4cd5-8295-97eff82b5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155332488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4155332488
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.654622579
Short name T483
Test name
Test status
Simulation time 2288225176 ps
CPU time 7.02 seconds
Started Apr 04 01:01:35 PM PDT 24
Finished Apr 04 01:01:42 PM PDT 24
Peak memory 222996 kb
Host smart-4ad48e20-b53d-45da-b463-0693d1afb7df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=654622579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.654622579
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.18702820
Short name T734
Test name
Test status
Simulation time 8382165306 ps
CPU time 6.25 seconds
Started Apr 04 01:01:35 PM PDT 24
Finished Apr 04 01:01:42 PM PDT 24
Peak memory 216468 kb
Host smart-0f57ccde-07be-4957-8ac2-ec6f4a2a6015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18702820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.18702820
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3421204263
Short name T410
Test name
Test status
Simulation time 196456517 ps
CPU time 7.77 seconds
Started Apr 04 01:01:36 PM PDT 24
Finished Apr 04 01:01:44 PM PDT 24
Peak memory 216680 kb
Host smart-05465316-c5f0-455f-bfa2-dad4c1d011bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421204263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3421204263
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3353880409
Short name T495
Test name
Test status
Simulation time 20942560 ps
CPU time 0.77 seconds
Started Apr 04 01:01:37 PM PDT 24
Finished Apr 04 01:01:38 PM PDT 24
Peak memory 205848 kb
Host smart-69ae5293-c627-47f9-b7d4-2d7725ff2eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353880409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3353880409
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3224641934
Short name T457
Test name
Test status
Simulation time 15121003 ps
CPU time 0.75 seconds
Started Apr 04 01:02:01 PM PDT 24
Finished Apr 04 01:02:01 PM PDT 24
Peak memory 205644 kb
Host smart-83c9a074-7a39-4136-823a-1448f3139c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224641934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3224641934
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1992132339
Short name T227
Test name
Test status
Simulation time 758493589 ps
CPU time 9.9 seconds
Started Apr 04 01:01:49 PM PDT 24
Finished Apr 04 01:02:00 PM PDT 24
Peak memory 232888 kb
Host smart-651c4779-3b34-44bd-b7bb-ba73a6e632ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992132339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1992132339
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2427226151
Short name T442
Test name
Test status
Simulation time 22764724 ps
CPU time 0.73 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:46 PM PDT 24
Peak memory 205624 kb
Host smart-8e8fb096-177e-4a59-a864-a052e7a5de70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427226151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2427226151
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3276794389
Short name T725
Test name
Test status
Simulation time 67352141 ps
CPU time 2.37 seconds
Started Apr 04 01:01:49 PM PDT 24
Finished Apr 04 01:01:52 PM PDT 24
Peak memory 222080 kb
Host smart-5a8b8dd7-2aa4-42fe-a218-3d9456a856ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276794389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3276794389
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3734108345
Short name T220
Test name
Test status
Simulation time 151708754 ps
CPU time 2.8 seconds
Started Apr 04 01:01:48 PM PDT 24
Finished Apr 04 01:01:51 PM PDT 24
Peak memory 222836 kb
Host smart-c9421782-ca0a-4d0a-af67-79aafe356248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734108345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3734108345
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3819897330
Short name T449
Test name
Test status
Simulation time 445915816 ps
CPU time 5.89 seconds
Started Apr 04 01:01:47 PM PDT 24
Finished Apr 04 01:01:53 PM PDT 24
Peak memory 218712 kb
Host smart-f7369bbe-3cc9-44c8-b752-ae05fcc67686
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819897330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3819897330
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3766870959
Short name T446
Test name
Test status
Simulation time 5757851306 ps
CPU time 8.22 seconds
Started Apr 04 01:01:45 PM PDT 24
Finished Apr 04 01:01:53 PM PDT 24
Peak memory 216508 kb
Host smart-0e1d43f6-5dbc-4fd0-a363-73473283b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766870959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3766870959
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4127643913
Short name T706
Test name
Test status
Simulation time 620636426 ps
CPU time 4.84 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:51 PM PDT 24
Peak memory 216572 kb
Host smart-03558428-f1b0-4d83-8b79-b189076f9d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127643913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4127643913
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3358074510
Short name T637
Test name
Test status
Simulation time 903434298 ps
CPU time 2.94 seconds
Started Apr 04 01:01:45 PM PDT 24
Finished Apr 04 01:01:48 PM PDT 24
Peak memory 216576 kb
Host smart-878f8b68-b676-4f80-b337-d3e7a9afe95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358074510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3358074510
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3025251011
Short name T563
Test name
Test status
Simulation time 344079866 ps
CPU time 0.87 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:47 PM PDT 24
Peak memory 205876 kb
Host smart-d2432846-138f-403e-8216-7e52f8525bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025251011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3025251011
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1634891229
Short name T233
Test name
Test status
Simulation time 1726015819 ps
CPU time 4.5 seconds
Started Apr 04 01:01:46 PM PDT 24
Finished Apr 04 01:01:50 PM PDT 24
Peak memory 219468 kb
Host smart-593ade08-4d85-4044-9f16-68f41e9b33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634891229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1634891229
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1871440348
Short name T435
Test name
Test status
Simulation time 83560351 ps
CPU time 0.74 seconds
Started Apr 04 12:56:51 PM PDT 24
Finished Apr 04 12:56:52 PM PDT 24
Peak memory 205368 kb
Host smart-0241cd2a-f98c-42cc-8561-dca348fc52b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871440348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
871440348
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2329909896
Short name T604
Test name
Test status
Simulation time 15660261 ps
CPU time 0.78 seconds
Started Apr 04 12:56:42 PM PDT 24
Finished Apr 04 12:56:43 PM PDT 24
Peak memory 206908 kb
Host smart-d54691ae-e202-4ad5-ae06-ce1b35dec444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329909896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2329909896
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.451560359
Short name T380
Test name
Test status
Simulation time 9687667168 ps
CPU time 85.56 seconds
Started Apr 04 12:56:52 PM PDT 24
Finished Apr 04 12:58:18 PM PDT 24
Peak memory 241240 kb
Host smart-ff444ff7-0243-4a64-9bc1-cf867dad02b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451560359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.451560359
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4276355333
Short name T103
Test name
Test status
Simulation time 5705928511 ps
CPU time 25.8 seconds
Started Apr 04 12:56:50 PM PDT 24
Finished Apr 04 12:57:15 PM PDT 24
Peak memory 223056 kb
Host smart-a2fc2098-e044-467f-b974-7d92d57ea2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276355333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4276355333
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1999792056
Short name T661
Test name
Test status
Simulation time 42108203 ps
CPU time 1.05 seconds
Started Apr 04 12:56:41 PM PDT 24
Finished Apr 04 12:56:42 PM PDT 24
Peak memory 218196 kb
Host smart-2c93248b-e638-4080-b01c-e270c8a9a1e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999792056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1999792056
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4233418085
Short name T249
Test name
Test status
Simulation time 1057377824 ps
CPU time 13.78 seconds
Started Apr 04 12:56:51 PM PDT 24
Finished Apr 04 12:57:05 PM PDT 24
Peak memory 238616 kb
Host smart-afa98c40-ba6c-4cf8-aa54-3559d66b53a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233418085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4233418085
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1166460565
Short name T41
Test name
Test status
Simulation time 34069179 ps
CPU time 0.75 seconds
Started Apr 04 12:56:42 PM PDT 24
Finished Apr 04 12:56:43 PM PDT 24
Peak memory 216392 kb
Host smart-8a3d103f-191c-4bd6-8f8a-049348fa0410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166460565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1166460565
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.990215897
Short name T433
Test name
Test status
Simulation time 6632599657 ps
CPU time 20.89 seconds
Started Apr 04 12:56:51 PM PDT 24
Finished Apr 04 12:57:12 PM PDT 24
Peak memory 221904 kb
Host smart-4bcf14ad-0fd1-46cf-a6b3-7caa4e3d7029
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=990215897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.990215897
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3306035641
Short name T51
Test name
Test status
Simulation time 347519114 ps
CPU time 1.17 seconds
Started Apr 04 12:56:50 PM PDT 24
Finished Apr 04 12:56:51 PM PDT 24
Peak memory 235508 kb
Host smart-8222233c-2225-45a2-aea0-843655f115dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306035641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3306035641
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.14295727
Short name T386
Test name
Test status
Simulation time 2686399381 ps
CPU time 15.76 seconds
Started Apr 04 12:56:42 PM PDT 24
Finished Apr 04 12:56:58 PM PDT 24
Peak memory 216520 kb
Host smart-70dde11c-438e-47a4-8dca-dd34b71bd09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14295727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.14295727
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1253391990
Short name T62
Test name
Test status
Simulation time 12438362123 ps
CPU time 16.71 seconds
Started Apr 04 12:56:42 PM PDT 24
Finished Apr 04 12:56:59 PM PDT 24
Peak memory 216668 kb
Host smart-54daa554-9d26-4386-8290-f23f97b6c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253391990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1253391990
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1346914192
Short name T600
Test name
Test status
Simulation time 66176365 ps
CPU time 1.47 seconds
Started Apr 04 12:56:52 PM PDT 24
Finished Apr 04 12:56:53 PM PDT 24
Peak memory 216564 kb
Host smart-d8e11b15-2de4-44d2-83df-1da1c3042753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346914192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1346914192
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2482569606
Short name T444
Test name
Test status
Simulation time 27904105 ps
CPU time 0.77 seconds
Started Apr 04 12:56:43 PM PDT 24
Finished Apr 04 12:56:44 PM PDT 24
Peak memory 205784 kb
Host smart-10b15cdc-bcbc-4441-9d41-e7eed8405992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482569606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2482569606
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4028011173
Short name T663
Test name
Test status
Simulation time 15747671 ps
CPU time 0.71 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:18 PM PDT 24
Peak memory 205252 kb
Host smart-cfd63255-dab8-46b4-9ad6-eb3ed305098b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028011173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4028011173
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1041247991
Short name T28
Test name
Test status
Simulation time 65539146 ps
CPU time 3.33 seconds
Started Apr 04 01:02:17 PM PDT 24
Finished Apr 04 01:02:20 PM PDT 24
Peak memory 224628 kb
Host smart-e8bdc4ee-b702-4b3b-814f-df6080e66afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041247991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1041247991
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3539455793
Short name T429
Test name
Test status
Simulation time 62871388 ps
CPU time 0.81 seconds
Started Apr 04 01:02:03 PM PDT 24
Finished Apr 04 01:02:04 PM PDT 24
Peak memory 206696 kb
Host smart-0b19ba0d-aaa2-46c4-86c6-f58ae700da8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539455793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3539455793
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1213176197
Short name T367
Test name
Test status
Simulation time 2014252456 ps
CPU time 10.48 seconds
Started Apr 04 01:02:20 PM PDT 24
Finished Apr 04 01:02:30 PM PDT 24
Peak memory 224704 kb
Host smart-081a5677-f155-40d9-9b48-388cba14e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213176197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1213176197
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.829195491
Short name T192
Test name
Test status
Simulation time 3924492399 ps
CPU time 14.08 seconds
Started Apr 04 01:02:02 PM PDT 24
Finished Apr 04 01:02:16 PM PDT 24
Peak memory 238032 kb
Host smart-2bb1de41-a4f9-4b98-99df-765a06943a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829195491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.829195491
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.43569601
Short name T104
Test name
Test status
Simulation time 998016178 ps
CPU time 11.75 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:29 PM PDT 24
Peak memory 222348 kb
Host smart-1a9ff58e-b26d-4c02-8da7-e75298c8cabb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=43569601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direc
t.43569601
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.357967878
Short name T575
Test name
Test status
Simulation time 361618882 ps
CPU time 5.2 seconds
Started Apr 04 01:02:01 PM PDT 24
Finished Apr 04 01:02:07 PM PDT 24
Peak memory 216620 kb
Host smart-9a56b3fc-4580-4966-a4ab-aa2e9e9757e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357967878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.357967878
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3255201680
Short name T471
Test name
Test status
Simulation time 4743594137 ps
CPU time 10.07 seconds
Started Apr 04 01:02:02 PM PDT 24
Finished Apr 04 01:02:13 PM PDT 24
Peak memory 216624 kb
Host smart-60135aab-b604-4524-8b35-9d65e8b32261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255201680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3255201680
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2446494261
Short name T469
Test name
Test status
Simulation time 248133200 ps
CPU time 1.83 seconds
Started Apr 04 01:02:02 PM PDT 24
Finished Apr 04 01:02:04 PM PDT 24
Peak memory 216520 kb
Host smart-3779af3b-32bf-4773-a081-7e421679d3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446494261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2446494261
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2127098951
Short name T580
Test name
Test status
Simulation time 62365160 ps
CPU time 0.77 seconds
Started Apr 04 01:02:03 PM PDT 24
Finished Apr 04 01:02:04 PM PDT 24
Peak memory 205864 kb
Host smart-eea01122-1454-464f-882e-911a3915654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127098951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2127098951
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1918710046
Short name T544
Test name
Test status
Simulation time 18182534 ps
CPU time 0.69 seconds
Started Apr 04 01:02:32 PM PDT 24
Finished Apr 04 01:02:33 PM PDT 24
Peak memory 204836 kb
Host smart-8cc272fb-df0b-4e66-bb81-cf9e524dc941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918710046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1918710046
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3009102088
Short name T720
Test name
Test status
Simulation time 33986916 ps
CPU time 0.76 seconds
Started Apr 04 01:02:19 PM PDT 24
Finished Apr 04 01:02:20 PM PDT 24
Peak memory 205876 kb
Host smart-45ff421d-6f5d-43e7-bd4b-4668e6d0de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009102088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3009102088
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3632105295
Short name T311
Test name
Test status
Simulation time 50973514733 ps
CPU time 168.73 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:05:06 PM PDT 24
Peak memory 251292 kb
Host smart-df14f8e0-dbf5-4e47-b376-75f4424dd59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632105295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3632105295
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1713454214
Short name T132
Test name
Test status
Simulation time 127132127 ps
CPU time 2.2 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:18 PM PDT 24
Peak memory 222668 kb
Host smart-aa7124e7-3fe7-4a66-a599-16199c9559ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713454214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1713454214
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1887177298
Short name T44
Test name
Test status
Simulation time 29151164165 ps
CPU time 62.27 seconds
Started Apr 04 01:02:17 PM PDT 24
Finished Apr 04 01:03:20 PM PDT 24
Peak memory 236144 kb
Host smart-d7006214-760e-4745-b7ae-07552ccfa191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887177298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1887177298
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2776644165
Short name T238
Test name
Test status
Simulation time 224943313 ps
CPU time 2.83 seconds
Started Apr 04 01:02:17 PM PDT 24
Finished Apr 04 01:02:20 PM PDT 24
Peak memory 222560 kb
Host smart-60afe3ce-bb88-401d-a17d-edee634be798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776644165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2776644165
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4156479212
Short name T653
Test name
Test status
Simulation time 1117480838 ps
CPU time 13.87 seconds
Started Apr 04 01:02:18 PM PDT 24
Finished Apr 04 01:02:32 PM PDT 24
Peak memory 221820 kb
Host smart-16d554e7-eeae-4be0-bfcc-4360b6a0ee6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156479212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4156479212
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2804457582
Short name T68
Test name
Test status
Simulation time 1360445870 ps
CPU time 8.27 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:25 PM PDT 24
Peak memory 216484 kb
Host smart-894ef389-718b-442e-889a-2de446b08748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804457582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2804457582
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.678324865
Short name T537
Test name
Test status
Simulation time 2626870633 ps
CPU time 14.43 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:30 PM PDT 24
Peak memory 216604 kb
Host smart-616451f7-4066-4ecc-a46f-319b541a6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678324865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.678324865
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.418746532
Short name T409
Test name
Test status
Simulation time 90481252 ps
CPU time 2.33 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:19 PM PDT 24
Peak memory 216500 kb
Host smart-26fdbfbe-ac00-4798-b0ab-632f73da414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418746532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.418746532
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2888702421
Short name T64
Test name
Test status
Simulation time 102760578 ps
CPU time 1.09 seconds
Started Apr 04 01:02:17 PM PDT 24
Finished Apr 04 01:02:19 PM PDT 24
Peak memory 206904 kb
Host smart-e1d54fc6-ab12-4f48-a866-1ac4d6a161b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888702421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2888702421
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4143737496
Short name T334
Test name
Test status
Simulation time 11903080853 ps
CPU time 36.05 seconds
Started Apr 04 01:02:16 PM PDT 24
Finished Apr 04 01:02:52 PM PDT 24
Peak memory 232924 kb
Host smart-ec3cf4f7-9d7d-455f-94de-62b29f5e3bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143737496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4143737496
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.417688996
Short name T608
Test name
Test status
Simulation time 13604070 ps
CPU time 0.71 seconds
Started Apr 04 01:02:32 PM PDT 24
Finished Apr 04 01:02:33 PM PDT 24
Peak memory 205396 kb
Host smart-54ecec06-506c-4763-b6e1-71a0d20f0db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417688996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.417688996
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2714357725
Short name T521
Test name
Test status
Simulation time 79710492 ps
CPU time 0.82 seconds
Started Apr 04 01:02:34 PM PDT 24
Finished Apr 04 01:02:35 PM PDT 24
Peak memory 206560 kb
Host smart-98650699-003d-40a8-b404-e2f039a0b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714357725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2714357725
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2148719131
Short name T361
Test name
Test status
Simulation time 5230019398 ps
CPU time 28.69 seconds
Started Apr 04 01:02:33 PM PDT 24
Finished Apr 04 01:03:02 PM PDT 24
Peak memory 240484 kb
Host smart-7abdf122-c9a1-4433-95c3-25bc5df1ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148719131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2148719131
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1740135007
Short name T569
Test name
Test status
Simulation time 184391722 ps
CPU time 3.87 seconds
Started Apr 04 01:02:34 PM PDT 24
Finished Apr 04 01:02:38 PM PDT 24
Peak memory 219976 kb
Host smart-c53446e8-ff65-42db-925c-322f16a6e66e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1740135007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1740135007
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2688791805
Short name T670
Test name
Test status
Simulation time 9280086102 ps
CPU time 12.63 seconds
Started Apr 04 01:02:33 PM PDT 24
Finished Apr 04 01:02:45 PM PDT 24
Peak memory 216620 kb
Host smart-7d0b3247-b38f-441d-951c-7d1072700e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688791805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2688791805
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1924669331
Short name T741
Test name
Test status
Simulation time 7251404412 ps
CPU time 20.76 seconds
Started Apr 04 01:02:31 PM PDT 24
Finished Apr 04 01:02:52 PM PDT 24
Peak memory 216624 kb
Host smart-270cb4c7-2147-4ea5-9723-fea228ee8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924669331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1924669331
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3612980195
Short name T570
Test name
Test status
Simulation time 289252374 ps
CPU time 6.39 seconds
Started Apr 04 01:02:33 PM PDT 24
Finished Apr 04 01:02:40 PM PDT 24
Peak memory 216484 kb
Host smart-2876f028-a17c-4b36-8ca1-0499cacebabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612980195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3612980195
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.296828840
Short name T466
Test name
Test status
Simulation time 275725456 ps
CPU time 0.87 seconds
Started Apr 04 01:02:33 PM PDT 24
Finished Apr 04 01:02:34 PM PDT 24
Peak memory 206872 kb
Host smart-b727330e-8f67-417d-a241-0f78d5c6cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296828840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.296828840
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2511311940
Short name T270
Test name
Test status
Simulation time 4890218200 ps
CPU time 5.53 seconds
Started Apr 04 01:02:33 PM PDT 24
Finished Apr 04 01:02:39 PM PDT 24
Peak memory 223240 kb
Host smart-34fbc419-deb1-48ca-ad40-76f08a9de4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511311940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2511311940
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3997416012
Short name T543
Test name
Test status
Simulation time 79552192 ps
CPU time 0.69 seconds
Started Apr 04 01:02:41 PM PDT 24
Finished Apr 04 01:02:42 PM PDT 24
Peak memory 205856 kb
Host smart-1930c352-f17e-4484-811e-662b68eeb3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997416012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3997416012
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.550449738
Short name T656
Test name
Test status
Simulation time 14521120 ps
CPU time 0.75 seconds
Started Apr 04 01:02:36 PM PDT 24
Finished Apr 04 01:02:37 PM PDT 24
Peak memory 205496 kb
Host smart-97855399-d016-4a66-b645-97742892012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550449738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.550449738
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.286449723
Short name T688
Test name
Test status
Simulation time 3121388288 ps
CPU time 41.18 seconds
Started Apr 04 01:02:41 PM PDT 24
Finished Apr 04 01:03:22 PM PDT 24
Peak memory 241156 kb
Host smart-28c89645-5adc-4dc0-959c-b5d48efa3b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286449723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.286449723
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.92861143
Short name T698
Test name
Test status
Simulation time 8991051107 ps
CPU time 22.42 seconds
Started Apr 04 01:02:41 PM PDT 24
Finished Apr 04 01:03:04 PM PDT 24
Peak memory 221516 kb
Host smart-6febae25-193a-4cda-a695-cab2923e8747
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=92861143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.92861143
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.559863390
Short name T65
Test name
Test status
Simulation time 30499789526 ps
CPU time 39.35 seconds
Started Apr 04 01:02:35 PM PDT 24
Finished Apr 04 01:03:14 PM PDT 24
Peak memory 216464 kb
Host smart-e6be1f71-03ad-4b7a-ae9b-22508574aea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559863390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.559863390
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.982720376
Short name T702
Test name
Test status
Simulation time 1944137136 ps
CPU time 3.4 seconds
Started Apr 04 01:02:36 PM PDT 24
Finished Apr 04 01:02:40 PM PDT 24
Peak memory 216368 kb
Host smart-78facb4e-719a-46e6-bc1c-70fe04e0df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982720376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.982720376
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.11020051
Short name T701
Test name
Test status
Simulation time 46001012 ps
CPU time 0.89 seconds
Started Apr 04 01:02:35 PM PDT 24
Finished Apr 04 01:02:36 PM PDT 24
Peak memory 206676 kb
Host smart-0d26764d-4d36-44ea-9106-2040f7ea75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11020051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.11020051
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3382158333
Short name T523
Test name
Test status
Simulation time 131824239 ps
CPU time 0.89 seconds
Started Apr 04 01:02:35 PM PDT 24
Finished Apr 04 01:02:36 PM PDT 24
Peak memory 205752 kb
Host smart-c4d2bc24-f369-44ce-a333-f374cd078844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382158333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3382158333
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1667114891
Short name T431
Test name
Test status
Simulation time 122662035 ps
CPU time 0.68 seconds
Started Apr 04 01:02:55 PM PDT 24
Finished Apr 04 01:02:55 PM PDT 24
Peak memory 205376 kb
Host smart-ac1b3d67-8361-477a-a1d5-ee373e77a58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667114891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1667114891
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2532045619
Short name T212
Test name
Test status
Simulation time 609063419 ps
CPU time 3.18 seconds
Started Apr 04 01:02:53 PM PDT 24
Finished Apr 04 01:02:57 PM PDT 24
Peak memory 218840 kb
Host smart-fb50c476-e3bf-4f61-8d28-d4940347a10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532045619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2532045619
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2346027652
Short name T434
Test name
Test status
Simulation time 18313890 ps
CPU time 0.76 seconds
Started Apr 04 01:02:44 PM PDT 24
Finished Apr 04 01:02:45 PM PDT 24
Peak memory 206676 kb
Host smart-8ee3f387-e827-4728-a6fa-0e0866ab9681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346027652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2346027652
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_intercept.23460499
Short name T329
Test name
Test status
Simulation time 16462588356 ps
CPU time 35.4 seconds
Started Apr 04 01:02:52 PM PDT 24
Finished Apr 04 01:03:27 PM PDT 24
Peak memory 224624 kb
Host smart-8820fa10-6306-488f-8e2a-a708b281b3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23460499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.23460499
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3670654428
Short name T204
Test name
Test status
Simulation time 604537828 ps
CPU time 4.92 seconds
Started Apr 04 01:02:52 PM PDT 24
Finished Apr 04 01:02:58 PM PDT 24
Peak memory 222448 kb
Host smart-4a26ecf7-9dbe-41de-a9a8-95a535f83f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670654428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3670654428
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.233806110
Short name T703
Test name
Test status
Simulation time 1278765220 ps
CPU time 9.24 seconds
Started Apr 04 01:02:53 PM PDT 24
Finished Apr 04 01:03:03 PM PDT 24
Peak memory 223160 kb
Host smart-114a7145-79ed-4aa6-a5f4-aa85b826b206
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233806110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.233806110
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2615936620
Short name T507
Test name
Test status
Simulation time 251212370042 ps
CPU time 33.1 seconds
Started Apr 04 01:02:45 PM PDT 24
Finished Apr 04 01:03:18 PM PDT 24
Peak memory 216592 kb
Host smart-7a07878d-7ba5-40f6-b866-baf5afe717f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615936620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2615936620
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4034528307
Short name T55
Test name
Test status
Simulation time 121312697 ps
CPU time 1.87 seconds
Started Apr 04 01:02:54 PM PDT 24
Finished Apr 04 01:02:56 PM PDT 24
Peak memory 208284 kb
Host smart-ba466949-b208-407d-94c6-d70c0d5f45bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034528307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4034528307
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.434825309
Short name T644
Test name
Test status
Simulation time 305086538 ps
CPU time 1.05 seconds
Started Apr 04 01:02:53 PM PDT 24
Finished Apr 04 01:02:54 PM PDT 24
Peak memory 206892 kb
Host smart-79588fc1-8a2a-4298-a25f-0bf6b61aeb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434825309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.434825309
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.668151052
Short name T225
Test name
Test status
Simulation time 2042366170 ps
CPU time 8.02 seconds
Started Apr 04 01:02:53 PM PDT 24
Finished Apr 04 01:03:01 PM PDT 24
Peak memory 221812 kb
Host smart-df11907c-dbe3-4ea9-8fd4-e5b74824ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668151052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.668151052
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2532254625
Short name T658
Test name
Test status
Simulation time 58463383 ps
CPU time 0.72 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:14 PM PDT 24
Peak memory 205424 kb
Host smart-e22fe080-2fa9-41c7-91fb-1c063f6bafc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532254625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2532254625
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2207502402
Short name T750
Test name
Test status
Simulation time 163779740 ps
CPU time 0.78 seconds
Started Apr 04 01:02:53 PM PDT 24
Finished Apr 04 01:02:54 PM PDT 24
Peak memory 206984 kb
Host smart-680a3e87-8894-4c13-8888-c4d352c2cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207502402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2207502402
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2581838448
Short name T614
Test name
Test status
Simulation time 7165772637 ps
CPU time 39.8 seconds
Started Apr 04 01:03:02 PM PDT 24
Finished Apr 04 01:03:42 PM PDT 24
Peak memory 232976 kb
Host smart-00bee7b7-d473-4ba4-9e08-f6fd80d7e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581838448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2581838448
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3286072964
Short name T454
Test name
Test status
Simulation time 216018045 ps
CPU time 4.27 seconds
Started Apr 04 01:03:02 PM PDT 24
Finished Apr 04 01:03:06 PM PDT 24
Peak memory 223464 kb
Host smart-8f7f0531-46e1-4d71-a134-58cfc803088c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286072964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3286072964
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1155166356
Short name T451
Test name
Test status
Simulation time 3823549825 ps
CPU time 7.85 seconds
Started Apr 04 01:03:06 PM PDT 24
Finished Apr 04 01:03:14 PM PDT 24
Peak memory 222716 kb
Host smart-657729d8-9c58-4742-ad9e-fe0d986684b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1155166356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1155166356
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.403440819
Short name T716
Test name
Test status
Simulation time 18622351445 ps
CPU time 17.96 seconds
Started Apr 04 01:03:00 PM PDT 24
Finished Apr 04 01:03:18 PM PDT 24
Peak memory 216640 kb
Host smart-a3b9e3d0-af3d-48fe-a3b9-62f97799f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403440819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.403440819
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.591785396
Short name T468
Test name
Test status
Simulation time 5185506167 ps
CPU time 5.19 seconds
Started Apr 04 01:03:01 PM PDT 24
Finished Apr 04 01:03:07 PM PDT 24
Peak memory 216648 kb
Host smart-b2761073-8d48-4ecb-9954-7877252d855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591785396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.591785396
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1519661820
Short name T590
Test name
Test status
Simulation time 139134413 ps
CPU time 1.94 seconds
Started Apr 04 01:03:06 PM PDT 24
Finished Apr 04 01:03:08 PM PDT 24
Peak memory 216564 kb
Host smart-200054e8-3ae3-4c4d-9b3d-9ad53b211629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519661820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1519661820
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.443289108
Short name T636
Test name
Test status
Simulation time 24946790 ps
CPU time 0.77 seconds
Started Apr 04 01:02:59 PM PDT 24
Finished Apr 04 01:03:01 PM PDT 24
Peak memory 205884 kb
Host smart-41810ef8-8332-46e2-ba62-453f3194aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443289108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.443289108
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2675569324
Short name T95
Test name
Test status
Simulation time 323793097 ps
CPU time 2.87 seconds
Started Apr 04 01:03:02 PM PDT 24
Finished Apr 04 01:03:05 PM PDT 24
Peak memory 223404 kb
Host smart-33f0d666-66d5-4a92-a54a-f641be396649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675569324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2675569324
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2623683298
Short name T450
Test name
Test status
Simulation time 16563904 ps
CPU time 0.76 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:03:25 PM PDT 24
Peak memory 205280 kb
Host smart-f64abe02-f656-474c-b5a6-1db8d037b3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623683298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2623683298
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4154379351
Short name T465
Test name
Test status
Simulation time 19520225 ps
CPU time 0.82 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:15 PM PDT 24
Peak memory 206556 kb
Host smart-70abc879-fd91-46a8-ba35-e513bce2d94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154379351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4154379351
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2959786095
Short name T652
Test name
Test status
Simulation time 646741016 ps
CPU time 22.63 seconds
Started Apr 04 01:03:22 PM PDT 24
Finished Apr 04 01:03:46 PM PDT 24
Peak memory 248492 kb
Host smart-d3357ef2-2e38-4e3d-b525-31228d28c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959786095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2959786095
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4096497208
Short name T101
Test name
Test status
Simulation time 6969719890 ps
CPU time 16.43 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:29 PM PDT 24
Peak memory 224032 kb
Host smart-4c8bf617-eaf3-48e5-8ed9-56282354a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096497208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4096497208
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2709986821
Short name T712
Test name
Test status
Simulation time 167290212 ps
CPU time 4.11 seconds
Started Apr 04 01:03:22 PM PDT 24
Finished Apr 04 01:03:28 PM PDT 24
Peak memory 222916 kb
Host smart-5c338a2b-2d0e-42c8-9a38-f78a72008c17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2709986821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2709986821
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3677843857
Short name T395
Test name
Test status
Simulation time 1837322363 ps
CPU time 21.05 seconds
Started Apr 04 01:03:12 PM PDT 24
Finished Apr 04 01:03:34 PM PDT 24
Peak memory 216664 kb
Host smart-76cc78c7-6468-415b-8c3c-cf8bb9a57309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677843857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3677843857
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.982291086
Short name T490
Test name
Test status
Simulation time 49229254967 ps
CPU time 29.14 seconds
Started Apr 04 01:03:12 PM PDT 24
Finished Apr 04 01:03:42 PM PDT 24
Peak memory 216592 kb
Host smart-ac14ba21-3400-43c9-b6e8-4030c6c72d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982291086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.982291086
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3208488195
Short name T418
Test name
Test status
Simulation time 332093696 ps
CPU time 3.8 seconds
Started Apr 04 01:03:12 PM PDT 24
Finished Apr 04 01:03:16 PM PDT 24
Peak memory 216684 kb
Host smart-59ea6247-2d96-466b-af5c-a05052474c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208488195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3208488195
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1906724120
Short name T456
Test name
Test status
Simulation time 200687382 ps
CPU time 1.21 seconds
Started Apr 04 01:03:13 PM PDT 24
Finished Apr 04 01:03:14 PM PDT 24
Peak memory 206812 kb
Host smart-2e3b0e84-5279-429f-9b5e-c5213ed71983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906724120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1906724120
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3179684924
Short name T30
Test name
Test status
Simulation time 37174535 ps
CPU time 0.7 seconds
Started Apr 04 01:03:34 PM PDT 24
Finished Apr 04 01:03:35 PM PDT 24
Peak memory 205388 kb
Host smart-cca44926-5677-4844-84ce-8b8e73d977a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179684924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3179684924
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2605183184
Short name T705
Test name
Test status
Simulation time 16284776 ps
CPU time 0.77 seconds
Started Apr 04 01:03:22 PM PDT 24
Finished Apr 04 01:03:24 PM PDT 24
Peak memory 206536 kb
Host smart-c0a5d24c-c8cc-4f15-99fd-f1a023124e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605183184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2605183184
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3165267212
Short name T61
Test name
Test status
Simulation time 16929168674 ps
CPU time 111.63 seconds
Started Apr 04 01:03:35 PM PDT 24
Finished Apr 04 01:05:27 PM PDT 24
Peak memory 241216 kb
Host smart-cc8c8a4a-39a4-4cde-a205-436ad8adf936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165267212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3165267212
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1642751582
Short name T281
Test name
Test status
Simulation time 49968675618 ps
CPU time 99.67 seconds
Started Apr 04 01:03:24 PM PDT 24
Finished Apr 04 01:05:04 PM PDT 24
Peak memory 219996 kb
Host smart-578fe734-8f27-4d40-9a74-be8803c06380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642751582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1642751582
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3816773214
Short name T535
Test name
Test status
Simulation time 1135915449 ps
CPU time 10.24 seconds
Started Apr 04 01:03:34 PM PDT 24
Finished Apr 04 01:03:45 PM PDT 24
Peak memory 220056 kb
Host smart-3a883fe7-b51a-4b58-ae98-32eb0a8de37e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816773214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3816773214
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4031375612
Short name T393
Test name
Test status
Simulation time 1747478806 ps
CPU time 17.86 seconds
Started Apr 04 01:03:24 PM PDT 24
Finished Apr 04 01:03:42 PM PDT 24
Peak memory 216700 kb
Host smart-df3b9c73-294a-4029-8ced-dfec7570e32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031375612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4031375612
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.176773177
Short name T686
Test name
Test status
Simulation time 1793502944 ps
CPU time 1.96 seconds
Started Apr 04 01:03:24 PM PDT 24
Finished Apr 04 01:03:27 PM PDT 24
Peak memory 206992 kb
Host smart-f07822bd-d6dc-4c17-b53e-e4c8e59fe16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176773177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.176773177
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1248657543
Short name T577
Test name
Test status
Simulation time 291502706 ps
CPU time 1.8 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:03:26 PM PDT 24
Peak memory 216376 kb
Host smart-7225f474-e86c-446e-897c-f555c355c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248657543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1248657543
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2581000737
Short name T478
Test name
Test status
Simulation time 145403489 ps
CPU time 1.22 seconds
Started Apr 04 01:03:25 PM PDT 24
Finished Apr 04 01:03:27 PM PDT 24
Peak memory 206752 kb
Host smart-cac61e98-ab84-4594-983d-195da691ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581000737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2581000737
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.90582916
Short name T261
Test name
Test status
Simulation time 325253505 ps
CPU time 6.1 seconds
Started Apr 04 01:03:23 PM PDT 24
Finished Apr 04 01:03:30 PM PDT 24
Peak memory 233000 kb
Host smart-6a1e80c8-6b54-4bdb-8835-04d89640670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90582916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.90582916
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3920876896
Short name T542
Test name
Test status
Simulation time 11583828 ps
CPU time 0.72 seconds
Started Apr 04 01:03:54 PM PDT 24
Finished Apr 04 01:03:55 PM PDT 24
Peak memory 205284 kb
Host smart-23a2f05f-093c-4a69-95d3-fb7ed89ded3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920876896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3920876896
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1544679171
Short name T327
Test name
Test status
Simulation time 356271763 ps
CPU time 3.71 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:03:52 PM PDT 24
Peak memory 218720 kb
Host smart-c97f837e-e8b7-466f-ac42-defc1594c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544679171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1544679171
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1404971289
Short name T445
Test name
Test status
Simulation time 57114978 ps
CPU time 0.76 seconds
Started Apr 04 01:03:33 PM PDT 24
Finished Apr 04 01:03:34 PM PDT 24
Peak memory 206588 kb
Host smart-d1a7adab-b176-493d-afb4-e1005f90fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404971289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1404971289
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.350960255
Short name T306
Test name
Test status
Simulation time 47051244615 ps
CPU time 65.39 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:04:54 PM PDT 24
Peak memory 241020 kb
Host smart-1d6aa166-2b7d-4a4e-a05b-a8d64b354fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350960255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.350960255
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3156110661
Short name T259
Test name
Test status
Simulation time 973074830 ps
CPU time 7.04 seconds
Started Apr 04 01:03:46 PM PDT 24
Finished Apr 04 01:03:53 PM PDT 24
Peak memory 222980 kb
Host smart-a630f510-db5d-4bc7-96c5-168cc5408810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156110661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3156110661
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3843226446
Short name T639
Test name
Test status
Simulation time 6535776817 ps
CPU time 10.47 seconds
Started Apr 04 01:03:48 PM PDT 24
Finished Apr 04 01:04:00 PM PDT 24
Peak memory 218888 kb
Host smart-1dce247a-75c6-48ad-9a27-708f01475e9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3843226446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3843226446
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2333646308
Short name T671
Test name
Test status
Simulation time 1937245598 ps
CPU time 19.13 seconds
Started Apr 04 01:03:47 PM PDT 24
Finished Apr 04 01:04:07 PM PDT 24
Peak memory 216636 kb
Host smart-6c198a48-65b2-4306-8460-10eedc603b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333646308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2333646308
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2955446026
Short name T441
Test name
Test status
Simulation time 3363229163 ps
CPU time 5.96 seconds
Started Apr 04 01:03:32 PM PDT 24
Finished Apr 04 01:03:38 PM PDT 24
Peak memory 216488 kb
Host smart-7cb7d893-4981-4e75-b97c-c1bb072cba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955446026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2955446026
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.971787848
Short name T399
Test name
Test status
Simulation time 229596697 ps
CPU time 5.53 seconds
Started Apr 04 01:03:48 PM PDT 24
Finished Apr 04 01:03:54 PM PDT 24
Peak memory 216488 kb
Host smart-eae58819-1092-4661-928c-123e4d7c9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971787848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.971787848
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.829637458
Short name T715
Test name
Test status
Simulation time 87164523 ps
CPU time 1.02 seconds
Started Apr 04 01:03:46 PM PDT 24
Finished Apr 04 01:03:47 PM PDT 24
Peak memory 206868 kb
Host smart-3437962b-3eba-48a0-932a-198f9ff41537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829637458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.829637458
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2997616903
Short name T532
Test name
Test status
Simulation time 22139243 ps
CPU time 0.71 seconds
Started Apr 04 01:04:07 PM PDT 24
Finished Apr 04 01:04:08 PM PDT 24
Peak memory 204808 kb
Host smart-a7dbf28d-950b-4d7f-9c91-874868269b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997616903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2997616903
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.790941822
Short name T120
Test name
Test status
Simulation time 22216076226 ps
CPU time 25.13 seconds
Started Apr 04 01:03:54 PM PDT 24
Finished Apr 04 01:04:19 PM PDT 24
Peak memory 224684 kb
Host smart-fffeaa66-6c57-4160-9bb7-0e8d7c023089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790941822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.790941822
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1587711602
Short name T60
Test name
Test status
Simulation time 45735592 ps
CPU time 0.79 seconds
Started Apr 04 01:03:55 PM PDT 24
Finished Apr 04 01:03:56 PM PDT 24
Peak memory 206620 kb
Host smart-c8c67ff4-de89-415f-a752-ada4998c2657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587711602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1587711602
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1141346827
Short name T304
Test name
Test status
Simulation time 11479938226 ps
CPU time 11.3 seconds
Started Apr 04 01:04:01 PM PDT 24
Finished Apr 04 01:04:12 PM PDT 24
Peak memory 217088 kb
Host smart-7dcca59d-c0f4-4df3-aa36-7043ac8f65be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141346827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1141346827
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2187812925
Short name T174
Test name
Test status
Simulation time 854853234 ps
CPU time 4.7 seconds
Started Apr 04 01:03:55 PM PDT 24
Finished Apr 04 01:04:00 PM PDT 24
Peak memory 218920 kb
Host smart-23cd3590-dc8a-46f2-a04f-b52ae589dfde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2187812925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2187812925
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.67201239
Short name T385
Test name
Test status
Simulation time 11816797829 ps
CPU time 50.48 seconds
Started Apr 04 01:04:00 PM PDT 24
Finished Apr 04 01:04:50 PM PDT 24
Peak memory 216576 kb
Host smart-5044dece-405d-4ac9-b68b-f6bf49a0a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67201239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.67201239
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1414318773
Short name T566
Test name
Test status
Simulation time 11504732984 ps
CPU time 21.06 seconds
Started Apr 04 01:03:55 PM PDT 24
Finished Apr 04 01:04:16 PM PDT 24
Peak memory 216596 kb
Host smart-e8999b77-0a55-4c68-9199-97c98119bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414318773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1414318773
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1642301035
Short name T69
Test name
Test status
Simulation time 131739370 ps
CPU time 2.14 seconds
Started Apr 04 01:03:55 PM PDT 24
Finished Apr 04 01:03:58 PM PDT 24
Peak memory 216544 kb
Host smart-0c26ff97-9445-4e94-904e-7814ff2418d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642301035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1642301035
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3621509601
Short name T610
Test name
Test status
Simulation time 134980524 ps
CPU time 1.12 seconds
Started Apr 04 01:03:54 PM PDT 24
Finished Apr 04 01:03:55 PM PDT 24
Peak memory 206812 kb
Host smart-bb353e47-6394-459e-8a32-98d133ec39bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621509601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3621509601
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1446112801
Short name T16
Test name
Test status
Simulation time 24215989 ps
CPU time 0.81 seconds
Started Apr 04 12:57:17 PM PDT 24
Finished Apr 04 12:57:18 PM PDT 24
Peak memory 204772 kb
Host smart-a0359bd3-351e-49fa-bbb9-6c701abdf8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446112801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
446112801
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.838203383
Short name T697
Test name
Test status
Simulation time 260885477 ps
CPU time 0.79 seconds
Started Apr 04 12:56:58 PM PDT 24
Finished Apr 04 12:56:59 PM PDT 24
Peak memory 206616 kb
Host smart-3323e8d3-4517-4197-9115-e49f2ad605f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838203383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.838203383
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1213671216
Short name T360
Test name
Test status
Simulation time 1389261064 ps
CPU time 28.98 seconds
Started Apr 04 12:57:09 PM PDT 24
Finished Apr 04 12:57:38 PM PDT 24
Peak memory 241028 kb
Host smart-efc5fe97-491b-4f93-bbd7-a9f27f599940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213671216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1213671216
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2543583013
Short name T250
Test name
Test status
Simulation time 871089660 ps
CPU time 3.78 seconds
Started Apr 04 12:57:08 PM PDT 24
Finished Apr 04 12:57:12 PM PDT 24
Peak memory 218748 kb
Host smart-b94f6560-af40-4a02-9160-0a900119c53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543583013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2543583013
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1266574860
Short name T17
Test name
Test status
Simulation time 33737079 ps
CPU time 1.09 seconds
Started Apr 04 12:56:59 PM PDT 24
Finished Apr 04 12:57:00 PM PDT 24
Peak memory 216940 kb
Host smart-f43e3462-0b09-4cfb-9092-67997c184a10
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266574860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1266574860
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3721489737
Short name T699
Test name
Test status
Simulation time 16945184 ps
CPU time 0.73 seconds
Started Apr 04 12:56:59 PM PDT 24
Finished Apr 04 12:56:59 PM PDT 24
Peak memory 216364 kb
Host smart-1d9876d9-7d60-44e5-8263-8091f8d08942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721489737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3721489737
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.398851483
Short name T707
Test name
Test status
Simulation time 743382010 ps
CPU time 9.02 seconds
Started Apr 04 12:57:09 PM PDT 24
Finished Apr 04 12:57:18 PM PDT 24
Peak memory 219320 kb
Host smart-4323d759-3244-41b9-944c-ac9a3d075d4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398851483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.398851483
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2112500997
Short name T50
Test name
Test status
Simulation time 59284358 ps
CPU time 1.09 seconds
Started Apr 04 12:57:09 PM PDT 24
Finished Apr 04 12:57:10 PM PDT 24
Peak memory 234856 kb
Host smart-fb22fd5b-1307-42bf-bb87-5fcc5201c956
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112500997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2112500997
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.228434500
Short name T369
Test name
Test status
Simulation time 181060715 ps
CPU time 0.85 seconds
Started Apr 04 12:57:07 PM PDT 24
Finished Apr 04 12:57:08 PM PDT 24
Peak memory 205824 kb
Host smart-0088e555-bb63-4232-8895-02559320c26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228434500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.228434500
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4997712
Short name T381
Test name
Test status
Simulation time 12870940597 ps
CPU time 40.86 seconds
Started Apr 04 12:57:00 PM PDT 24
Finished Apr 04 12:57:41 PM PDT 24
Peak memory 216600 kb
Host smart-9f96f14d-0a17-4df8-91a9-3fc7d4b72119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4997712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4997712
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3264092966
Short name T63
Test name
Test status
Simulation time 20935732252 ps
CPU time 14.46 seconds
Started Apr 04 12:56:59 PM PDT 24
Finished Apr 04 12:57:14 PM PDT 24
Peak memory 216440 kb
Host smart-4083ed47-8c52-4b01-b824-1bc118efae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264092966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3264092966
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3330726222
Short name T414
Test name
Test status
Simulation time 84257470 ps
CPU time 1.59 seconds
Started Apr 04 12:56:58 PM PDT 24
Finished Apr 04 12:57:00 PM PDT 24
Peak memory 216524 kb
Host smart-8a06423d-0bf2-41c9-b445-ce14c759ab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330726222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3330726222
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2276534304
Short name T694
Test name
Test status
Simulation time 299991345 ps
CPU time 0.84 seconds
Started Apr 04 12:57:00 PM PDT 24
Finished Apr 04 12:57:00 PM PDT 24
Peak memory 206196 kb
Host smart-1b1f494a-c323-468c-8f4d-3e18213cf8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276534304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2276534304
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1073053014
Short name T241
Test name
Test status
Simulation time 3067503049 ps
CPU time 9.46 seconds
Started Apr 04 12:57:08 PM PDT 24
Finished Apr 04 12:57:17 PM PDT 24
Peak memory 220488 kb
Host smart-a5068989-433e-4278-b418-ea7e7e8f4700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073053014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1073053014
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2238156866
Short name T514
Test name
Test status
Simulation time 13048962 ps
CPU time 0.69 seconds
Started Apr 04 01:04:16 PM PDT 24
Finished Apr 04 01:04:17 PM PDT 24
Peak memory 205300 kb
Host smart-1d7348ef-39e4-40cb-9960-4aa31006ff99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238156866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2238156866
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2183478891
Short name T23
Test name
Test status
Simulation time 1728158796 ps
CPU time 7.19 seconds
Started Apr 04 01:04:02 PM PDT 24
Finished Apr 04 01:04:10 PM PDT 24
Peak memory 218740 kb
Host smart-bfa3fc01-7e54-4b4a-8ce1-f92d6efd025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183478891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2183478891
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2457738265
Short name T557
Test name
Test status
Simulation time 21688525 ps
CPU time 0.78 seconds
Started Apr 04 01:04:07 PM PDT 24
Finished Apr 04 01:04:08 PM PDT 24
Peak memory 206576 kb
Host smart-d829fa56-186b-4ee8-943e-3d23fefdde3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457738265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2457738265
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2031553265
Short name T312
Test name
Test status
Simulation time 1852705785 ps
CPU time 14.61 seconds
Started Apr 04 01:04:17 PM PDT 24
Finished Apr 04 01:04:31 PM PDT 24
Peak memory 249260 kb
Host smart-fc8bf3ab-95ef-4ede-99ea-09e9c19df9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031553265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2031553265
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2348814964
Short name T320
Test name
Test status
Simulation time 640164815 ps
CPU time 3.63 seconds
Started Apr 04 01:04:04 PM PDT 24
Finished Apr 04 01:04:08 PM PDT 24
Peak memory 221920 kb
Host smart-e0ef8e54-3ff2-4787-8f0e-5e99437fc2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348814964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2348814964
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2350859985
Short name T247
Test name
Test status
Simulation time 370468112 ps
CPU time 3.47 seconds
Started Apr 04 01:04:03 PM PDT 24
Finished Apr 04 01:04:07 PM PDT 24
Peak memory 222584 kb
Host smart-0335e8e6-ae06-4ffb-83c3-b25bd59bcdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350859985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2350859985
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3750472800
Short name T92
Test name
Test status
Simulation time 243006300 ps
CPU time 5.55 seconds
Started Apr 04 01:04:15 PM PDT 24
Finished Apr 04 01:04:21 PM PDT 24
Peak memory 220088 kb
Host smart-3a43e4ff-978b-4ef0-aa61-a9c16e46e021
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750472800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3750472800
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2919594500
Short name T589
Test name
Test status
Simulation time 11977629868 ps
CPU time 59.04 seconds
Started Apr 04 01:04:05 PM PDT 24
Finished Apr 04 01:05:05 PM PDT 24
Peak memory 216452 kb
Host smart-c093dbe4-58c2-4490-aab0-b17798b731b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919594500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2919594500
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2030147389
Short name T559
Test name
Test status
Simulation time 2456456142 ps
CPU time 6.28 seconds
Started Apr 04 01:04:04 PM PDT 24
Finished Apr 04 01:04:11 PM PDT 24
Peak memory 216636 kb
Host smart-d0ee09ac-6139-4200-b411-7729b3249902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030147389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2030147389
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2437503809
Short name T391
Test name
Test status
Simulation time 228330641 ps
CPU time 1.68 seconds
Started Apr 04 01:04:03 PM PDT 24
Finished Apr 04 01:04:05 PM PDT 24
Peak memory 216724 kb
Host smart-34ea3df1-6014-4452-b4d8-3165af203f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437503809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2437503809
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4284647685
Short name T638
Test name
Test status
Simulation time 1040612724 ps
CPU time 1.11 seconds
Started Apr 04 01:04:03 PM PDT 24
Finished Apr 04 01:04:05 PM PDT 24
Peak memory 206868 kb
Host smart-55c461bd-7c87-4d83-b4c2-b523d47a5d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284647685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4284647685
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2293275947
Short name T197
Test name
Test status
Simulation time 12682839233 ps
CPU time 11.78 seconds
Started Apr 04 01:04:05 PM PDT 24
Finished Apr 04 01:04:17 PM PDT 24
Peak memory 239844 kb
Host smart-0aff80a8-7f52-4c95-af0e-4bc6b582c8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293275947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2293275947
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4273323076
Short name T625
Test name
Test status
Simulation time 33049753 ps
CPU time 0.74 seconds
Started Apr 04 01:04:26 PM PDT 24
Finished Apr 04 01:04:27 PM PDT 24
Peak memory 205428 kb
Host smart-693aa557-a8c3-4273-a631-a419a427292a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273323076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4273323076
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2707522028
Short name T218
Test name
Test status
Simulation time 5592404953 ps
CPU time 15.26 seconds
Started Apr 04 01:04:27 PM PDT 24
Finished Apr 04 01:04:42 PM PDT 24
Peak memory 219388 kb
Host smart-80a0834b-982d-419e-a3e5-7bd91d53fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707522028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2707522028
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1803268996
Short name T425
Test name
Test status
Simulation time 58553961 ps
CPU time 0.77 seconds
Started Apr 04 01:04:15 PM PDT 24
Finished Apr 04 01:04:16 PM PDT 24
Peak memory 205584 kb
Host smart-d531f61b-1530-45a8-8045-d8b9d0b25b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803268996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1803268996
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2231593274
Short name T319
Test name
Test status
Simulation time 4641425814 ps
CPU time 28.62 seconds
Started Apr 04 01:04:27 PM PDT 24
Finished Apr 04 01:04:55 PM PDT 24
Peak memory 253140 kb
Host smart-b2382678-fc71-4b55-a30f-bf84cdeb424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231593274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2231593274
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.37191172
Short name T7
Test name
Test status
Simulation time 119241203 ps
CPU time 2.47 seconds
Started Apr 04 01:04:15 PM PDT 24
Finished Apr 04 01:04:18 PM PDT 24
Peak memory 222940 kb
Host smart-43014f5c-9033-4091-b8ce-c93af3be76a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37191172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.37191172
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3402479430
Short name T331
Test name
Test status
Simulation time 9165277456 ps
CPU time 13.83 seconds
Started Apr 04 01:04:16 PM PDT 24
Finished Apr 04 01:04:30 PM PDT 24
Peak memory 227204 kb
Host smart-fc9a9c1e-ef31-459d-8285-db184c5be3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402479430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3402479430
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.454276026
Short name T737
Test name
Test status
Simulation time 688510338 ps
CPU time 5.27 seconds
Started Apr 04 01:04:28 PM PDT 24
Finished Apr 04 01:04:33 PM PDT 24
Peak memory 223000 kb
Host smart-174251d7-9025-4626-804c-ae2ad1b7d7e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454276026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.454276026
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1105740632
Short name T624
Test name
Test status
Simulation time 38190530123 ps
CPU time 37.74 seconds
Started Apr 04 01:04:16 PM PDT 24
Finished Apr 04 01:04:54 PM PDT 24
Peak memory 216544 kb
Host smart-9c9847ae-ace3-4e5c-8648-65bb1d28a37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105740632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1105740632
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1406881258
Short name T756
Test name
Test status
Simulation time 8291311330 ps
CPU time 23.5 seconds
Started Apr 04 01:04:14 PM PDT 24
Finished Apr 04 01:04:38 PM PDT 24
Peak memory 216476 kb
Host smart-5d8ef965-c5d7-4ef7-a5a5-fa50cf1753ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406881258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1406881258
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3397434837
Short name T403
Test name
Test status
Simulation time 819226656 ps
CPU time 2.43 seconds
Started Apr 04 01:04:19 PM PDT 24
Finished Apr 04 01:04:21 PM PDT 24
Peak memory 216476 kb
Host smart-6f5edd64-6de9-454d-a02c-3d89d2f13084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397434837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3397434837
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.611994888
Short name T640
Test name
Test status
Simulation time 145886274 ps
CPU time 1.19 seconds
Started Apr 04 01:04:19 PM PDT 24
Finished Apr 04 01:04:20 PM PDT 24
Peak memory 206800 kb
Host smart-bb012c3e-7943-42fc-89da-c7a28c18d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611994888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.611994888
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1619206722
Short name T330
Test name
Test status
Simulation time 324055034 ps
CPU time 4.19 seconds
Started Apr 04 01:04:26 PM PDT 24
Finished Apr 04 01:04:30 PM PDT 24
Peak memory 224496 kb
Host smart-6d55d331-c243-4715-b844-66ae4b3c4732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619206722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1619206722
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4231542151
Short name T583
Test name
Test status
Simulation time 10876221 ps
CPU time 0.68 seconds
Started Apr 04 01:04:56 PM PDT 24
Finished Apr 04 01:04:58 PM PDT 24
Peak memory 205284 kb
Host smart-7e46cc54-a043-4b9a-bf80-20675d402091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231542151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4231542151
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1188372572
Short name T506
Test name
Test status
Simulation time 941725056 ps
CPU time 9.8 seconds
Started Apr 04 01:04:42 PM PDT 24
Finished Apr 04 01:04:53 PM PDT 24
Peak memory 218984 kb
Host smart-4e1f3d8b-8c48-4d4c-bb73-7a9bb3e077e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188372572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1188372572
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3258530054
Short name T424
Test name
Test status
Simulation time 53750000 ps
CPU time 0.76 seconds
Started Apr 04 01:04:25 PM PDT 24
Finished Apr 04 01:04:26 PM PDT 24
Peak memory 206972 kb
Host smart-764914df-3dd1-4f3a-b946-9f6e250ef82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258530054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3258530054
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3462140541
Short name T308
Test name
Test status
Simulation time 48748371777 ps
CPU time 160.4 seconds
Started Apr 04 01:04:43 PM PDT 24
Finished Apr 04 01:07:24 PM PDT 24
Peak memory 262216 kb
Host smart-ca59eb38-53f1-4919-8698-8ee9f80e9252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462140541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3462140541
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.8601337
Short name T691
Test name
Test status
Simulation time 413595779 ps
CPU time 2.48 seconds
Started Apr 04 01:04:42 PM PDT 24
Finished Apr 04 01:04:46 PM PDT 24
Peak memory 218604 kb
Host smart-733469c5-8887-45f9-a163-6b0e9b68f799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8601337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.8601337
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2174588724
Short name T215
Test name
Test status
Simulation time 1275398918 ps
CPU time 8.36 seconds
Started Apr 04 01:04:28 PM PDT 24
Finished Apr 04 01:04:36 PM PDT 24
Peak memory 216984 kb
Host smart-a2c6d226-a5a6-4624-b887-a038fe65e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174588724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2174588724
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2203155806
Short name T585
Test name
Test status
Simulation time 3740564096 ps
CPU time 10.33 seconds
Started Apr 04 01:04:43 PM PDT 24
Finished Apr 04 01:04:54 PM PDT 24
Peak memory 222944 kb
Host smart-10b1119a-b04b-4044-9075-b53a9302fd9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2203155806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2203155806
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.826390559
Short name T111
Test name
Test status
Simulation time 7555641404 ps
CPU time 48.15 seconds
Started Apr 04 01:04:31 PM PDT 24
Finished Apr 04 01:05:19 PM PDT 24
Peak memory 216404 kb
Host smart-16805aa8-c396-4b7e-8128-990b807e5b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826390559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.826390559
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1979993568
Short name T402
Test name
Test status
Simulation time 150039533 ps
CPU time 3.15 seconds
Started Apr 04 01:04:26 PM PDT 24
Finished Apr 04 01:04:29 PM PDT 24
Peak memory 216576 kb
Host smart-f7fa63dd-0305-4949-878e-3cafc523891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979993568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1979993568
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.732513088
Short name T567
Test name
Test status
Simulation time 26454900 ps
CPU time 0.75 seconds
Started Apr 04 01:04:27 PM PDT 24
Finished Apr 04 01:04:28 PM PDT 24
Peak memory 205876 kb
Host smart-98ba86d0-6e3e-4f9c-bcb1-13e9fcc33851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732513088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.732513088
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.600776926
Short name T31
Test name
Test status
Simulation time 21362537 ps
CPU time 0.73 seconds
Started Apr 04 01:04:57 PM PDT 24
Finished Apr 04 01:04:58 PM PDT 24
Peak memory 205412 kb
Host smart-9e11d546-c9a6-473e-94cb-2e658a93025e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600776926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.600776926
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2793937814
Short name T482
Test name
Test status
Simulation time 13985553 ps
CPU time 0.8 seconds
Started Apr 04 01:04:56 PM PDT 24
Finished Apr 04 01:04:58 PM PDT 24
Peak memory 206576 kb
Host smart-4fe4c327-6595-44c2-81ca-3427f4cebf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793937814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2793937814
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3872149848
Short name T11
Test name
Test status
Simulation time 4253456238 ps
CPU time 48.51 seconds
Started Apr 04 01:04:56 PM PDT 24
Finished Apr 04 01:05:45 PM PDT 24
Peak memory 250536 kb
Host smart-bdc9b1da-f8ba-45a0-9fa8-16ff464c9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872149848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3872149848
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3699691189
Short name T322
Test name
Test status
Simulation time 162116915 ps
CPU time 4.05 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:00 PM PDT 24
Peak memory 219032 kb
Host smart-d7f6afc4-999b-4b2f-880d-a925667db2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699691189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3699691189
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3617023159
Short name T282
Test name
Test status
Simulation time 7144282002 ps
CPU time 18.02 seconds
Started Apr 04 01:04:54 PM PDT 24
Finished Apr 04 01:05:13 PM PDT 24
Peak memory 222616 kb
Host smart-19487cd6-a0cf-48c4-b2e2-5f1cbc97233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617023159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3617023159
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.236516808
Short name T79
Test name
Test status
Simulation time 1690479295 ps
CPU time 3.24 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:59 PM PDT 24
Peak memory 216808 kb
Host smart-ceef018a-55eb-4391-abb6-d4db5e72a7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236516808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.236516808
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3493717855
Short name T718
Test name
Test status
Simulation time 896114113 ps
CPU time 6.82 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:03 PM PDT 24
Peak memory 219320 kb
Host smart-150fcdc2-1694-43b8-9540-b368d922fef7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493717855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3493717855
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1403196262
Short name T613
Test name
Test status
Simulation time 3067381508 ps
CPU time 28.25 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:25 PM PDT 24
Peak memory 216524 kb
Host smart-29a0fde1-ef93-4012-9ac8-dd08197725a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403196262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1403196262
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4241111330
Short name T134
Test name
Test status
Simulation time 1535939901 ps
CPU time 8.21 seconds
Started Apr 04 01:04:56 PM PDT 24
Finished Apr 04 01:05:05 PM PDT 24
Peak memory 216464 kb
Host smart-645d317a-fbda-439c-bc43-361ed39a3ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241111330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4241111330
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.347758630
Short name T711
Test name
Test status
Simulation time 475395426 ps
CPU time 2.11 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:59 PM PDT 24
Peak memory 208652 kb
Host smart-729d6dc9-8d8d-41f6-bda9-e60eaa05ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347758630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.347758630
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2718549645
Short name T584
Test name
Test status
Simulation time 431657090 ps
CPU time 1.04 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:57 PM PDT 24
Peak memory 206764 kb
Host smart-5f347cca-9221-46bb-8480-dbe9c2b3c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718549645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2718549645
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3007952974
Short name T32
Test name
Test status
Simulation time 14562450 ps
CPU time 0.72 seconds
Started Apr 04 01:05:08 PM PDT 24
Finished Apr 04 01:05:09 PM PDT 24
Peak memory 205428 kb
Host smart-e465df2b-dc6b-49cd-8c36-2a9f2f8472c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007952974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3007952974
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.472395652
Short name T500
Test name
Test status
Simulation time 376293652 ps
CPU time 6.43 seconds
Started Apr 04 01:05:08 PM PDT 24
Finished Apr 04 01:05:14 PM PDT 24
Peak memory 223588 kb
Host smart-14919929-d692-4968-8e30-a1822fccfaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472395652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.472395652
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.15600693
Short name T423
Test name
Test status
Simulation time 77978103 ps
CPU time 0.79 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:57 PM PDT 24
Peak memory 206552 kb
Host smart-d2a5f739-5f03-40a3-8a41-6789ea93eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15600693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.15600693
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1988832649
Short name T578
Test name
Test status
Simulation time 6395680071 ps
CPU time 52.28 seconds
Started Apr 04 01:05:08 PM PDT 24
Finished Apr 04 01:06:01 PM PDT 24
Peak memory 224704 kb
Host smart-70f3cd4f-4a02-4c41-be53-b1fb9ec6fea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988832649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1988832649
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3213753646
Short name T266
Test name
Test status
Simulation time 2433832970 ps
CPU time 12.8 seconds
Started Apr 04 01:05:09 PM PDT 24
Finished Apr 04 01:05:22 PM PDT 24
Peak memory 224680 kb
Host smart-87b36479-03d7-458c-a653-127c51eb33a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213753646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3213753646
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1713085233
Short name T202
Test name
Test status
Simulation time 6418321099 ps
CPU time 20 seconds
Started Apr 04 01:05:08 PM PDT 24
Finished Apr 04 01:05:29 PM PDT 24
Peak memory 224880 kb
Host smart-379b4079-febb-45f3-ac00-834647357f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713085233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1713085233
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.674907148
Short name T597
Test name
Test status
Simulation time 6617508740 ps
CPU time 10.35 seconds
Started Apr 04 01:05:07 PM PDT 24
Finished Apr 04 01:05:17 PM PDT 24
Peak memory 222012 kb
Host smart-dafeea21-60b1-4a74-8961-7ffbe8980205
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=674907148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.674907148
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1935439011
Short name T397
Test name
Test status
Simulation time 2104138353 ps
CPU time 25.99 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:22 PM PDT 24
Peak memory 216504 kb
Host smart-562bc707-5438-4925-b5b7-f1f6f11dd687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935439011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1935439011
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.36530022
Short name T447
Test name
Test status
Simulation time 3029424436 ps
CPU time 3.21 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:05:00 PM PDT 24
Peak memory 216404 kb
Host smart-5dd9310e-fd16-4d5f-b2cb-92fcda4e7d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36530022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.36530022
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3837122287
Short name T401
Test name
Test status
Simulation time 65922590 ps
CPU time 1.69 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:58 PM PDT 24
Peak memory 216460 kb
Host smart-b9cb44e6-f405-4c05-ac40-e48bd15f411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837122287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3837122287
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2288592609
Short name T620
Test name
Test status
Simulation time 152645930 ps
CPU time 1.02 seconds
Started Apr 04 01:04:55 PM PDT 24
Finished Apr 04 01:04:57 PM PDT 24
Peak memory 206812 kb
Host smart-44e9d522-f6b6-4659-8b01-d87973afe607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288592609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2288592609
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.300218688
Short name T668
Test name
Test status
Simulation time 45318583 ps
CPU time 0.73 seconds
Started Apr 04 01:05:29 PM PDT 24
Finished Apr 04 01:05:31 PM PDT 24
Peak memory 205376 kb
Host smart-8c6b2d73-c58f-41ae-acbf-0eb2fe1e8b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300218688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.300218688
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3787013167
Short name T2
Test name
Test status
Simulation time 51782472 ps
CPU time 0.78 seconds
Started Apr 04 01:05:10 PM PDT 24
Finished Apr 04 01:05:10 PM PDT 24
Peak memory 206992 kb
Host smart-7b6922d8-dea1-4dbe-a82b-6b613b877bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787013167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3787013167
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.555780172
Short name T58
Test name
Test status
Simulation time 355392162 ps
CPU time 14 seconds
Started Apr 04 01:05:19 PM PDT 24
Finished Apr 04 01:05:33 PM PDT 24
Peak memory 249224 kb
Host smart-7b7bc452-91b5-44fa-aae3-b634f8cbebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555780172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.555780172
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3977211564
Short name T89
Test name
Test status
Simulation time 2684929391 ps
CPU time 33.21 seconds
Started Apr 04 01:05:17 PM PDT 24
Finished Apr 04 01:05:50 PM PDT 24
Peak memory 223288 kb
Host smart-82f3898b-970e-42a8-82e1-787eeb2911f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977211564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3977211564
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4254897404
Short name T56
Test name
Test status
Simulation time 1129338508 ps
CPU time 11.78 seconds
Started Apr 04 01:05:18 PM PDT 24
Finished Apr 04 01:05:30 PM PDT 24
Peak memory 222620 kb
Host smart-a1c178eb-d9e8-4b44-90db-03f9f6bb7a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254897404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4254897404
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4069817784
Short name T280
Test name
Test status
Simulation time 2829207273 ps
CPU time 4.19 seconds
Started Apr 04 01:05:22 PM PDT 24
Finished Apr 04 01:05:28 PM PDT 24
Peak memory 217276 kb
Host smart-7d187515-14fb-4e30-b103-bce40c449f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069817784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4069817784
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2484424983
Short name T357
Test name
Test status
Simulation time 3622593629 ps
CPU time 8.3 seconds
Started Apr 04 01:05:18 PM PDT 24
Finished Apr 04 01:05:26 PM PDT 24
Peak memory 237680 kb
Host smart-ebf604d8-c293-4ca1-bf6d-e5e7407acc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484424983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2484424983
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.332624169
Short name T740
Test name
Test status
Simulation time 4010056084 ps
CPU time 6.98 seconds
Started Apr 04 01:05:22 PM PDT 24
Finished Apr 04 01:05:31 PM PDT 24
Peak memory 220788 kb
Host smart-422418dd-f5cc-4a54-8680-ad7aa0800da0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332624169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.332624169
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.192326510
Short name T371
Test name
Test status
Simulation time 55797397 ps
CPU time 1.01 seconds
Started Apr 04 01:05:28 PM PDT 24
Finished Apr 04 01:05:30 PM PDT 24
Peak memory 207008 kb
Host smart-b8ed793f-c4ce-427c-910d-d05ce9086eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192326510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.192326510
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3189740633
Short name T664
Test name
Test status
Simulation time 8234073539 ps
CPU time 6.18 seconds
Started Apr 04 01:05:08 PM PDT 24
Finished Apr 04 01:05:15 PM PDT 24
Peak memory 216544 kb
Host smart-b6e1fbf1-4af4-4021-b4fb-db86b92925a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189740633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3189740633
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4132659526
Short name T564
Test name
Test status
Simulation time 811145999 ps
CPU time 2.18 seconds
Started Apr 04 01:05:17 PM PDT 24
Finished Apr 04 01:05:19 PM PDT 24
Peak memory 216480 kb
Host smart-2d0986ac-7fde-4f99-a44f-969d620756b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132659526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4132659526
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3594864751
Short name T574
Test name
Test status
Simulation time 35358967 ps
CPU time 0.81 seconds
Started Apr 04 01:05:19 PM PDT 24
Finished Apr 04 01:05:20 PM PDT 24
Peak memory 205688 kb
Host smart-0e893d52-9dd4-40da-95f9-0c92f4cdcf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594864751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3594864751
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.828257953
Short name T275
Test name
Test status
Simulation time 817436897 ps
CPU time 5.85 seconds
Started Apr 04 01:05:19 PM PDT 24
Finished Apr 04 01:05:27 PM PDT 24
Peak memory 232964 kb
Host smart-87ac12ca-f924-4737-aa74-add45e3bb142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828257953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.828257953
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.790676382
Short name T437
Test name
Test status
Simulation time 14405609 ps
CPU time 0.68 seconds
Started Apr 04 01:05:39 PM PDT 24
Finished Apr 04 01:05:40 PM PDT 24
Peak memory 204884 kb
Host smart-d9df55e7-29fb-4ed9-8c00-9c3abd4b2c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790676382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.790676382
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3155935975
Short name T540
Test name
Test status
Simulation time 262028485 ps
CPU time 3.83 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:44 PM PDT 24
Peak memory 223040 kb
Host smart-a5c0dcc8-ae4d-4d34-9254-00c5012b65a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155935975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3155935975
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3785597218
Short name T464
Test name
Test status
Simulation time 69512190 ps
CPU time 0.8 seconds
Started Apr 04 01:05:29 PM PDT 24
Finished Apr 04 01:05:31 PM PDT 24
Peak memory 206664 kb
Host smart-f1493d8c-bdeb-4b34-adda-cad42ede27ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785597218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3785597218
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2704016030
Short name T726
Test name
Test status
Simulation time 3611909785 ps
CPU time 16.37 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:05:57 PM PDT 24
Peak memory 256516 kb
Host smart-1c5a2861-e35f-4204-b47b-74e42aa33ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704016030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2704016030
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.970024819
Short name T244
Test name
Test status
Simulation time 4604701913 ps
CPU time 39.2 seconds
Started Apr 04 01:05:39 PM PDT 24
Finished Apr 04 01:06:18 PM PDT 24
Peak memory 238652 kb
Host smart-418e6550-2db6-4044-b5b4-08f78aacc729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970024819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.970024819
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1453506513
Short name T199
Test name
Test status
Simulation time 3359856779 ps
CPU time 14.75 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:05:56 PM PDT 24
Peak memory 235312 kb
Host smart-e43773fc-02e1-4ea8-b8c6-875ba112f679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453506513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1453506513
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1645488595
Short name T615
Test name
Test status
Simulation time 5294145407 ps
CPU time 11.53 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:51 PM PDT 24
Peak memory 220372 kb
Host smart-42d4cc34-ad5e-4a94-a210-74ad5efe358e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1645488595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1645488595
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.996509927
Short name T384
Test name
Test status
Simulation time 179501620458 ps
CPU time 53.82 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:06:34 PM PDT 24
Peak memory 216436 kb
Host smart-71a2a48d-ec75-47bb-9f5d-afafb3a0bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996509927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.996509927
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2226619068
Short name T634
Test name
Test status
Simulation time 2037129209 ps
CPU time 4.55 seconds
Started Apr 04 01:05:29 PM PDT 24
Finished Apr 04 01:05:34 PM PDT 24
Peak memory 216396 kb
Host smart-2c3ea48f-c4ff-4dfe-9bab-e34190c1804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226619068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2226619068
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3807972688
Short name T685
Test name
Test status
Simulation time 131823016 ps
CPU time 4.28 seconds
Started Apr 04 01:05:39 PM PDT 24
Finished Apr 04 01:05:44 PM PDT 24
Peak memory 216584 kb
Host smart-8bb4ea96-7f59-4ed2-bed8-1266cebec77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807972688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3807972688
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.807174318
Short name T488
Test name
Test status
Simulation time 412021785 ps
CPU time 0.97 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:05:42 PM PDT 24
Peak memory 205872 kb
Host smart-4a0270bd-ab9f-4bc5-a6e0-d1dbc01346dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807174318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.807174318
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3528635337
Short name T245
Test name
Test status
Simulation time 2144098708 ps
CPU time 4.62 seconds
Started Apr 04 01:05:38 PM PDT 24
Finished Apr 04 01:05:43 PM PDT 24
Peak memory 220288 kb
Host smart-258c4bd8-904e-468d-9fe7-9bce1980f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528635337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3528635337
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3891592601
Short name T493
Test name
Test status
Simulation time 138545144 ps
CPU time 0.69 seconds
Started Apr 04 01:05:50 PM PDT 24
Finished Apr 04 01:05:51 PM PDT 24
Peak memory 205320 kb
Host smart-1b625e5f-1199-4ae8-b029-30d4cc3d1ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891592601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3891592601
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1082135574
Short name T641
Test name
Test status
Simulation time 229012449 ps
CPU time 0.76 seconds
Started Apr 04 01:05:43 PM PDT 24
Finished Apr 04 01:05:43 PM PDT 24
Peak memory 206544 kb
Host smart-f34ae196-1e1f-4931-8d5a-9fa2f77a1aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082135574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1082135574
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4170582258
Short name T366
Test name
Test status
Simulation time 2411675190 ps
CPU time 30.2 seconds
Started Apr 04 01:05:49 PM PDT 24
Finished Apr 04 01:06:20 PM PDT 24
Peak memory 239068 kb
Host smart-8fc1f77a-6271-4df8-9032-04e1b9650f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170582258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4170582258
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4039338337
Short name T240
Test name
Test status
Simulation time 49132278484 ps
CPU time 37.42 seconds
Started Apr 04 01:05:42 PM PDT 24
Finished Apr 04 01:06:19 PM PDT 24
Peak memory 237780 kb
Host smart-24f61152-58c0-46ea-acde-e1514ad3799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039338337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4039338337
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3132697974
Short name T748
Test name
Test status
Simulation time 171924057 ps
CPU time 4.32 seconds
Started Apr 04 01:05:50 PM PDT 24
Finished Apr 04 01:05:55 PM PDT 24
Peak memory 222828 kb
Host smart-f4ece4c0-2bd7-4695-a263-111ce353ee49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132697974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3132697974
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.40111200
Short name T687
Test name
Test status
Simulation time 6407956802 ps
CPU time 12.25 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:52 PM PDT 24
Peak memory 216564 kb
Host smart-959af9ba-f99b-4ce1-ab65-32f1cd5bfae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40111200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.40111200
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2025622323
Short name T755
Test name
Test status
Simulation time 1017351039 ps
CPU time 6.72 seconds
Started Apr 04 01:05:41 PM PDT 24
Finished Apr 04 01:05:48 PM PDT 24
Peak memory 216404 kb
Host smart-e9cb0756-414e-4e8c-8bc9-f5b6c427accd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025622323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2025622323
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3377677543
Short name T751
Test name
Test status
Simulation time 291752253 ps
CPU time 2.83 seconds
Started Apr 04 01:05:38 PM PDT 24
Finished Apr 04 01:05:41 PM PDT 24
Peak memory 216536 kb
Host smart-ef71f9fe-2b83-46c6-ab61-8d92efdae977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377677543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3377677543
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3262480606
Short name T477
Test name
Test status
Simulation time 647466655 ps
CPU time 1.18 seconds
Started Apr 04 01:05:40 PM PDT 24
Finished Apr 04 01:05:41 PM PDT 24
Peak memory 206832 kb
Host smart-13d925ad-7d68-45f6-b36f-03e1701046ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262480606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3262480606
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4128970055
Short name T26
Test name
Test status
Simulation time 2661918104 ps
CPU time 6.93 seconds
Started Apr 04 01:05:39 PM PDT 24
Finished Apr 04 01:05:47 PM PDT 24
Peak memory 223436 kb
Host smart-f01c4e71-e30a-4cce-8e82-6d0760921a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128970055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4128970055
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3475315430
Short name T430
Test name
Test status
Simulation time 13588481 ps
CPU time 0.67 seconds
Started Apr 04 01:05:59 PM PDT 24
Finished Apr 04 01:06:00 PM PDT 24
Peak memory 205288 kb
Host smart-a1572f5e-8941-4658-9258-a8163d7271f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475315430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3475315430
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1851677750
Short name T623
Test name
Test status
Simulation time 836923452 ps
CPU time 13.14 seconds
Started Apr 04 01:05:58 PM PDT 24
Finished Apr 04 01:06:11 PM PDT 24
Peak memory 218980 kb
Host smart-a0ee5fd5-9e74-4059-9460-43a38a6ddaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851677750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1851677750
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3613880696
Short name T443
Test name
Test status
Simulation time 43802258 ps
CPU time 0.78 seconds
Started Apr 04 01:05:51 PM PDT 24
Finished Apr 04 01:05:52 PM PDT 24
Peak memory 206500 kb
Host smart-2a01ae17-ec02-4c4f-a766-787adb11873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613880696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3613880696
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1974872510
Short name T315
Test name
Test status
Simulation time 21211005785 ps
CPU time 82.96 seconds
Started Apr 04 01:05:58 PM PDT 24
Finished Apr 04 01:07:21 PM PDT 24
Peak memory 241152 kb
Host smart-a75a837f-2503-432f-8dc3-e5e62de4a355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974872510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1974872510
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3388997827
Short name T126
Test name
Test status
Simulation time 372528624 ps
CPU time 7.24 seconds
Started Apr 04 01:06:02 PM PDT 24
Finished Apr 04 01:06:09 PM PDT 24
Peak memory 223064 kb
Host smart-0c02f238-9c1f-4fe8-a7a6-51f4ab8d0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388997827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3388997827
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3320745993
Short name T74
Test name
Test status
Simulation time 349282381 ps
CPU time 3.12 seconds
Started Apr 04 01:05:50 PM PDT 24
Finished Apr 04 01:05:54 PM PDT 24
Peak memory 223548 kb
Host smart-0370669b-13ea-4c3c-9c44-980e9a053753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320745993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3320745993
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.210226696
Short name T173
Test name
Test status
Simulation time 1269757860 ps
CPU time 3.46 seconds
Started Apr 04 01:05:59 PM PDT 24
Finished Apr 04 01:06:02 PM PDT 24
Peak memory 219836 kb
Host smart-ae64e7b4-7f1f-4900-8104-fd439185560c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210226696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.210226696
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1078598449
Short name T398
Test name
Test status
Simulation time 4499715243 ps
CPU time 23.8 seconds
Started Apr 04 01:05:49 PM PDT 24
Finished Apr 04 01:06:13 PM PDT 24
Peak memory 216532 kb
Host smart-1efb0868-4bb4-41a1-a099-33556285aa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078598449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1078598449
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2975672733
Short name T539
Test name
Test status
Simulation time 15225795094 ps
CPU time 21.14 seconds
Started Apr 04 01:05:52 PM PDT 24
Finished Apr 04 01:06:13 PM PDT 24
Peak memory 216572 kb
Host smart-bd0e83e2-d6e7-47c8-85b4-b333db4e2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975672733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2975672733
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.627357627
Short name T503
Test name
Test status
Simulation time 197421340 ps
CPU time 1.51 seconds
Started Apr 04 01:05:49 PM PDT 24
Finished Apr 04 01:05:50 PM PDT 24
Peak memory 217756 kb
Host smart-b07599e7-069f-4409-98e8-3429fa31ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627357627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.627357627
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2171802543
Short name T525
Test name
Test status
Simulation time 65718522 ps
CPU time 0.75 seconds
Started Apr 04 01:05:51 PM PDT 24
Finished Apr 04 01:05:52 PM PDT 24
Peak memory 205848 kb
Host smart-ea95b439-b2bb-4fbc-a5b0-4b72e5b36af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171802543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2171802543
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2608613509
Short name T727
Test name
Test status
Simulation time 38332145 ps
CPU time 0.69 seconds
Started Apr 04 01:06:20 PM PDT 24
Finished Apr 04 01:06:21 PM PDT 24
Peak memory 205748 kb
Host smart-410cbb19-bb8b-4c85-9ac7-d5318b3c39db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608613509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2608613509
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.726775154
Short name T565
Test name
Test status
Simulation time 33167159 ps
CPU time 0.73 seconds
Started Apr 04 01:06:00 PM PDT 24
Finished Apr 04 01:06:01 PM PDT 24
Peak memory 206908 kb
Host smart-36af95f2-24c9-4a59-9fda-37182c81253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726775154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.726775154
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1001583265
Short name T516
Test name
Test status
Simulation time 7608826820 ps
CPU time 41.9 seconds
Started Apr 04 01:06:10 PM PDT 24
Finished Apr 04 01:06:52 PM PDT 24
Peak memory 241192 kb
Host smart-c699d7e3-7ea0-4c6e-880c-c58b98413b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001583265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1001583265
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2527598850
Short name T263
Test name
Test status
Simulation time 461467765 ps
CPU time 2.67 seconds
Started Apr 04 01:06:09 PM PDT 24
Finished Apr 04 01:06:11 PM PDT 24
Peak memory 220152 kb
Host smart-1ba90d90-bdbb-44e5-8632-19f912f37110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527598850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2527598850
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1596248084
Short name T153
Test name
Test status
Simulation time 34402788344 ps
CPU time 70.2 seconds
Started Apr 04 01:06:11 PM PDT 24
Finished Apr 04 01:07:21 PM PDT 24
Peak memory 229532 kb
Host smart-1d7ba64d-b2b8-45be-a504-b1899acb7af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596248084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1596248084
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1446347998
Short name T293
Test name
Test status
Simulation time 6341643447 ps
CPU time 7.23 seconds
Started Apr 04 01:06:10 PM PDT 24
Finished Apr 04 01:06:17 PM PDT 24
Peak memory 219048 kb
Host smart-64820c82-22b4-4473-801e-c2e29660fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446347998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1446347998
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4118011254
Short name T203
Test name
Test status
Simulation time 2699872518 ps
CPU time 8.79 seconds
Started Apr 04 01:06:08 PM PDT 24
Finished Apr 04 01:06:17 PM PDT 24
Peak memory 216896 kb
Host smart-cca1bca0-d0f4-44c6-a522-18dd4c4cfef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118011254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4118011254
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4108190194
Short name T596
Test name
Test status
Simulation time 201276001 ps
CPU time 3.77 seconds
Started Apr 04 01:06:11 PM PDT 24
Finished Apr 04 01:06:15 PM PDT 24
Peak memory 220784 kb
Host smart-92873f53-70fd-4aac-b584-b7e874fdf36c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108190194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4108190194
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.390988276
Short name T368
Test name
Test status
Simulation time 152647219 ps
CPU time 0.94 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:06:23 PM PDT 24
Peak memory 206692 kb
Host smart-14830637-d2a3-451f-a19e-b23777da2582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390988276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.390988276
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3414800202
Short name T382
Test name
Test status
Simulation time 4564954204 ps
CPU time 35.33 seconds
Started Apr 04 01:06:09 PM PDT 24
Finished Apr 04 01:06:45 PM PDT 24
Peak memory 216616 kb
Host smart-c272a682-da64-42e7-856a-1f11c1c3097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414800202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3414800202
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2483845082
Short name T114
Test name
Test status
Simulation time 9172511479 ps
CPU time 6.58 seconds
Started Apr 04 01:06:00 PM PDT 24
Finished Apr 04 01:06:06 PM PDT 24
Peak memory 216472 kb
Host smart-bc1832ec-9fbc-4665-be9a-8abfaa3177f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483845082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2483845082
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2545366870
Short name T412
Test name
Test status
Simulation time 139060601 ps
CPU time 1.32 seconds
Started Apr 04 01:06:09 PM PDT 24
Finished Apr 04 01:06:10 PM PDT 24
Peak memory 208416 kb
Host smart-46aa108b-20e5-4fa7-b370-0b22f2ff0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545366870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2545366870
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.962938654
Short name T534
Test name
Test status
Simulation time 337785073 ps
CPU time 1.1 seconds
Started Apr 04 01:06:09 PM PDT 24
Finished Apr 04 01:06:10 PM PDT 24
Peak memory 206856 kb
Host smart-9c0d3377-2fd1-47d5-a0ff-d69f70788e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962938654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.962938654
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.950215051
Short name T205
Test name
Test status
Simulation time 124468694332 ps
CPU time 32.45 seconds
Started Apr 04 01:06:11 PM PDT 24
Finished Apr 04 01:06:43 PM PDT 24
Peak memory 223276 kb
Host smart-3aabfaee-ac69-4f4b-9cd2-19657ebf1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950215051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.950215051
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1202596145
Short name T632
Test name
Test status
Simulation time 22784627 ps
CPU time 0.71 seconds
Started Apr 04 12:57:24 PM PDT 24
Finished Apr 04 12:57:25 PM PDT 24
Peak memory 205728 kb
Host smart-99ab2be2-cd25-40e9-9087-c78e5d18c047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202596145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
202596145
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2769344043
Short name T752
Test name
Test status
Simulation time 173180551 ps
CPU time 0.82 seconds
Started Apr 04 12:57:15 PM PDT 24
Finished Apr 04 12:57:16 PM PDT 24
Peak memory 206628 kb
Host smart-dc393a81-3c08-4970-8aa6-ee4ab43fca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769344043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2769344043
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2998944591
Short name T117
Test name
Test status
Simulation time 1808005245 ps
CPU time 20.07 seconds
Started Apr 04 12:57:15 PM PDT 24
Finished Apr 04 12:57:35 PM PDT 24
Peak memory 218816 kb
Host smart-0f97d721-9a23-42c3-b0b6-22586fee4b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998944591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2998944591
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2530369253
Short name T474
Test name
Test status
Simulation time 154665460 ps
CPU time 1.04 seconds
Started Apr 04 12:57:17 PM PDT 24
Finished Apr 04 12:57:18 PM PDT 24
Peak memory 218208 kb
Host smart-18d4329a-29b2-427e-a766-4f50b89c280d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530369253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2530369253
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1485900305
Short name T335
Test name
Test status
Simulation time 938384831 ps
CPU time 6.12 seconds
Started Apr 04 12:57:17 PM PDT 24
Finished Apr 04 12:57:24 PM PDT 24
Peak memory 232952 kb
Host smart-2c0dfdf3-74c4-4ec8-81fb-feb8d4c051bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485900305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1485900305
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3277661270
Short name T693
Test name
Test status
Simulation time 42289663 ps
CPU time 0.77 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:17 PM PDT 24
Peak memory 216372 kb
Host smart-431c9259-91fd-48b9-adf8-1695b070bd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277661270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3277661270
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3737919822
Short name T619
Test name
Test status
Simulation time 7015106998 ps
CPU time 7.98 seconds
Started Apr 04 12:57:17 PM PDT 24
Finished Apr 04 12:57:25 PM PDT 24
Peak memory 221996 kb
Host smart-158a8107-3184-4b23-b588-d7401517093f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3737919822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3737919822
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.214396478
Short name T14
Test name
Test status
Simulation time 42016620423 ps
CPU time 31.67 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:48 PM PDT 24
Peak memory 216476 kb
Host smart-e573957b-f993-436a-849d-50910d4ab4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214396478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.214396478
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1128000294
Short name T405
Test name
Test status
Simulation time 200126616 ps
CPU time 0.99 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:18 PM PDT 24
Peak memory 207100 kb
Host smart-584cc21c-62d7-4f7d-b09b-7e42f9876673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128000294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1128000294
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3810154128
Short name T453
Test name
Test status
Simulation time 50437406 ps
CPU time 0.9 seconds
Started Apr 04 12:57:16 PM PDT 24
Finished Apr 04 12:57:18 PM PDT 24
Peak memory 205832 kb
Host smart-9d5a9e56-06c1-4e3d-aee0-cc886ed2c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810154128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3810154128
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.68988613
Short name T617
Test name
Test status
Simulation time 36936219 ps
CPU time 0.68 seconds
Started Apr 04 12:57:31 PM PDT 24
Finished Apr 04 12:57:32 PM PDT 24
Peak memory 204840 kb
Host smart-8fa37440-24b4-4b8a-9f1c-fff95ef2f97f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68988613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.68988613
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2519134638
Short name T332
Test name
Test status
Simulation time 341235011 ps
CPU time 5.55 seconds
Started Apr 04 12:57:34 PM PDT 24
Finished Apr 04 12:57:39 PM PDT 24
Peak memory 223192 kb
Host smart-5af85ea3-c269-44d6-bcc2-a976ddcf806a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519134638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2519134638
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4280891032
Short name T530
Test name
Test status
Simulation time 20687056 ps
CPU time 0.76 seconds
Started Apr 04 12:57:26 PM PDT 24
Finished Apr 04 12:57:27 PM PDT 24
Peak memory 206312 kb
Host smart-d49befa8-09b5-475c-8c33-e688422debca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280891032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4280891032
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2211030649
Short name T317
Test name
Test status
Simulation time 3218069653 ps
CPU time 48.27 seconds
Started Apr 04 12:57:30 PM PDT 24
Finished Apr 04 12:58:18 PM PDT 24
Peak memory 249400 kb
Host smart-a6cafca6-108b-4afd-8f42-71d12157b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211030649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2211030649
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1641747676
Short name T346
Test name
Test status
Simulation time 41303429249 ps
CPU time 159.84 seconds
Started Apr 04 12:57:27 PM PDT 24
Finished Apr 04 01:00:07 PM PDT 24
Peak memory 238968 kb
Host smart-8c821e4c-0e05-410a-a76c-e03f8c1108c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641747676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1641747676
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2111894388
Short name T724
Test name
Test status
Simulation time 43394579 ps
CPU time 1.06 seconds
Started Apr 04 12:57:24 PM PDT 24
Finished Apr 04 12:57:26 PM PDT 24
Peak memory 216976 kb
Host smart-4663a930-8665-46c3-92b0-a9b136d6ceda
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111894388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2111894388
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.384681726
Short name T286
Test name
Test status
Simulation time 385635995 ps
CPU time 3.82 seconds
Started Apr 04 12:57:26 PM PDT 24
Finished Apr 04 12:57:30 PM PDT 24
Peak memory 222868 kb
Host smart-febd3c5a-61b3-4e7a-906c-0309bb9e73b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384681726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
384681726
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.1593019235
Short name T517
Test name
Test status
Simulation time 33038160 ps
CPU time 0.71 seconds
Started Apr 04 12:57:26 PM PDT 24
Finished Apr 04 12:57:27 PM PDT 24
Peak memory 216092 kb
Host smart-37241c97-7824-424c-a19e-f588b0a4782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593019235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.1593019235
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1767855009
Short name T440
Test name
Test status
Simulation time 2431705811 ps
CPU time 8.24 seconds
Started Apr 04 12:57:30 PM PDT 24
Finished Apr 04 12:57:39 PM PDT 24
Peak memory 221616 kb
Host smart-f83a5008-eaf5-434e-8ffa-9e5bde1a2561
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1767855009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1767855009
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2194260337
Short name T413
Test name
Test status
Simulation time 83773700 ps
CPU time 1.92 seconds
Started Apr 04 12:57:25 PM PDT 24
Finished Apr 04 12:57:27 PM PDT 24
Peak memory 216356 kb
Host smart-e587eb97-6e60-417b-b24a-cd930637ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194260337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2194260337
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1399341329
Short name T572
Test name
Test status
Simulation time 5203480942 ps
CPU time 8.52 seconds
Started Apr 04 12:57:23 PM PDT 24
Finished Apr 04 12:57:32 PM PDT 24
Peak memory 216652 kb
Host smart-42f281de-76c9-4b8d-9daa-077562100a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399341329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1399341329
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2383257457
Short name T392
Test name
Test status
Simulation time 66751650 ps
CPU time 1.53 seconds
Started Apr 04 12:57:25 PM PDT 24
Finished Apr 04 12:57:26 PM PDT 24
Peak memory 216504 kb
Host smart-62b7cf4d-e380-476b-a95a-d9fdb2cffcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383257457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2383257457
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.133901364
Short name T432
Test name
Test status
Simulation time 109107097 ps
CPU time 1.07 seconds
Started Apr 04 12:57:27 PM PDT 24
Finished Apr 04 12:57:28 PM PDT 24
Peak memory 206800 kb
Host smart-7e7eafb6-c6e7-491d-b517-30e5fbbe3b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133901364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.133901364
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3808084208
Short name T5
Test name
Test status
Simulation time 1149613529 ps
CPU time 5.83 seconds
Started Apr 04 12:57:32 PM PDT 24
Finished Apr 04 12:57:38 PM PDT 24
Peak memory 223236 kb
Host smart-08e9aab2-4bb9-4a09-9bca-3e21b3c3bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808084208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3808084208
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.597042400
Short name T601
Test name
Test status
Simulation time 41451024 ps
CPU time 0.73 seconds
Started Apr 04 12:57:47 PM PDT 24
Finished Apr 04 12:57:48 PM PDT 24
Peak memory 205720 kb
Host smart-7c974025-1a9b-4051-be7e-78eafdc2359e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597042400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.597042400
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3697564856
Short name T739
Test name
Test status
Simulation time 17517703 ps
CPU time 0.81 seconds
Started Apr 04 12:57:33 PM PDT 24
Finished Apr 04 12:57:34 PM PDT 24
Peak memory 206636 kb
Host smart-f2bd0b05-ed5e-43f8-985d-6e776cd7228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697564856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3697564856
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3721981009
Short name T363
Test name
Test status
Simulation time 1494147207 ps
CPU time 14.42 seconds
Started Apr 04 12:57:41 PM PDT 24
Finished Apr 04 12:57:55 PM PDT 24
Peak memory 250792 kb
Host smart-b8974476-4d96-4f27-a51e-cc650fa50d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721981009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3721981009
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1593709245
Short name T355
Test name
Test status
Simulation time 735351100 ps
CPU time 5.22 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:57:44 PM PDT 24
Peak memory 233540 kb
Host smart-092d856f-e084-4c7c-b856-a5ab55340fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593709245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1593709245
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1048665042
Short name T744
Test name
Test status
Simulation time 15752561 ps
CPU time 1.02 seconds
Started Apr 04 12:57:40 PM PDT 24
Finished Apr 04 12:57:42 PM PDT 24
Peak memory 217032 kb
Host smart-a7d8571c-a51b-4f4f-8c66-5deec679fccc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048665042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1048665042
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1815627768
Short name T364
Test name
Test status
Simulation time 51881533488 ps
CPU time 32.06 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:58:12 PM PDT 24
Peak memory 235976 kb
Host smart-19404710-1042-4fd3-b6cc-71bbab07dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815627768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1815627768
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.807888260
Short name T581
Test name
Test status
Simulation time 24466440 ps
CPU time 0.72 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:57:41 PM PDT 24
Peak memory 216384 kb
Host smart-d0a5e6b9-a439-4030-997d-9243e314d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807888260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.807888260
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1577284437
Short name T455
Test name
Test status
Simulation time 77008433 ps
CPU time 3.53 seconds
Started Apr 04 12:57:40 PM PDT 24
Finished Apr 04 12:57:44 PM PDT 24
Peak memory 220292 kb
Host smart-16fc4e16-1ec7-4356-a4ca-62bac2781d26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577284437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1577284437
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1325999236
Short name T370
Test name
Test status
Simulation time 118952057 ps
CPU time 0.88 seconds
Started Apr 04 12:57:49 PM PDT 24
Finished Apr 04 12:57:50 PM PDT 24
Peak memory 206596 kb
Host smart-b4ab5d83-7afb-4745-b048-013b5912e474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325999236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1325999236
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2885404285
Short name T592
Test name
Test status
Simulation time 6586524581 ps
CPU time 33.09 seconds
Started Apr 04 12:57:42 PM PDT 24
Finished Apr 04 12:58:15 PM PDT 24
Peak memory 221252 kb
Host smart-a1bd8ed2-fcb9-42b0-b129-60e7ee124feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885404285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2885404285
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.125405334
Short name T622
Test name
Test status
Simulation time 230154517 ps
CPU time 2.07 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:57:41 PM PDT 24
Peak memory 216380 kb
Host smart-bef8002a-f2fd-4679-8406-24b44c9fb101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125405334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.125405334
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2587946989
Short name T411
Test name
Test status
Simulation time 241798904 ps
CPU time 3.95 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:57:44 PM PDT 24
Peak memory 216544 kb
Host smart-a1d946dc-7734-4bf3-b2de-aff361e5cd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587946989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2587946989
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.680615354
Short name T439
Test name
Test status
Simulation time 159090066 ps
CPU time 1.11 seconds
Started Apr 04 12:57:39 PM PDT 24
Finished Apr 04 12:57:41 PM PDT 24
Peak memory 206888 kb
Host smart-0d10a8ce-7486-4aca-8d24-f3d71ba98631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680615354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.680615354
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.678561619
Short name T336
Test name
Test status
Simulation time 371630304 ps
CPU time 2.31 seconds
Started Apr 04 12:57:44 PM PDT 24
Finished Apr 04 12:57:46 PM PDT 24
Peak memory 222528 kb
Host smart-4340080a-63b4-45da-9c35-50cc97b3e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678561619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.678561619
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1952825678
Short name T679
Test name
Test status
Simulation time 11277440 ps
CPU time 0.71 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:57:57 PM PDT 24
Peak memory 204832 kb
Host smart-e94631e8-5d4b-4249-95dd-9aa63f53ae2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952825678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
952825678
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3172150941
Short name T422
Test name
Test status
Simulation time 22748838 ps
CPU time 0.74 seconds
Started Apr 04 12:57:47 PM PDT 24
Finished Apr 04 12:57:48 PM PDT 24
Peak memory 206592 kb
Host smart-85af3641-fce0-4060-9437-dff172c5cc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172150941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3172150941
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3087386464
Short name T310
Test name
Test status
Simulation time 50789045520 ps
CPU time 182.21 seconds
Started Apr 04 12:57:57 PM PDT 24
Finished Apr 04 01:00:59 PM PDT 24
Peak memory 237484 kb
Host smart-31458da5-0d8c-4cb3-815e-5f3739070b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087386464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3087386464
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3545177726
Short name T264
Test name
Test status
Simulation time 6170467957 ps
CPU time 17.84 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:58:14 PM PDT 24
Peak memory 223308 kb
Host smart-221bc329-a9af-4079-97be-ff49d36cc155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545177726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3545177726
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.214137117
Short name T746
Test name
Test status
Simulation time 33838891 ps
CPU time 1.04 seconds
Started Apr 04 12:57:46 PM PDT 24
Finished Apr 04 12:57:48 PM PDT 24
Peak memory 216880 kb
Host smart-7d05c3d5-ba22-471e-839f-5d3b2c65f28c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214137117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.214137117
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2844998208
Short name T75
Test name
Test status
Simulation time 18734563972 ps
CPU time 9.57 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:58:06 PM PDT 24
Peak memory 241064 kb
Host smart-527b03aa-1e06-42f8-9991-7dd8e9447686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844998208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2844998208
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.1794673566
Short name T650
Test name
Test status
Simulation time 18316745 ps
CPU time 0.77 seconds
Started Apr 04 12:57:46 PM PDT 24
Finished Apr 04 12:57:47 PM PDT 24
Peak memory 216368 kb
Host smart-99e27ac3-8cc2-4bc3-8ab6-1f523e3a1a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794673566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.1794673566
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3132109553
Short name T6
Test name
Test status
Simulation time 2684052968 ps
CPU time 9.83 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:58:06 PM PDT 24
Peak memory 222060 kb
Host smart-f0ab1ab5-c68d-455e-993d-daa94f32aa2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132109553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3132109553
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3171366126
Short name T627
Test name
Test status
Simulation time 2192920175 ps
CPU time 9.08 seconds
Started Apr 04 12:57:48 PM PDT 24
Finished Apr 04 12:57:57 PM PDT 24
Peak memory 216492 kb
Host smart-8f0f6275-3760-41dc-9682-002e7966c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171366126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3171366126
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4116274823
Short name T18
Test name
Test status
Simulation time 250517179 ps
CPU time 1.59 seconds
Started Apr 04 12:57:57 PM PDT 24
Finished Apr 04 12:57:59 PM PDT 24
Peak memory 216572 kb
Host smart-dfcc04f5-0d27-445b-8ef1-3ff86277e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116274823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4116274823
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.933117541
Short name T595
Test name
Test status
Simulation time 166605410 ps
CPU time 0.9 seconds
Started Apr 04 12:57:55 PM PDT 24
Finished Apr 04 12:57:56 PM PDT 24
Peak memory 205888 kb
Host smart-db0b8958-bf0c-4154-b8f6-3564d52ff5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933117541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.933117541
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1479498202
Short name T586
Test name
Test status
Simulation time 35217907 ps
CPU time 0.71 seconds
Started Apr 04 12:58:18 PM PDT 24
Finished Apr 04 12:58:19 PM PDT 24
Peak memory 204820 kb
Host smart-c3cc6fb1-3882-4465-a76a-967d241fd559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479498202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
479498202
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2136241916
Short name T97
Test name
Test status
Simulation time 132987037 ps
CPU time 3.12 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:12 PM PDT 24
Peak memory 219980 kb
Host smart-2f76d353-25bd-4545-97b5-a923b8ccf12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136241916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2136241916
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4289889481
Short name T533
Test name
Test status
Simulation time 22519080 ps
CPU time 0.83 seconds
Started Apr 04 12:57:56 PM PDT 24
Finished Apr 04 12:57:57 PM PDT 24
Peak memory 206524 kb
Host smart-df91e858-15b6-4527-ae68-cde42e2c9ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289889481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4289889481
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3957044334
Short name T135
Test name
Test status
Simulation time 3694791464 ps
CPU time 34.6 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:43 PM PDT 24
Peak memory 236696 kb
Host smart-b2b0a824-6c41-40af-9d23-5427175d67d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957044334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3957044334
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.37923479
Short name T467
Test name
Test status
Simulation time 56033354 ps
CPU time 1.01 seconds
Started Apr 04 12:57:55 PM PDT 24
Finished Apr 04 12:57:57 PM PDT 24
Peak memory 218216 kb
Host smart-f7444a6f-4ff0-4c77-ac71-d6b0e3b0d081
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37923479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.37923479
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2355390611
Short name T704
Test name
Test status
Simulation time 26580514 ps
CPU time 0.74 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:10 PM PDT 24
Peak memory 216372 kb
Host smart-099d3cf1-fb0d-4e2a-8c24-1576ec248501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355390611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2355390611
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1907215725
Short name T513
Test name
Test status
Simulation time 328411968 ps
CPU time 3.86 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:13 PM PDT 24
Peak memory 220396 kb
Host smart-d7c2c3ab-c7cb-4640-91a8-a0b7b8659b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1907215725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1907215725
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.656593121
Short name T709
Test name
Test status
Simulation time 5926548161 ps
CPU time 28.75 seconds
Started Apr 04 12:58:07 PM PDT 24
Finished Apr 04 12:58:36 PM PDT 24
Peak memory 216560 kb
Host smart-3e01d38e-68c5-4e2c-a0a5-80648ef9ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656593121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.656593121
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.452363516
Short name T116
Test name
Test status
Simulation time 12050380922 ps
CPU time 12.52 seconds
Started Apr 04 12:58:10 PM PDT 24
Finished Apr 04 12:58:23 PM PDT 24
Peak memory 216648 kb
Host smart-2226bc13-cf84-4e5a-8afa-5a38ed4e4b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452363516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.452363516
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3693120994
Short name T573
Test name
Test status
Simulation time 30664882 ps
CPU time 0.99 seconds
Started Apr 04 12:58:08 PM PDT 24
Finished Apr 04 12:58:09 PM PDT 24
Peak memory 206984 kb
Host smart-62188e7c-0168-4f06-89e8-2ee49ecd06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693120994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3693120994
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3029466684
Short name T692
Test name
Test status
Simulation time 706811830 ps
CPU time 1.15 seconds
Started Apr 04 12:58:10 PM PDT 24
Finished Apr 04 12:58:11 PM PDT 24
Peak memory 206800 kb
Host smart-c497ce05-7d4b-44ef-a363-610c955781ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029466684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3029466684
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2903805708
Short name T53
Test name
Test status
Simulation time 948996051 ps
CPU time 9.31 seconds
Started Apr 04 12:58:09 PM PDT 24
Finished Apr 04 12:58:19 PM PDT 24
Peak memory 223456 kb
Host smart-ad5e523d-32f9-4e97-83b3-a73dc6378864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903805708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2903805708
Directory /workspace/9.spi_device_upload/latest
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