Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1508005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1670865

1

T1

108

T2

900

T3

1084

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2472946	1			T1	101		T2	8		T3	405
values[0x0]	351590	1			T1	48		T2	453		T3	438
values[0x1]	354334	1			T1	52		T2	446		T3	447

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1144215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2034655

1

T1

163

T2

902

T3

1127

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13388	1			T2	4		T3	10		T13	73
valid_sources[0x01]	11337	1			T2	6		T3	4		T13	80
valid_sources[0x02]	10117	1			T2	5		T3	1		T13	77
valid_sources[0x03]	15887	1			T2	4		T3	5		T13	79
valid_sources[0x04]	11049	1			T2	2		T3	7		T13	83
valid_sources[0x05]	10553	1			T2	9		T13	57		T5	9
valid_sources[0x06]	12778	1			T2	10		T3	9		T13	110
valid_sources[0x07]	11345	1			T2	3		T13	80		T5	1
valid_sources[0x08]	10325	1			T2	1		T3	2		T13	69
valid_sources[0x09]	10376	1			T2	3		T3	4		T13	83
valid_sources[0x0a]	13444	1			T2	5		T3	6		T13	76
valid_sources[0x0b]	29126	1			T2	4		T3	3		T13	61
valid_sources[0x0c]	10517	1			T2	6		T3	6		T13	69
valid_sources[0x0d]	11409	1			T2	2		T3	3		T13	95
valid_sources[0x0e]	11203	1			T2	2		T3	8		T13	79
valid_sources[0x0f]	11168	1			T2	3		T13	77		T5	13
valid_sources[0x10]	10440	1			T2	6		T3	2		T13	75
valid_sources[0x11]	22477	1			T2	1		T3	5		T13	78
valid_sources[0x12]	11265	1			T2	1		T3	8		T13	90
valid_sources[0x13]	10796	1			T2	2		T13	91		T5	13
valid_sources[0x14]	10514	1			T2	7		T13	73		T5	18
valid_sources[0x15]	11128	1			T2	6		T3	2		T13	98
valid_sources[0x16]	11514	1			T2	5		T3	7		T13	73
valid_sources[0x17]	21042	1			T2	4		T3	5		T13	75
valid_sources[0x18]	12928	1			T2	2		T3	2		T13	66
valid_sources[0x19]	10607	1			T2	5		T3	12		T13	95
valid_sources[0x1a]	10878	1			T2	9		T3	12		T13	88
valid_sources[0x1b]	10145	1			T2	5		T3	5		T13	73
valid_sources[0x1c]	22352	1			T2	4		T3	12		T13	71
valid_sources[0x1d]	11794	1			T3	2		T13	76		T5	7
valid_sources[0x1e]	11871	1			T2	4		T3	2		T13	82
valid_sources[0x1f]	11074	1			T2	2		T13	71		T5	2
valid_sources[0x20]	10498	1			T2	7		T3	9		T13	82
valid_sources[0x21]	10545	1			T2	2		T3	1		T13	96
valid_sources[0x22]	10790	1			T2	1		T3	3		T13	82
valid_sources[0x23]	11228	1			T2	3		T3	2		T13	103
valid_sources[0x24]	11073	1			T2	3		T3	4		T13	90
valid_sources[0x25]	10582	1			T2	3		T13	63		T5	7
valid_sources[0x26]	10767	1			T2	5		T3	2		T13	89
valid_sources[0x27]	19929	1			T2	3		T3	2		T13	90
valid_sources[0x28]	11457	1			T2	4		T3	6		T13	88
valid_sources[0x29]	10515	1			T2	2		T3	6		T13	83
valid_sources[0x2a]	13267	1			T2	6		T3	1		T13	84
valid_sources[0x2b]	15323	1			T2	4		T3	4		T13	86
valid_sources[0x2c]	11769	1			T2	5		T3	7		T13	65
valid_sources[0x2d]	13446	1			T2	5		T3	6		T13	69
valid_sources[0x2e]	11544	1			T2	2		T3	4		T13	82
valid_sources[0x2f]	10029	1			T2	5		T3	3		T13	75
valid_sources[0x30]	10747	1			T3	4		T13	94		T5	11
valid_sources[0x31]	10121	1			T2	7		T3	6		T13	70
valid_sources[0x32]	15893	1			T2	5		T3	1		T13	57
valid_sources[0x33]	11350	1			T2	1		T3	8		T13	73
valid_sources[0x34]	13189	1			T2	4		T3	5		T13	94
valid_sources[0x35]	11227	1			T2	2		T3	5		T13	62
valid_sources[0x36]	11077	1			T2	5		T3	1		T13	105
valid_sources[0x37]	11335	1			T2	3		T3	5		T13	107
valid_sources[0x38]	33289	1			T2	5		T3	6		T13	77
valid_sources[0x39]	15122	1			T2	4		T3	11		T13	75
valid_sources[0x3a]	11831	1			T2	1		T3	3		T13	114
valid_sources[0x3b]	10634	1			T2	1		T3	16		T13	82
valid_sources[0x3c]	11509	1			T2	4		T3	7		T13	72
valid_sources[0x3d]	11587	1			T2	5		T3	5		T13	99
valid_sources[0x3e]	11794	1			T2	5		T3	5		T13	83
valid_sources[0x3f]	11763	1			T2	14		T3	10		T13	101
valid_sources[0x40]	11712	1			T2	5		T3	11		T13	85
valid_sources[0x41]	11672	1			T3	4		T13	69		T5	10
valid_sources[0x42]	10331	1			T2	8		T3	8		T13	106
valid_sources[0x43]	12106	1			T2	6		T3	3		T13	93
valid_sources[0x44]	11902	1			T2	4		T3	1		T13	82
valid_sources[0x45]	11512	1			T2	6		T3	11		T13	82
valid_sources[0x46]	10114	1			T2	3		T3	6		T13	70
valid_sources[0x47]	10317	1			T2	2		T3	2		T13	80
valid_sources[0x48]	10706	1			T2	9		T3	7		T13	86
valid_sources[0x49]	10052	1			T2	3		T3	5		T13	75
valid_sources[0x4a]	10379	1			T2	4		T3	4		T13	78
valid_sources[0x4b]	10890	1			T2	4		T3	1		T13	107
valid_sources[0x4c]	12076	1			T2	3		T3	6		T13	83
valid_sources[0x4d]	29811	1			T2	1		T3	4		T13	69
valid_sources[0x4e]	10283	1			T2	5		T3	3		T13	85
valid_sources[0x4f]	10248	1			T2	4		T3	6		T13	68
valid_sources[0x50]	15595	1			T2	7		T3	5		T13	100
valid_sources[0x51]	10644	1			T2	3		T3	3		T13	108
valid_sources[0x52]	11248	1			T2	2		T3	6		T13	74
valid_sources[0x53]	10169	1			T2	2		T13	86		T5	13
valid_sources[0x54]	10941	1			T2	4		T3	9		T13	79
valid_sources[0x55]	15461	1			T2	5		T3	6		T13	74
valid_sources[0x56]	17788	1			T2	1		T3	7		T13	59
valid_sources[0x57]	11281	1			T2	2		T3	7		T13	99
valid_sources[0x58]	11279	1			T2	3		T3	4		T13	104
valid_sources[0x59]	29233	1			T2	3		T13	90		T5	8
valid_sources[0x5a]	10958	1			T2	3		T3	11		T13	72
valid_sources[0x5b]	11303	1			T2	2		T3	4		T13	99
valid_sources[0x5c]	12815	1			T2	1		T3	3		T13	79
valid_sources[0x5d]	11284	1			T2	3		T3	4		T13	94
valid_sources[0x5e]	10140	1			T2	1		T3	9		T13	84
valid_sources[0x5f]	11360	1			T3	6		T13	75		T5	3
valid_sources[0x60]	14641	1			T2	3		T3	6		T13	73
valid_sources[0x61]	10667	1			T2	8		T3	11		T13	102
valid_sources[0x62]	11256	1			T1	201		T2	1		T3	4
valid_sources[0x63]	10402	1			T2	5		T3	4		T13	85
valid_sources[0x64]	10731	1			T2	4		T3	15		T13	89
valid_sources[0x65]	32765	1			T2	4		T3	1		T13	70
valid_sources[0x66]	16266	1			T2	5		T3	4		T13	72
valid_sources[0x67]	11705	1			T2	1		T3	4		T13	82
valid_sources[0x68]	12998	1			T2	2		T3	4		T13	68
valid_sources[0x69]	19355	1			T2	8		T3	7		T13	78
valid_sources[0x6a]	11576	1			T2	8		T3	9		T13	78
valid_sources[0x6b]	10280	1			T2	2		T3	5		T13	70
valid_sources[0x6c]	10535	1			T2	2		T3	8		T13	91
valid_sources[0x6d]	10733	1			T2	2		T3	2		T13	80
valid_sources[0x6e]	10717	1			T2	3		T13	93		T5	4
valid_sources[0x6f]	11103	1			T2	4		T3	6		T13	78
valid_sources[0x70]	11175	1			T2	3		T3	6		T13	75
valid_sources[0x71]	18252	1			T2	6		T3	5		T13	85
valid_sources[0x72]	10880	1			T2	3		T3	7		T13	82
valid_sources[0x73]	10676	1			T2	5		T3	5		T13	73
valid_sources[0x74]	12490	1			T2	2		T3	6		T13	83
valid_sources[0x75]	14230	1			T2	6		T3	9		T13	86
valid_sources[0x76]	10553	1			T2	4		T3	2		T13	78
valid_sources[0x77]	10048	1			T2	2		T3	2		T13	67
valid_sources[0x78]	11429	1			T2	4		T3	4		T13	81
valid_sources[0x79]	10729	1			T2	1		T3	6		T13	75
valid_sources[0x7a]	10390	1			T2	1		T3	2		T13	74
valid_sources[0x7b]	11524	1			T2	1		T3	5		T13	74
valid_sources[0x7c]	13558	1			T2	3		T3	7		T13	76
valid_sources[0x7d]	12197	1			T2	3		T13	80		T5	18
valid_sources[0x7e]	12080	1			T2	6		T3	8		T13	78
valid_sources[0x7f]	11968	1			T2	6		T3	8		T13	89
valid_sources[0x80]	11319	1			T2	4		T3	2		T13	108

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1032394

1

T1

8

T2

2

T3

204

values[0x0]

all_enables

biggest_size

321850

1

T1

48

T2

453

T3

438

values[0x1]

all_enables

biggest_size

316621

1

T1

52

T2

445

T3

442