Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1526178

1

T2

7

T3

206

T7

219

full_word

1669773

1

T2

900

T3

1084

T7

908

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3195511	1			T2	907		T3	1290		T7	1127
auto[TlIntgErrCmd]	137	1			T110	8		T117	3		T118	6
auto[TlIntgErrData]	152	1			T110	4		T117	4		T118	7
auto[TlIntgErrBoth]	151	1			T110	8		T117	3		T118	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2474335

1

T2

8

T3

405

T7

1

auto[1]

721616

1

T2

899

T3

885

T7

1126

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1441677	1			T2	6		T3	201		T7	1
auto[TlIntgErrNone]	partial	auto[1]	84095	1			T2	1		T3	5		T7	218
auto[TlIntgErrNone]	full_word	auto[0]	1032456	1			T2	2		T3	204		T13	1512
auto[TlIntgErrNone]	full_word	auto[1]	637283	1			T2	898		T3	880		T7	908
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T117	1		T118	4		T131	4
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T110	8		T117	1		T118	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T117	1		T351	1		T352	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T131	2		T349	1		T353	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T110	1		T117	1		T118	4
auto[TlIntgErrData]	partial	auto[1]	74	1			T110	3		T117	2		T118	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T117	1		T132	1		T354	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T132	1		T351	1		T355	2
auto[TlIntgErrBoth]	partial	auto[0]	67	1			T110	4		T117	3		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T110	4		T118	3		T131	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T118	1		T351	1		T356	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T118	1		T132	1		T355	1