Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	121538991	2996963	0	0
DepthKnown_A	121538991	121427874	0	0
RvalidKnown_A	121538991	121427874	0	0
WreadyKnown_A	121538991	121427874	0	0
gen_passthru_fifo.paramCheckPass	861	861	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	2996963	0	0
T1	1743	1	0	0
T2	47717	75	0	0
T3	20920	458	0	0
T4	111113	5768	0	0
T5	111096	1671	0	0
T6	20249	539	0	0
T7	531049	1127	0	0
T8	63598	3098	0	0
T13	115503	19692	0	0
T14	4110	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	861	861	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	121538991	5662340	0	0
DepthKnown_A	121538991	121427874	0	0
RvalidKnown_A	121538991	121427874	0	0
WreadyKnown_A	121538991	121427874	0	0
gen_passthru_fifo.paramCheckPass	861	861	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	5662340	0	0
T1	1743	1	0	0
T2	47717	234	0	0
T3	20920	1332	0	0
T4	111113	5766	0	0
T5	111096	1670	0	0
T6	20249	539	0	0
T7	531049	1127	0	0
T8	63598	3098	0	0
T13	115503	19611	0	0
T14	4110	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121538991	121427874	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	861	861	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0