Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	100.00	70.37			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	55.51	86.36	44.44			60.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
55.51	86.36

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T17
1	0	Covered	T13,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T14
1	0	Unreachable
1	1	Covered	T13,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
55.51	44.44

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	198282977	158013613	0	0
CheckNGreaterZero_A	2058	2058	0	0
GntImpliesReady_A	198282977	717022	0	0
GntImpliesValid_A	198282977	717022	0	0
GrantKnown_A	198282977	158013613	0	0
IdxKnown_A	198282977	158013613	0	0
IndexIsCorrect_A	198282977	717022	0	0
LockArbDecision_A	198282977	0	0	0
NoReadyValidNoGrant_A	198282977	0	0	0
ReadyAndValidImplyGrant_A	198282977	717022	0	0
ReqAndReadyImplyGrant_A	198282977	717022	0	0
ReqImpliesValid_A	198282977	717022	0	0
ReqStaysHighUntilGranted0_M	198282977	0	0	0
RoundRobin_A	198282977	0	0	686
ValidKnown_A	198282977	158013613	0	0
gen_data_port_assertion.DataFlow_A	198282977	717022	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	158013613	0	0
T1	1743	1647	0	0
T2	160661	159942	0	0
T3	56280	56223	0	0
T4	182197	145855	0	0
T5	387668	249036	0	0
T6	71231	45660	0	0
T7	801277	654633	0	0
T8	91410	77054	0	0
T9	173799	173456	0	0
T10	12272	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	441133	267662	0	0
T14	4830	4382	0	0
T15	1558	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2058	2058	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	158013613	0	0
T1	1743	1647	0	0
T2	160661	159942	0	0
T3	56280	56223	0	0
T4	182197	145855	0	0
T5	387668	249036	0	0
T6	71231	45660	0	0
T7	801277	654633	0	0
T8	91410	77054	0	0
T9	173799	173456	0	0
T10	12272	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	441133	267662	0	0
T14	4830	4382	0	0
T15	1558	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	158013613	0	0
T1	1743	1647	0	0
T2	160661	159942	0	0
T3	56280	56223	0	0
T4	182197	145855	0	0
T5	387668	249036	0	0
T6	71231	45660	0	0
T7	801277	654633	0	0
T8	91410	77054	0	0
T9	173799	173456	0	0
T10	12272	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	441133	267662	0	0
T14	4830	4382	0	0
T15	1558	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	0	0	686

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	158013613	0	0
T1	1743	1647	0	0
T2	160661	159942	0	0
T3	56280	56223	0	0
T4	182197	145855	0	0
T5	387668	249036	0	0
T6	71231	45660	0	0
T7	801277	654633	0	0
T8	91410	77054	0	0
T9	173799	173456	0	0
T10	12272	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	441133	267662	0	0
T14	4830	4382	0	0
T15	1558	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198282977	717022	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	146655	832	0	0
T5	249382	832	0	0
T6	45740	832	0	0
T7	531049	0	0	0
T8	77504	832	0	0
T9	173799	832	0	0
T10	12272	832	0	0
T11	20854	0	0	0
T13	278318	10133	0	0
T14	4470	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	19	86.36
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	3	75.00
ALWAYS	124	4	3	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	0	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	1	50.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39628215	25666802	0	0
CheckNGreaterZero_A	686	686	0	0
GntImpliesReady_A	39628215	0	0	0
GntImpliesValid_A	39628215	0	0	0
GrantKnown_A	39628215	25666802	0	0
IdxKnown_A	39628215	25666802	0	0
IndexIsCorrect_A	39628215	0	0	0
LockArbDecision_A	39628215	0	0	0
NoReadyValidNoGrant_A	39628215	0	0	0
ReadyAndValidImplyGrant_A	39628215	0	0	0
ReqAndReadyImplyGrant_A	39628215	0	0	0
ReqImpliesValid_A	39628215	0	0	0
ReqStaysHighUntilGranted0_M	39628215	0	0	0
RoundRobin_A	39628215	0	0	0
ValidKnown_A	39628215	25666802	0	0
gen_data_port_assertion.DataFlow_A	39628215	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	25666802	0	0
T2	112944	112284	0	0
T3	35360	35360	0	0
T4	35542	34816	0	0
T5	138286	137948	0	0
T6	25491	25491	0	0
T7	135114	0	0	0
T8	13906	13536	0	0
T9	0	173456	0	0
T10	0	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	162815	0	0	0
T14	360	0	0	0
T15	779	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686	686	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	25666802	0	0
T2	112944	112284	0	0
T3	35360	35360	0	0
T4	35542	34816	0	0
T5	138286	137948	0	0
T6	25491	25491	0	0
T7	135114	0	0	0
T8	13906	13536	0	0
T9	0	173456	0	0
T10	0	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	162815	0	0	0
T14	360	0	0	0
T15	779	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	25666802	0	0
T2	112944	112284	0	0
T3	35360	35360	0	0
T4	35542	34816	0	0
T5	138286	137948	0	0
T6	25491	25491	0	0
T7	135114	0	0	0
T8	13906	13536	0	0
T9	0	173456	0	0
T10	0	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	162815	0	0	0
T14	360	0	0	0
T15	779	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	25666802	0	0
T2	112944	112284	0	0
T3	35360	35360	0	0
T4	35542	34816	0	0
T5	138286	137948	0	0
T6	25491	25491	0	0
T7	135114	0	0	0
T8	13906	13536	0	0
T9	0	173456	0	0
T10	0	12272	0	0
T11	0	20368	0	0
T12	0	117722	0	0
T13	162815	0	0	0
T14	360	0	0	0
T15	779	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T17
1	0	Covered	T13,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T14
1	0	Unreachable
1	1	Covered	T13,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T16,T17
0	0	1	Unreachable
0	0	0	Covered	T7,T13,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39628215	13383242	0	0
CheckNGreaterZero_A	686	686	0	0
GntImpliesReady_A	39628215	235013	0	0
GntImpliesValid_A	39628215	235013	0	0
GrantKnown_A	39628215	13383242	0	0
IdxKnown_A	39628215	13383242	0	0
IndexIsCorrect_A	39628215	235013	0	0
LockArbDecision_A	39628215	0	0	0
NoReadyValidNoGrant_A	39628215	0	0	0
ReadyAndValidImplyGrant_A	39628215	235013	0	0
ReqAndReadyImplyGrant_A	39628215	235013	0	0
ReqImpliesValid_A	39628215	235013	0	0
ReqStaysHighUntilGranted0_M	39628215	0	0	0
RoundRobin_A	39628215	0	0	0
ValidKnown_A	39628215	13383242	0	0
gen_data_port_assertion.DataFlow_A	39628215	235013	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	13383242	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T7	135114	123664	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T13	162815	152168	0	0
T14	360	360	0	0
T15	779	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686	686	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	13383242	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T7	135114	123664	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T13	162815	152168	0	0
T14	360	360	0	0
T15	779	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	13383242	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T7	135114	123664	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T13	162815	152168	0	0
T14	360	360	0	0
T15	779	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	13383242	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T7	135114	123664	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T13	162815	152168	0	0
T14	360	360	0	0
T15	779	432	0	0
T16	0	455080	0	0
T17	0	262840	0	0
T23	0	72	0	0
T54	0	144	0	0
T55	0	464	0	0
T56	0	576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39628215	235013	0	0
T4	35542	0	0	0
T5	138286	0	0	0
T6	25491	0	0	0
T8	13906	0	0	0
T9	173799	0	0	0
T10	12272	0	0	0
T11	20854	0	0	0
T13	162815	6935	0	0
T14	360	0	0	0
T15	779	0	0	0
T16	0	7827	0	0
T17	0	8035	0	0
T55	0	11	0	0
T57	0	51	0	0
T58	0	884	0	0
T59	0	167	0	0
T60	0	2841	0	0
T61	0	160	0	0
T62	0	159	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T13,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T13,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	119026547	118963569	0	0
CheckNGreaterZero_A	686	686	0	0
GntImpliesReady_A	119026547	482009	0	0
GntImpliesValid_A	119026547	482009	0	0
GrantKnown_A	119026547	118963569	0	0
IdxKnown_A	119026547	118963569	0	0
IndexIsCorrect_A	119026547	482009	0	0
LockArbDecision_A	119026547	0	0	0
NoReadyValidNoGrant_A	119026547	0	0	0
ReadyAndValidImplyGrant_A	119026547	482009	0	0
ReqAndReadyImplyGrant_A	119026547	482009	0	0
ReqImpliesValid_A	119026547	482009	0	0
ReqStaysHighUntilGranted0_M	119026547	0	0	0
RoundRobin_A	119026547	0	0	686
ValidKnown_A	119026547	118963569	0	0
gen_data_port_assertion.DataFlow_A	119026547	482009	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	118963569	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	686	686	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	118963569	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	118963569	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	0	0	686

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	118963569	0	0
T1	1743	1647	0	0
T2	47717	47658	0	0
T3	20920	20863	0	0
T4	111113	111039	0	0
T5	111096	111088	0	0
T6	20249	20169	0	0
T7	531049	530969	0	0
T8	63598	63518	0	0
T13	115503	115494	0	0
T14	4110	4022	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119026547	482009	0	0
T1	1743	200	0	0
T2	47717	832	0	0
T3	20920	832	0	0
T4	111113	832	0	0
T5	111096	832	0	0
T6	20249	832	0	0
T7	531049	0	0	0
T8	63598	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	115503	3198	0	0
T14	4110	0	0	0