Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	251448	1			T1	132		T2	1		T4	1
all_values[1]	251448	1			T1	132		T2	1		T4	1
all_values[2]	251448	1			T1	132		T2	1		T4	1
all_values[3]	251448	1			T1	132		T2	1		T4	1
all_values[4]	251448	1			T1	132		T2	1		T4	1
all_values[5]	251448	1			T1	132		T2	1		T4	1
all_values[6]	251448	1			T1	132		T2	1		T4	1
all_values[7]	251448	1			T1	132		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2008795

1

T1

1056

T2

8

T4

8

auto[1]

2789

1

T23

104

T37

86

T43

67

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2008963

1

T1

1056

T2

8

T4

8

auto[1]

2621

1

T63

5

T23

69

T53

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	250954	1			T1	132		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	147	1			T23	3		T37	8		T43	4
all_values[0]	auto[1]	auto[0]	199	1			T23	10		T37	3		T43	4
all_values[0]	auto[1]	auto[1]	148	1			T23	5		T37	6		T43	4
all_values[1]	auto[0]	auto[0]	250935	1			T1	132		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	151	1			T23	4		T37	3		T43	2
all_values[1]	auto[1]	auto[0]	201	1			T23	10		T37	6		T43	5
all_values[1]	auto[1]	auto[1]	161	1			T23	5		T37	4		T43	7
all_values[2]	auto[0]	auto[0]	250951	1			T1	132		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	148	1			T23	3		T37	8		T43	6
all_values[2]	auto[1]	auto[0]	211	1			T23	10		T37	7		T43	7
all_values[2]	auto[1]	auto[1]	138	1			T23	5		T37	1		T43	1
all_values[3]	auto[0]	auto[0]	250938	1			T1	132		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	167	1			T23	4		T37	2		T43	4
all_values[3]	auto[1]	auto[0]	212	1			T23	5		T37	15		T43	3
all_values[3]	auto[1]	auto[1]	131	1			T23	10		T37	2		T43	1
all_values[4]	auto[0]	auto[0]	250934	1			T1	132		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	164	1			T63	5		T23	3		T53	4
all_values[4]	auto[1]	auto[0]	178	1			T23	5		T37	5		T43	1
all_values[4]	auto[1]	auto[1]	172	1			T23	5		T37	5		T43	1
all_values[5]	auto[0]	auto[0]	250718	1			T1	132		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	379	1			T23	4		T55	4		T58	3
all_values[5]	auto[1]	auto[0]	231	1			T23	4		T37	6		T43	8
all_values[5]	auto[1]	auto[1]	120	1			T23	2		T37	5		T43	5
all_values[6]	auto[0]	auto[0]	250945	1			T1	132		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	152	1			T23	1		T37	3		T43	2
all_values[6]	auto[1]	auto[0]	212	1			T23	14		T37	10		T43	7
all_values[6]	auto[1]	auto[1]	139	1			T23	3		T37	5		T43	5
all_values[7]	auto[0]	auto[0]	250952	1			T1	132		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	160	1			T23	5		T37	7		T43	6
all_values[7]	auto[1]	auto[0]	192	1			T23	4		T37	3		T43	5
all_values[7]	auto[1]	auto[1]	144	1			T23	7		T37	3		T43	3