Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total684010
Category 0684010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total684010
Severity 0684010


Summary for Assertions
NUMBERPERCENT
Total Number684100.00
Uncovered639.21
Success62190.79
Failure00.00
Incomplete10.15
Without Attempts60.88


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00


Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.InterceptLevel_M 0037213908000
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A 00103890405000
tb.dut.g_sram_connect[3].ReqAlwaysAccepted_A 00103890405000
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckAckNeedsReq 0037213250000
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.SyncReqAckHoldReq 00103890405000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 0037213250000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 0037213250000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 0037213250000
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0037213250000
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataHoldSrc2Dst 00103890405000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 00103890405000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 00103890405000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 00103890405000
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0010389040500679
tb.dut.u_tlul2sram_egress.rvalidHighReqFifoEmpty 00103890405000
tb.dut.u_tlul2sram_egress.rvalidHighWhenRspFifoFull 00103890405000
tb.dut.u_tlul2sram_egress.u_rspfifo.DataKnown_A 00103890405000
tb.dut.u_tlul2sram_egress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00103890405000
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DataKnown_A 00103890405000
tb.dut.u_tlul2sram_egress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00103890405000
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_upload.AddrFifoNeverFull_M 0037213250000
tb.dut.u_upload.CmdFifoNeverFull_M 0037213250000
tb.dut.u_upload.CmdFifoPush_A 0037213250000
tb.dut.u_upload.PayloadNeverFull_M 0037213250000
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A 00103890405000
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A 0037213250000
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M 00103890405000
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A 00103890405000
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A 00103890405000
tb.dut.u_upload.u_addrfifo.RptrIncrease_A 00103890405000
tb.dut.u_upload.u_addrfifo.SramRvalid_A 00103890405000
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A 0037213250000
tb.dut.u_upload.u_addrfifo.WptrIncrease_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0037213250000
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 0037213250000
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A 0037213250000
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0037213250000
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A 00103890405000
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A 0037213250000
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M 00103890405000
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A 00103890405000
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A 00103890405000
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A 00103890405000
tb.dut.u_upload.u_cmdfifo.SramRvalid_A 00103890405000
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A 0037213250000
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A 0037213250000
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A 00103890405000
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M 0037213250000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.AlertKnownO_A 0010389040510382794900
tb.dut.CioSdoEnOKnown 0010389040510382794900
tb.dut.CioSdoEnOffWhenInactive 0010389040510382794900
tb.dut.FpvSecCmRegWeOnehotCheck_A 0010389040512000
tb.dut.IntrReadbufFlipOKnown 0010389040510382794900
tb.dut.IntrReadbufWatermarkOKnown 0010389040510382794900
tb.dut.IntrTpmHeaderNotEmptyOKnown 0010389040510382794900
tb.dut.IntrTpmRdfifoCmdEndOKnown 0010389040510382794900
tb.dut.IntrTpmRdfifoDropOKnown 0010389040510382794900
tb.dut.IntrUploadCmdfifoNotEmptyOKnown 0010389040510382794900
tb.dut.IntrUploadPayloadNotEmptyOKnown 0010389040510382794900
tb.dut.IntrUploadPayloadOverflowOKnown 0010389040510382794900
tb.dut.PayloadStartIdxWidthMatch_A 0067967900
tb.dut.SpiModeKnown_A 0010389040510382794900
tb.dut.TpmEnableWhenTpmCsbIdle_M 0010389040520000
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A 0010389040534190400
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A 001038904054203900
tb.dut.g_sram_connect[4].ReqAlwaysAccepted_A 001038904056935500
tb.dut.scanmodeKnown 0010389040510389040500
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A 00106204354355900
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A 00106204354281200
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A 00106204354253000
tb.dut.spi_device_csr_assert.cfg_rd_A 00106204354290900
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A 00106204354619700
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A 00106204354659900
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A 00106204354552300
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A 00106204354639900
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A 00106204354587100
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A 00106204354667800
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A 00106204354556000
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A 00106204354628100
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A 00106204354384500
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A 00106204354407100
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A 00106204354400400
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A 00106204354388200
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A 00106204354392300
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A 00106204354426300
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A 00106204354407000
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A 00106204354398000
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A 00106204354406600
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A 00106204354443000
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A 00106204354417100
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A 00106204354393900
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A 00106204354406400
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A 00106204354401700
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A 00106204354408500
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A 00106204354432600
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A 00106204354366500
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A 00106204354406000
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A 00106204354376600
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A 00106204354415400
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A 00106204354426700
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A 00106204354421600
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A 00106204354420600
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A 00106204354415900
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A 00106204354291600
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A 00106204354261300
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A 00106204354282600
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A 00106204354256400
tb.dut.spi_device_csr_assert.intercept_en_rd_A 00106204354302500
tb.dut.spi_device_csr_assert.intr_enable_rd_A 00106204354401400
tb.dut.spi_device_csr_assert.jedec_cc_rd_A 00106204354280200
tb.dut.spi_device_csr_assert.jedec_id_rd_A 00106204354264700
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A 00106204354271700
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A 00106204354279700
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A 00106204354269800
tb.dut.spi_device_csr_assert.read_threshold_rd_A 00106204354261700
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A 00106204354305800
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A 00106204354266100
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A 00106204354321900
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A 00106204354284000
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A 00106204354263000
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A 00106204354271500
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A 00106204354268400
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A 00106204354266100
tb.dut.spi_device_csr_assert.tpm_rid_rd_A 00106204354265600
tb.dut.spi_device_csr_assert.tpm_sts_rd_A 00106204354272100
tb.dut.tlul_assert_device.aKnown_A 00106204354324886200
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0010620435410610015200
tb.dut.tlul_assert_device.aReadyKnown_A 0010620435410610015200
tb.dut.tlul_assert_device.dKnown_A 00106204354522272200
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0010620435410610015200
tb.dut.tlul_assert_device.dReadyKnown_A 0010620435410610015200
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 0085485400
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 0085485400
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tb.dut.tlul_assert_device.gen_device.aDataKnown_M 0010620488792200800
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 00106204354702700
tb.dut.tlul_assert_device.gen_device.contigMask_M 00106204887251628200
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00106204887388085900
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 00106204354579300
tb.dut.tlul_assert_device.gen_device.legalAParam_M 00106204887324886200
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00106204887522272200
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 00106204887324886200
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00106204887522272200
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00106204887522272200
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00106204887522272200
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 00106204354509400
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00106204354497500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0085485400
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0 007342666300
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0 00372139083721322900
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1 00372132503721271100
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0 00372132503721271100
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0 00372139083721322900
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A 00372132502310710600
tb.dut.u_cmdparse.OnlyOneDatapath_A 0037213250611400
tb.dut.u_cmdparse.SelDpKnown_A 00372132502310710600
tb.dut.u_cmdparse.StKnown_A 00372132502310710600
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0 006663626200
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A 0010389040547600
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M 003721325047600
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A 0010389040528600
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M 003721325028600
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A 0067967900
tb.dut.u_intr_payload_not_empty.IntrTKind_A 0067967900
tb.dut.u_intr_payload_overflow.IntrTKind_A 0067967900
tb.dut.u_intr_readbuf_flip.IntrTKind_A 0067967900
tb.dut.u_intr_readbuf_watermark.IntrTKind_A 0067967900
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A 0067967900
tb.dut.u_intr_tpm_rdfifo_cmd_end.IntrTKind_A 0067967900
tb.dut.u_intr_tpm_rdfifo_drop.IntrTKind_A 0067967900
tb.dut.u_jedec.JedecStKnown_A 00372132502310710600
tb.dut.u_p2s.IoModeChangeValid_A 0037213908250100
tb.dut.u_p2s.IoModeDefault_A 003721390861700
tb.dut.u_passthrough.PassThroughStKnown_A 00372132502310710600
tb.dut.u_passthrough.PayloadSwapConstraint_M 00372132503901600
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A 0037213250102534700
tb.dut.u_readcmd.MailboxSizeMatch_M 00372132502310710600
tb.dut.u_readcmd.ValidCmdConfig_A 00372132504742600
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A 0037213250175800
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M 0037213250786700
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A 0037213250102534700
tb.dut.u_readcmd.u_readsram.NotOverflow_A 003721325025854000
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M 0037213250175800
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M 003721325025843000
tb.dut.u_readcmd.u_readsram.SramReadOnly_A 003721325025854000
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A 0037213250476873300
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0037213250476873300
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A 0037213250451546700
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A 00372132502310710600
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0037213250451546700
tb.dut.u_reg.en2addrHit 00106204354242872900
tb.dut.u_reg.reAfterRv 00106204354242872900
tb.dut.u_reg.rePulse 00106204354212041800
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0085485400
tb.dut.u_reg.u_reg_if.AllowedLatency_A 0085485400
tb.dut.u_reg.u_reg_if.MatchedWidthAssert 0085485400
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A 0085485400
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 0085485400
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 0085485400
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A 0085485400
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck 0085485400
tb.dut.u_reg.u_socket.NotOverflowed_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A 00106204354324886200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A 00106204354522272200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0010620435454797100
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0010620435449717700
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 001062043544687400
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 001062043549515400
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 00106204354263572400
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 00106204354463039100
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 0010620435410610015200
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 0085485400
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 0085485400
tb.dut.u_reg.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 0085485400
tb.dut.u_reg.u_socket.maxN 0085485400
tb.dut.u_reg.wePulse 0010620435430831100
tb.dut.u_s2p.IoModeDefault_A 003721325061700
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A 0067967900
tb.dut.u_scanmode_sync.OutputsKnown_A 0010389040510382794900
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A 0010389040510382794900
tb.dut.u_spi_tpm.CmdAddrAvailable_A 00372132501787400
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A 003721325030127200
tb.dut.u_spi_tpm.CmdAddrInfo_A 00372132503290300
tb.dut.u_spi_tpm.CmdPowerof2_A 0067967900
tb.dut.u_spi_tpm.DataFifoLessThan64_A 0067967900
tb.dut.u_spi_tpm.DataSelKnown_A 00372139081353190800
tb.dut.u_spi_tpm.HwRegCondition2_a 00372132501296000
tb.dut.u_spi_tpm.HwRegCondition_A 00372132503765900
tb.dut.u_spi_tpm.HwRegIdxKnown_A 00372139081353190800
tb.dut.u_spi_tpm.LocalityLatchCondition_A 00372132503765900
tb.dut.u_spi_tpm.RdFifoDepthPoT_A 0067967900
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A 0067967900
tb.dut.u_spi_tpm.RdPowerof2_A 0067967900
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A 00372132503765900
tb.dut.u_spi_tpm.TpmRegSizeMatch_A 0067967900
tb.dut.u_spi_tpm.WrDepthSpec_A 0067967900
tb.dut.u_spi_tpm.WrFifoAvailable_A 003721325015462500
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 0067967900
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 003721325023064100
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DataKnown_A 00372132506935500
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.DepthKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.RvalidKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.WreadyKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00372132506935500
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A 0010389040510382712200
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A 00372132503721271100
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A 0067967900
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A 0067967900
tb.dut.u_spi_tpm.u_sram_fifo.DataKnown_A 0037213250215971200
tb.dut.u_spi_tpm.u_sram_fifo.DepthKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_sram_fifo.RvalidKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_sram_fifo.WreadyKnown_A 00372132501353190800
tb.dut.u_spi_tpm.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0037213250215971200
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 0067967900
tb.dut.u_spi_tpm.u_tpm_wr_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A 0067967900
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckAckNeedsReq 00372132502735200
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.SyncReqAckHoldReq 001038904052520100
tb.dut.u_spid_addr_4b.u_sys2spi_sync.gen_assert_data_src2dst.SyncReqAckDataReg 0067967900
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckAckNeedsReq 003721325033900
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.SyncReqAckHoldReq 0010389040533900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.CannotHaveEccAndParity_A 0067967900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.gen_byte_parity.ParityNeedsByteWriteMask_A 0067967900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.gen_byte_parity.WidthNeedsToBeByteAligned_A 0067967900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A 0010389040541125900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortB_A 003721325015462500
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A 0010389040541125900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortB_A 003721325015462500
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A 0010389040541125900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortB_A 003721325015462500
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A 0010389040541125900
tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortB_A 003721325015462500
tb.dut.u_spid_status.BusyBitZero_A 0067967900
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A 00372132503721271100
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A 0010389040510382712200
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A 0067967900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 0067967900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A 0010389040545329800
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A 001038904054203900
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 001038904054203900
tb.dut.u_tlul2sram_egress.AddrOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.DataIntgOptions_A 0067967900
tb.dut.u_tlul2sram_egress.ReqOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.SramDwHasByteGranularity_A 0067967900
tb.dut.u_tlul2sram_egress.SramDwIsMultipleOfTlulWidth_A 0067967900
tb.dut.u_tlul2sram_egress.TlOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_A 0010389040546686800
tb.dut.u_tlul2sram_egress.TlOutPayloadKnown_AKnownEnable 0010389040510382794900
tb.dut.u_tlul2sram_egress.WdataOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.WeOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.WmaskOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.adapterNoReadOrWrite 0067967900
tb.dut.u_tlul2sram_egress.u_err.dataWidthOnly32_A 0067967900
tb.dut.u_tlul2sram_egress.u_reqfifo.DataKnown_A 0010389040546686800
tb.dut.u_tlul2sram_egress.u_reqfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_reqfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_reqfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0010389040546686800
tb.dut.u_tlul2sram_egress.u_rsp_gen.DataWidthCheck_A 0067967900
tb.dut.u_tlul2sram_egress.u_rsp_gen.PayLoadWidthCheck 0067967900
tb.dut.u_tlul2sram_egress.u_rspfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_rspfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_rspfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_sramreqfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_sramreqfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_egress.u_sramreqfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.AddrOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.DataIntgOptions_A 0067967900
tb.dut.u_tlul2sram_ingress.ReqOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.SramDwHasByteGranularity_A 0067967900
tb.dut.u_tlul2sram_ingress.SramDwIsMultipleOfTlulWidth_A 0067967900
tb.dut.u_tlul2sram_ingress.TlOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_A 001038904058601000
tb.dut.u_tlul2sram_ingress.TlOutPayloadKnown_AKnownEnable 0010389040510382794900
tb.dut.u_tlul2sram_ingress.WdataOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.WeOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.WmaskOutKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.adapterNoReadOrWrite 0067967900
tb.dut.u_tlul2sram_ingress.rvalidHighReqFifoEmpty 001038904054203900
tb.dut.u_tlul2sram_ingress.rvalidHighWhenRspFifoFull 001038904054203900
tb.dut.u_tlul2sram_ingress.u_err.dataWidthOnly32_A 0067967900
tb.dut.u_tlul2sram_ingress.u_reqfifo.DataKnown_A 001038904058601000
tb.dut.u_tlul2sram_ingress.u_reqfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_reqfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_reqfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001038904058601000
tb.dut.u_tlul2sram_ingress.u_rsp_gen.DataWidthCheck_A 0067967900
tb.dut.u_tlul2sram_ingress.u_rsp_gen.PayLoadWidthCheck 0067967900
tb.dut.u_tlul2sram_ingress.u_rspfifo.DataKnown_A 001038904058601000
tb.dut.u_tlul2sram_ingress.u_rspfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_rspfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_rspfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001038904058601000
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DataKnown_A 001038904054203900
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.DepthKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.RvalidKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.WreadyKnown_A 0010389040510382794900
tb.dut.u_tlul2sram_ingress.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 001038904054203900
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0 00382033794100
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0 00382033794100
tb.dut.u_upload.FifosOnlyOneValid_A 00372132502310710600
tb.dut.u_upload.u_addrfifo.MinDepth_A 0067967900
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A 0067967900
tb.dut.u_upload.u_addrfifo.WSramRvalid_A 00372132503721325000
tb.dut.u_upload.u_addrfifo.WidthMatch_A 0067967900
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A 00372132502310710600
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A 0067967900
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A 00372132502310710600
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A 00372132502310710600
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A 00372132502310710600
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A 00372132502310710600
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A 00372132502310710600
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A 00372132502310710600
tb.dut.u_upload.u_cmdfifo.MinDepth_A 0067967900
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A 0067967900
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A 00372132503721325000
tb.dut.u_upload.u_cmdfifo.WidthMatch_A 0067967900
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A 0067967900
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A 0067967900

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A 0010389040500679

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1 000000
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1 000000


Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0010620488717500175000
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00106204887234923490
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00106204887243524350
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00106204887160416040
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001062048872292290
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00106204887127112710
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001062048873583580
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0010620488712031120310
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001062048872205792205790
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0010620488714234361423436834

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0010620488717500175000
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 00106204887234923490
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 00106204887243524350
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00106204887160416040
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 001062048872292290
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00106204887127112710
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 001062048873583580
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0010620488712031120310
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C 001062048872205792205790
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C 0010620488714234361423436834

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