Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	28	20	41.67	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1160	1			T1	8		T2	10		T8	2
auto[SpiFlashAddrCfg]	772	1			T1	10		T4	2		T6	4
auto[SpiFlashAddr3b]	924	1			T1	6		T2	4		T4	2
auto[SpiFlashAddr4b]	755	1			T1	4		T4	2		T6	11

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2840

1

T1

28

T2

14

T6

20

auto[1]

771

1

T4

6

T8

6

T61

2

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1887

1

T1

14

T2

4

T4

2

auto[1]

1724

1

T1

14

T2

10

T4

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1582	1			T1	12		T2	14		T6	7
values[1]	66	1			T56	2		T173	2		T175	4
values[2]	145	1			T6	6		T175	6		T160	2
values[3]	162	1			T1	2		T7	4		T63	7
values[4]	139	1			T71	4		T72	5		T57	4
values[5]	119	1			T1	4		T4	2		T63	4
values[6]	143	1			T1	2		T6	3		T71	2
values[7]	211	1			T72	7		T73	2		T76	4
values[8]	1044	1			T1	8		T4	4		T6	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3150

1

T1

28

T2

14

T4

6

auto[1]

461

1

T6

20

T10

14

T63

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3542

1

T1

28

T2

14

T4

6

write

69

1

T70

2

T71

2

T74

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1687

1

T1

8

T4

4

T6

13

valids[0x1]

1924

1

T1

20

T2

14

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	168	1			T71	2		T45	10		T76	4
internal_process_ops[0x5a]	189	1			T1	4		T2	4		T71	2
internal_process_ops[0x05]	240	1			T1	2		T2	10		T69	2
internal_process_ops[0x35]	189	1			T38	8		T71	2		T45	2
internal_process_ops[0x15]	211	1			T1	2		T45	18		T76	4
internal_process_ops[0x03]	191	1			T1	4		T6	5		T7	2
internal_process_ops[0x0b]	214	1			T6	2		T9	2		T10	5
internal_process_ops[0x3b]	268	1			T1	2		T6	3		T9	2
internal_process_ops[0x6b]	207	1			T1	4		T63	1		T53	4
internal_process_ops[0xbb]	233	1			T6	6		T10	1		T63	4
internal_process_ops[0xeb]	228	1			T4	2		T6	4		T7	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3586

1

T1

28

T2

14

T4

6

auto[1]

25

1

T70

2

T71

2

T75

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3611

1

T1

28

T2

14

T4

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	28	20	41.67	28
Automatically Generated Cross Bins	48	28	20	41.67	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	*	*	*	--	--	16

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

949

1

T1

8

T2

10

T38

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

188

1

T8

2

T69

2

T71

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

423

1

T1

10

T9

2

T76

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

199

1

T4

2

T71

8

T59

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

530

1

T1

6

T2

4

T7

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

197

1

T4

2

T69

4

T71

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

433

1

T1

4

T7

4

T9

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

162

1

T4

2

T8

4

T61

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12

1

T278

2

T77

2

T283

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

4

1

T75

4

-

-

-

-

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

14

1

T160

2

T257

2

T191

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

8

1

T70

2

T71

2

T85

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

8

1

T74

2

T79

2

T233

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

2

1

T82

2

-

-

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

10

1

T76

2

T183

4

T244

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

11

1

T81

2

T86

1

T83

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7

1

T53

7

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T6

4

T63

1

T72

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

187

1

T6

5

T10

6

T63

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

139

1

T6

11

T10

8

T72

5

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[2] , values[3]]	[valids[0x1]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	348	1			T71	2		T73	4		T29	6
auto[0]	values[0]	valids[0x1]	1163	1			T1	12		T2	14		T7	2
auto[0]	values[1]	valids[0x1]	64	1			T56	2		T173	2		T175	4
auto[0]	values[2]	valids[0x0]	82	1			T175	2		T77	10		T284	2
auto[0]	values[2]	valids[0x1]	36	1			T175	4		T160	2		T163	4
auto[0]	values[3]	valids[0x0]	80	1			T7	4		T69	2		T171	4
auto[0]	values[3]	valids[0x1]	43	1			T1	2		T173	2		T163	2
auto[0]	values[4]	valids[0x0]	72	1			T71	4		T57	4		T80	4
auto[0]	values[4]	valids[0x1]	51	1			T211	2		T270	2		T46	2
auto[0]	values[5]	valids[0x0]	50	1			T1	4		T242	4		T163	2
auto[0]	values[5]	valids[0x1]	38	1			T4	2		T71	2		T45	4
auto[0]	values[6]	valids[0x0]	100	1			T1	2		T173	2		T31	2
auto[0]	values[6]	valids[0x1]	18	1			T71	2		T90	4		T186	2
auto[0]	values[7]	valids[0x0]	112	1			T73	2		T57	8		T80	4
auto[0]	values[7]	valids[0x1]	54	1			T76	4		T80	2		T245	2
auto[0]	values[8]	valids[0x0]	536	1			T1	2		T4	4		T9	2
auto[0]	values[8]	valids[0x1]	303	1			T1	6		T8	2		T9	2
auto[1]	values[0]	valids[0x1]	71	1			T6	7		T10	8		T53	11
auto[1]	values[1]	valids[0x1]	2	1			T285	2		-	-		-	-
auto[1]	values[2]	valids[0x0]	27	1			T6	6		T286	6		T287	6
auto[1]	values[3]	valids[0x0]	39	1			T63	7		T87	11		T288	3
auto[1]	values[4]	valids[0x0]	11	1			T289	1		T290	5		T291	3
auto[1]	values[4]	valids[0x1]	5	1			T72	5		-	-		-	-
auto[1]	values[5]	valids[0x0]	30	1			T63	4		T288	4		T290	5
auto[1]	values[5]	valids[0x1]	1	1			T292	1		-	-		-	-
auto[1]	values[6]	valids[0x0]	14	1			T6	3		T293	4		T285	5
auto[1]	values[6]	valids[0x1]	11	1			T294	7		T295	4		-	-
auto[1]	values[7]	valids[0x0]	37	1			T72	7		T289	7		T286	2
auto[1]	values[7]	valids[0x1]	8	1			T296	7		T297	1		-	-
auto[1]	values[8]	valids[0x0]	149	1			T6	4		T10	1		T63	1
auto[1]	values[8]	valids[0x1]	56	1			T10	5		T288	7		T298	6