Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1619584 1 T1 17 T2 61503 T4 1


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1438058 1 T1 1 T2 57875 T4 1
auto[1] 181526 1 T1 16 T2 3628 T45 21352


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 367826 1 T1 17 T2 4763 T4 1
auto[524288:1048575] 196239 1 T2 1625 T6 109 T7 153
auto[1048576:1572863] 176281 1 T2 13039 T6 1498 T7 70
auto[1572864:2097151] 177280 1 T2 16952 T6 236 T7 126
auto[2097152:2621439] 152847 1 T2 14759 T6 364 T7 132
auto[2621440:3145727] 234891 1 T2 8732 T7 116 T10 4910
auto[3145728:3670015] 158475 1 T2 1190 T6 591 T7 152
auto[3670016:4194303] 155745 1 T2 443 T6 1744 T7 71


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192394 1 T1 17 T2 3733 T4 1
auto[1] 1427190 1 T2 57770 T6 6157 T7 952


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1619584 1 T1 17 T2 61503 T4 1


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 248868 1 T1 1 T2 2699 T4 1
auto[0] auto[0] auto[0:524287] auto[1] 118958 1 T1 16 T2 2064 T45 9850
auto[0] auto[0] auto[524288:1048575] auto[0] 185162 1 T2 1624 T6 109 T7 153
auto[0] auto[0] auto[524288:1048575] auto[1] 11077 1 T2 1 T45 525 T166 4
auto[0] auto[0] auto[1048576:1572863] auto[0] 166688 1 T2 13036 T6 1498 T7 70
auto[0] auto[0] auto[1048576:1572863] auto[1] 9593 1 T2 3 T45 2330 T166 521
auto[0] auto[0] auto[1572864:2097151] auto[0] 168153 1 T2 16571 T6 236 T7 126
auto[0] auto[0] auto[1572864:2097151] auto[1] 9127 1 T2 381 T45 261 T166 20
auto[0] auto[0] auto[2097152:2621439] auto[0] 147808 1 T2 13582 T6 364 T7 132
auto[0] auto[0] auto[2097152:2621439] auto[1] 5039 1 T2 1177 T45 4 T167 6
auto[0] auto[0] auto[2621440:3145727] auto[0] 225639 1 T2 8730 T7 116 T10 4910
auto[0] auto[0] auto[2621440:3145727] auto[1] 9252 1 T2 2 T45 2217 T166 2709
auto[0] auto[0] auto[3145728:3670015] auto[0] 150394 1 T2 1190 T6 591 T7 152
auto[0] auto[0] auto[3145728:3670015] auto[1] 8081 1 T45 1445 T168 587 T167 259
auto[0] auto[0] auto[3670016:4194303] auto[0] 145346 1 T2 443 T6 1744 T7 71
auto[0] auto[0] auto[3670016:4194303] auto[1] 10399 1 T45 4720 T166 1666 T168 172


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 192394 1 T1 17 T2 3733 T4 1
auto[0] auto[0] auto[1] 1427190 1 T2 57770 T6 6157 T7 952

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