Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.97	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	38	90	70.31

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	38	90	70.31	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2379

1

T1

28

T2

14

T7

6

auto[1]

771

1

T4

6

T8

6

T61

2

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	490	1			T56	4		T59	4		T26	4
values[1]	276	1			T7	6		T169	2		T172	2
values[2]	378	1			T1	28		T4	6		T9	4
values[3]	342	1			T69	8		T71	28		T171	8
values[4]	488	1			T2	14		T8	6		T11	2
values[5]	390	1			T57	22		T80	30		T93	4
values[6]	496	1			T73	8		T76	26		T30	12
values[7]	290	1			T61	2		T70	2		T167	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T2	14		T38	8		T70	2
values[1]	364	1			T4	6		T61	2		T71	28
values[2]	320	1			T7	6		T9	4		T73	8
values[3]	386	1			T169	2		T173	22		T175	16
values[4]	324	1			T76	26		T59	4		T94	14
values[5]	282	1			T11	2		T248	8		T278	12
values[6]	638	1			T1	28		T8	6		T74	2
values[7]	318	1			T69	8		T29	6		T171	8

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	38	90	70.31	38

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[values[0]]	0	1	1
[auto[0]]	[values[1]]	[values[3]]	0	1	1
[auto[0]]	[values[2]]	[values[1]]	0	1	1
[auto[0]]	[values[3]]	[values[2]]	0	1	1
[auto[0]]	[values[5]]	[values[4] , values[5]]	--	--	2
[auto[0]]	[values[7]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[1]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[2]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[3]]	[values[0]]	0	1	1
[auto[1]]	[values[3]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[4]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	5
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2]]	0	1	1
[auto[1]]	[values[6]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[7]]	[values[5] , values[6]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	26	1			T163	24		T240	2		-	-
auto[0]	values[0]	values[1]	62	1			T26	4		T165	2		T270	12
auto[0]	values[0]	values[2]	30	1			T166	16		T255	14		-	-
auto[0]	values[0]	values[3]	32	1			T276	10		T299	16		T300	2
auto[0]	values[0]	values[4]	64	1			T245	26		T200	14		T189	20
auto[0]	values[0]	values[5]	38	1			T174	6		T193	18		T207	2
auto[0]	values[0]	values[6]	18	1			T168	18		-	-		-	-
auto[0]	values[0]	values[7]	34	1			T229	22		T301	12		-	-
auto[0]	values[1]	values[1]	36	1			T172	2		T230	22		T302	12
auto[0]	values[1]	values[2]	70	1			T7	6		T303	14		T218	24
auto[0]	values[1]	values[4]	4	1			T304	4		-	-		-	-
auto[0]	values[1]	values[5]	48	1			T202	18		T305	4		T179	22
auto[0]	values[1]	values[6]	59	1			T210	8		T86	15		T273	20
auto[0]	values[1]	values[7]	16	1			T266	16		-	-		-	-
auto[0]	values[2]	values[0]	68	1			T38	8		T242	12		T233	36
auto[0]	values[2]	values[2]	12	1			T9	4		T306	8		-	-
auto[0]	values[2]	values[3]	18	1			T280	2		T269	8		T307	6
auto[0]	values[2]	values[4]	22	1			T94	14		T191	8		-	-
auto[0]	values[2]	values[5]	50	1			T216	12		T243	10		T308	28
auto[0]	values[2]	values[6]	124	1			T1	28		T197	12		T231	14
auto[0]	values[2]	values[7]	6	1			T29	6		-	-		-	-
auto[0]	values[3]	values[0]	70	1			T27	24		T31	12		T194	8
auto[0]	values[3]	values[1]	32	1			T284	6		T309	20		T310	6
auto[0]	values[3]	values[3]	28	1			T262	22		T311	2		T258	4
auto[0]	values[3]	values[4]	8	1			T211	6		T217	2		-	-
auto[0]	values[3]	values[5]	12	1			T278	12		-	-		-	-
auto[0]	values[3]	values[6]	12	1			T223	2		T271	8		T228	2
auto[0]	values[3]	values[7]	28	1			T171	8		T312	6		T227	14
auto[0]	values[4]	values[0]	82	1			T2	14		T113	6		T213	26
auto[0]	values[4]	values[1]	46	1			T246	30		T206	6		T201	10
auto[0]	values[4]	values[2]	52	1			T89	14		T79	22		T235	10
auto[0]	values[4]	values[3]	54	1			T173	22		T32	20		T256	12
auto[0]	values[4]	values[4]	38	1			T187	18		T313	20		-	-
auto[0]	values[4]	values[5]	2	1			T11	2		-	-		-	-
auto[0]	values[4]	values[6]	88	1			T74	2		T45	40		T188	4
auto[0]	values[4]	values[7]	32	1			T106	2		T314	12		T315	6
auto[0]	values[5]	values[0]	16	1			T178	2		T316	14		-	-
auto[0]	values[5]	values[1]	26	1			T274	26		-	-		-	-
auto[0]	values[5]	values[2]	20	1			T281	2		T317	18		-	-
auto[0]	values[5]	values[3]	90	1			T175	16		T199	14		T318	10
auto[0]	values[5]	values[6]	112	1			T234	12		T190	4		T183	38
auto[0]	values[5]	values[7]	36	1			T57	22		T93	4		T268	2
auto[0]	values[6]	values[0]	68	1			T283	22		T319	28		T320	18
auto[0]	values[6]	values[1]	42	1			T257	20		T92	22		-	-
auto[0]	values[6]	values[2]	42	1			T73	8		T90	14		T232	2
auto[0]	values[6]	values[3]	68	1			T205	16		T321	16		T322	28
auto[0]	values[6]	values[4]	46	1			T76	26		T323	14		T196	6
auto[0]	values[6]	values[5]	80	1			T159	18		T279	14		T324	22
auto[0]	values[6]	values[6]	44	1			T28	16		T325	14		T326	14
auto[0]	values[6]	values[7]	62	1			T30	12		T77	28		T327	16
auto[0]	values[7]	values[0]	44	1			T184	18		T260	12		T203	4
auto[0]	values[7]	values[1]	32	1			T47	18		T259	2		T328	4
auto[0]	values[7]	values[2]	18	1			T222	2		T212	16		-	-
auto[0]	values[7]	values[3]	26	1			T329	6		T330	20		-	-
auto[0]	values[7]	values[4]	54	1			T167	10		T160	12		T249	14
auto[0]	values[7]	values[5]	12	1			T238	12		-	-		-	-
auto[0]	values[7]	values[6]	20	1			T198	8		T186	12		-	-
auto[1]	values[0]	values[0]	34	1			T254	14		T275	20		-	-
auto[1]	values[0]	values[1]	16	1			T239	12		T331	4		-	-
auto[1]	values[0]	values[2]	14	1			T56	4		T272	10		-	-
auto[1]	values[0]	values[3]	42	1			T84	20		T332	22		-	-
auto[1]	values[0]	values[4]	38	1			T59	4		T82	28		T83	6
auto[1]	values[0]	values[5]	18	1			T248	8		T185	10		-	-
auto[1]	values[0]	values[6]	2	1			T333	2		-	-		-	-
auto[1]	values[0]	values[7]	22	1			T236	22		-	-		-	-
auto[1]	values[1]	values[3]	2	1			T169	2		-	-		-	-
auto[1]	values[1]	values[6]	41	1			T176	24		T86	5		T267	12
auto[1]	values[2]	values[0]	48	1			T177	32		T180	16		-	-
auto[1]	values[2]	values[1]	6	1			T4	6		-	-		-	-
auto[1]	values[2]	values[4]	8	1			T219	8		-	-		-	-
auto[1]	values[2]	values[7]	16	1			T237	16		-	-		-	-
auto[1]	values[3]	values[1]	56	1			T71	28		T81	28		-	-
auto[1]	values[3]	values[2]	20	1			T334	20		-	-		-	-
auto[1]	values[3]	values[3]	24	1			T224	24		-	-		-	-
auto[1]	values[3]	values[4]	20	1			T335	20		-	-		-	-
auto[1]	values[3]	values[7]	32	1			T69	8		T336	24		-	-
auto[1]	values[4]	values[0]	24	1			T337	24		-	-		-	-
auto[1]	values[4]	values[6]	54	1			T8	6		T75	24		T338	24
auto[1]	values[4]	values[7]	16	1			T221	16		-	-		-	-
auto[1]	values[5]	values[0]	26	1			T251	26		-	-		-	-
auto[1]	values[5]	values[6]	64	1			T80	30		T85	34		-	-
auto[1]	values[6]	values[1]	8	1			T170	8		-	-		-	-
auto[1]	values[6]	values[3]	2	1			T339	2		-	-		-	-
auto[1]	values[6]	values[4]	12	1			T250	4		T340	8		-	-
auto[1]	values[6]	values[5]	22	1			T252	22		-	-		-	-
auto[1]	values[7]	values[0]	12	1			T70	2		T78	10		-	-
auto[1]	values[7]	values[1]	2	1			T61	2		-	-		-	-
auto[1]	values[7]	values[2]	42	1			T182	14		T253	28		-	-
auto[1]	values[7]	values[4]	10	1			T226	10		-	-		-	-
auto[1]	values[7]	values[7]	18	1			T341	18		-	-		-	-