Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 66 0 66 100.00
Crosses 128 0 128 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_filtered 2 0 2 100.00 100 1 1 2
cp_opcode 64 0 64 100.00 100 1 1 64


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 0 128 100.00 100 1 1 0


Summary for Variable cp_filtered

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_filtered

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1575 1 T1 14 T2 7 T4 3
auto[1] 2036 1 T1 14 T2 7 T4 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 64 0 64 100.00


Automatically Generated Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] 205 1 T1 4 T6 5 T7 2
auto[4:7] 324 1 T1 2 T2 10 T69 2
auto[8:11] 214 1 T6 2 T9 2 T10 5
auto[12:15] 16 1 T242 2 T175 4 T32 2
auto[16:19] 12 1 T273 4 T330 2 T369 2
auto[20:23] 221 1 T1 2 T45 18 T76 4
auto[24:27] 12 1 T81 4 T184 4 T326 2
auto[28:31] 22 1 T80 4 T245 4 T210 2
auto[32:35] 24 1 T175 6 T216 2 T254 2
auto[36:39] 10 1 T335 2 T237 4 T336 2
auto[40:43] 24 1 T1 2 T159 4 T283 2
auto[44:47] 28 1 T8 2 T73 4 T163 2
auto[48:51] 2 1 T218 2 - - - -
auto[52:55] 197 1 T38 8 T71 2 T45 2
auto[56:59] 282 1 T1 2 T6 3 T9 2
auto[60:63] 12 1 T80 4 T278 2 T187 2
auto[64:67] 12 1 T231 2 T370 2 T184 2
auto[68:71] 25 1 T242 2 T170 2 T191 2
auto[72:75] 24 1 T11 2 T173 6 T214 6
auto[76:79] 16 1 T59 2 T77 6 T309 2
auto[80:83] 14 1 T177 4 T261 4 T231 2
auto[84:87] 27 1 T245 4 T257 2 T186 2
auto[88:91] 215 1 T1 4 T2 4 T4 2
auto[92:95] 18 1 T175 2 T79 2 T239 2
auto[96:99] 20 1 T1 2 T76 4 T173 2
auto[100:103] 14 1 T79 2 T321 2 T273 2
auto[104:107] 211 1 T1 4 T63 1 T53 4
auto[108:111] 16 1 T242 2 T94 4 T371 4
auto[112:115] 13 1 T31 2 T233 2 T86 1
auto[116:119] 16 1 T80 4 T257 2 T187 2
auto[120:123] 20 1 T232 2 T176 6 T283 2
auto[124:127] 11 1 T1 2 T86 1 T239 2
auto[128:131] 14 1 T216 2 T257 4 T233 2
auto[132:135] 16 1 T229 4 T299 2 T82 2
auto[136:139] 22 1 T76 2 T248 4 T160 2
auto[140:143] 12 1 T69 2 T78 2 T214 4
auto[144:147] 12 1 T229 4 T241 2 T337 4
auto[148:151] 14 1 T71 2 T76 2 T173 2
auto[152:155] 2 1 T244 2 - - - -
auto[156:159] 182 1 T71 2 T45 10 T76 4
auto[160:163] 12 1 T71 2 T257 2 T183 4
auto[164:167] 30 1 T75 8 T187 4 T238 2
auto[168:171] 26 1 T94 2 T163 4 T78 2
auto[172:175] 18 1 T1 2 T176 2 T199 2
auto[176:179] 36 1 T74 2 T242 4 T80 2
auto[180:183] 101 1 T69 2 T29 6 T27 14
auto[184:187] 255 1 T4 2 T6 6 T10 1
auto[188:191] 4 1 T372 2 T316 2 - -
auto[192:195] 24 1 T1 2 T163 2 T170 2
auto[196:199] 20 1 T170 4 T245 2 T272 2
auto[200:203] 24 1 T278 2 T257 4 T226 2
auto[204:207] 12 1 T56 2 T183 4 T253 2
auto[208:211] 20 1 T216 2 T185 2 T324 4
auto[212:215] 12 1 T186 4 T202 2 T319 2
auto[216:219] 21 1 T173 2 T163 2 T257 2
auto[220:223] 22 1 T61 2 T80 2 T159 4
auto[224:227] 30 1 T73 2 T173 2 T159 2
auto[228:231] 14 1 T94 2 T334 2 T281 2
auto[232:235] 304 1 T4 2 T6 4 T7 4
auto[236:239] 15 1 T86 1 T273 4 T254 2
auto[240:243] 16 1 T69 2 T76 2 T187 2
auto[244:247] 6 1 T77 2 T245 2 T331 2
auto[248:251] 24 1 T80 2 T252 2 T231 2
auto[252:255] 14 1 T238 2 T323 2 T299 4



Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_opcodecp_filteredCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:3] auto[0] 69 1 T1 2 T7 1 T8 2
auto[0:3] auto[1] 136 1 T1 2 T6 5 T7 1
auto[4:7] auto[0] 162 1 T1 1 T2 5 T69 1
auto[4:7] auto[1] 162 1 T1 1 T2 5 T69 1
auto[8:11] auto[0] 67 1 T9 1 T76 2 T57 1
auto[8:11] auto[1] 147 1 T6 2 T9 1 T10 5
auto[12:15] auto[0] 8 1 T242 1 T175 2 T32 1
auto[12:15] auto[1] 8 1 T242 1 T175 2 T32 1
auto[16:19] auto[0] 6 1 T273 2 T330 1 T369 1
auto[16:19] auto[1] 6 1 T273 2 T330 1 T369 1
auto[20:23] auto[0] 110 1 T1 1 T45 9 T76 2
auto[20:23] auto[1] 111 1 T1 1 T45 9 T76 2
auto[24:27] auto[0] 6 1 T81 2 T184 2 T326 1
auto[24:27] auto[1] 6 1 T81 2 T184 2 T326 1
auto[28:31] auto[0] 11 1 T80 2 T245 2 T210 1
auto[28:31] auto[1] 11 1 T80 2 T245 2 T210 1
auto[32:35] auto[0] 12 1 T175 3 T216 1 T254 1
auto[32:35] auto[1] 12 1 T175 3 T216 1 T254 1
auto[36:39] auto[0] 5 1 T335 1 T237 2 T336 1
auto[36:39] auto[1] 5 1 T335 1 T237 2 T336 1
auto[40:43] auto[0] 12 1 T1 1 T159 2 T283 1
auto[40:43] auto[1] 12 1 T1 1 T159 2 T283 1
auto[44:47] auto[0] 14 1 T8 1 T73 2 T163 1
auto[44:47] auto[1] 14 1 T8 1 T73 2 T163 1
auto[48:51] auto[0] 1 1 T218 1 - - - -
auto[48:51] auto[1] 1 1 T218 1 - - - -
auto[52:55] auto[0] 99 1 T38 4 T71 1 T45 1
auto[52:55] auto[1] 98 1 T38 4 T71 1 T45 1
auto[56:59] auto[0] 97 1 T1 1 T9 1 T71 1
auto[56:59] auto[1] 185 1 T1 1 T6 3 T9 1
auto[60:63] auto[0] 6 1 T80 2 T278 1 T187 1
auto[60:63] auto[1] 6 1 T80 2 T278 1 T187 1
auto[64:67] auto[0] 6 1 T231 1 T370 1 T184 1
auto[64:67] auto[1] 6 1 T231 1 T370 1 T184 1
auto[68:71] auto[0] 11 1 T242 1 T170 1 T191 1
auto[68:71] auto[1] 14 1 T242 1 T170 1 T191 1
auto[72:75] auto[0] 12 1 T11 1 T173 3 T214 3
auto[72:75] auto[1] 12 1 T11 1 T173 3 T214 3
auto[76:79] auto[0] 8 1 T59 1 T77 3 T309 1
auto[76:79] auto[1] 8 1 T59 1 T77 3 T309 1
auto[80:83] auto[0] 7 1 T177 2 T261 2 T231 1
auto[80:83] auto[1] 7 1 T177 2 T261 2 T231 1
auto[84:87] auto[0] 15 1 T245 2 T257 1 T186 1
auto[84:87] auto[1] 12 1 T245 2 T257 1 T186 1
auto[88:91] auto[0] 107 1 T1 2 T2 2 T4 1
auto[88:91] auto[1] 108 1 T1 2 T2 2 T4 1
auto[92:95] auto[0] 9 1 T175 1 T79 1 T239 1
auto[92:95] auto[1] 9 1 T175 1 T79 1 T239 1
auto[96:99] auto[0] 10 1 T1 1 T76 2 T173 1
auto[96:99] auto[1] 10 1 T1 1 T76 2 T173 1
auto[100:103] auto[0] 7 1 T79 1 T321 1 T273 1
auto[100:103] auto[1] 7 1 T79 1 T321 1 T273 1
auto[104:107] auto[0] 76 1 T1 2 T57 4 T80 3
auto[104:107] auto[1] 135 1 T1 2 T63 1 T53 4
auto[108:111] auto[0] 8 1 T242 1 T94 2 T371 2
auto[108:111] auto[1] 8 1 T242 1 T94 2 T371 2
auto[112:115] auto[0] 7 1 T31 1 T233 1 T86 1
auto[112:115] auto[1] 6 1 T31 1 T233 1 T219 1
auto[116:119] auto[0] 8 1 T80 2 T257 1 T187 1
auto[116:119] auto[1] 8 1 T80 2 T257 1 T187 1
auto[120:123] auto[0] 10 1 T232 1 T176 3 T283 1
auto[120:123] auto[1] 10 1 T232 1 T176 3 T283 1
auto[124:127] auto[0] 6 1 T1 1 T86 1 T239 1
auto[124:127] auto[1] 5 1 T1 1 T239 1 T323 1
auto[128:131] auto[0] 7 1 T216 1 T257 2 T233 1
auto[128:131] auto[1] 7 1 T216 1 T257 2 T233 1
auto[132:135] auto[0] 8 1 T229 2 T299 1 T82 1
auto[132:135] auto[1] 8 1 T229 2 T299 1 T82 1
auto[136:139] auto[0] 11 1 T76 1 T248 2 T160 1
auto[136:139] auto[1] 11 1 T76 1 T248 2 T160 1
auto[140:143] auto[0] 6 1 T69 1 T78 1 T214 2
auto[140:143] auto[1] 6 1 T69 1 T78 1 T214 2
auto[144:147] auto[0] 6 1 T229 2 T241 1 T337 2
auto[144:147] auto[1] 6 1 T229 2 T241 1 T337 2
auto[148:151] auto[0] 7 1 T71 1 T76 1 T173 1
auto[148:151] auto[1] 7 1 T71 1 T76 1 T173 1
auto[152:155] auto[0] 1 1 T244 1 - - - -
auto[152:155] auto[1] 1 1 T244 1 - - - -
auto[156:159] auto[0] 91 1 T71 1 T45 5 T76 2
auto[156:159] auto[1] 91 1 T71 1 T45 5 T76 2
auto[160:163] auto[0] 6 1 T71 1 T257 1 T183 2
auto[160:163] auto[1] 6 1 T71 1 T257 1 T183 2
auto[164:167] auto[0] 15 1 T75 4 T187 2 T238 1
auto[164:167] auto[1] 15 1 T75 4 T187 2 T238 1
auto[168:171] auto[0] 13 1 T94 1 T163 2 T78 1
auto[168:171] auto[1] 13 1 T94 1 T163 2 T78 1
auto[172:175] auto[0] 9 1 T1 1 T176 1 T199 1
auto[172:175] auto[1] 9 1 T1 1 T176 1 T199 1
auto[176:179] auto[0] 18 1 T74 1 T242 2 T80 1
auto[176:179] auto[1] 18 1 T74 1 T242 2 T80 1
auto[180:183] auto[0] 51 1 T69 1 T29 3 T27 7
auto[180:183] auto[1] 50 1 T69 1 T29 3 T27 7
auto[184:187] auto[0] 79 1 T4 1 T70 1 T71 2
auto[184:187] auto[1] 176 1 T4 1 T6 6 T10 1
auto[188:191] auto[0] 2 1 T372 1 T316 1 - -
auto[188:191] auto[1] 2 1 T372 1 T316 1 - -
auto[192:195] auto[0] 12 1 T1 1 T163 1 T170 1
auto[192:195] auto[1] 12 1 T1 1 T163 1 T170 1
auto[196:199] auto[0] 10 1 T170 2 T245 1 T272 1
auto[196:199] auto[1] 10 1 T170 2 T245 1 T272 1
auto[200:203] auto[0] 12 1 T278 1 T257 2 T226 1
auto[200:203] auto[1] 12 1 T278 1 T257 2 T226 1
auto[204:207] auto[0] 6 1 T56 1 T183 2 T253 1
auto[204:207] auto[1] 6 1 T56 1 T183 2 T253 1
auto[208:211] auto[0] 10 1 T216 1 T185 1 T324 2
auto[208:211] auto[1] 10 1 T216 1 T185 1 T324 2
auto[212:215] auto[0] 6 1 T186 2 T202 1 T319 1
auto[212:215] auto[1] 6 1 T186 2 T202 1 T319 1
auto[216:219] auto[0] 11 1 T173 1 T163 1 T257 1
auto[216:219] auto[1] 10 1 T173 1 T163 1 T257 1
auto[220:223] auto[0] 10 1 T61 1 T80 1 T159 2
auto[220:223] auto[1] 12 1 T61 1 T80 1 T159 2
auto[224:227] auto[0] 15 1 T73 1 T173 1 T159 1
auto[224:227] auto[1] 15 1 T73 1 T173 1 T159 1
auto[228:231] auto[0] 7 1 T94 1 T334 1 T281 1
auto[228:231] auto[1] 7 1 T94 1 T334 1 T281 1
auto[232:235] auto[0] 117 1 T4 1 T7 2 T76 1
auto[232:235] auto[1] 187 1 T4 1 T6 4 T7 2
auto[236:239] auto[0] 7 1 T273 2 T254 1 T221 2
auto[236:239] auto[1] 8 1 T86 1 T273 2 T254 1
auto[240:243] auto[0] 8 1 T69 1 T76 1 T187 1
auto[240:243] auto[1] 8 1 T69 1 T76 1 T187 1
auto[244:247] auto[0] 3 1 T77 1 T245 1 T331 1
auto[244:247] auto[1] 3 1 T77 1 T245 1 T331 1
auto[248:251] auto[0] 12 1 T80 1 T252 1 T231 1
auto[248:251] auto[1] 12 1 T80 1 T252 1 T231 1
auto[252:255] auto[0] 7 1 T238 1 T323 1 T299 2
auto[252:255] auto[1] 7 1 T238 1 T323 1 T299 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%