Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	6	54	90.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	6	54	90.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	110	1			T7	6		T9	4		T168	8
auto[ReadAddrCrossIntoMailbox]	34	1			T249	6		T234	2		T215	2
auto[ReadAddrCrossOutOfMailbox]	22	1			T198	2		T207	2		T215	2
auto[ReadAddrCrossAllMailbox]	18	1			T284	2		T249	2		T198	2
auto[ReadAddrOutsideMailbox]	676	1			T1	10		T4	2		T8	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

429

1

T1

5

T4

1

T7

3

auto[1]

431

1

T1

5

T4

1

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	124	1			T1	4		T7	2		T8	4
read_ops[0x0b]	132	1			T9	2		T76	4		T57	2
read_ops[0x3b]	178	1			T1	2		T9	2		T73	2
read_ops[0x6b]	142	1			T1	4		T57	8		T168	2
read_ops[0xbb]	135	1			T71	4		T57	8		T159	2
read_ops[0xeb]	149	1			T4	2		T7	4		T76	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossOutOfMailbox] , auto[ReadAddrCrossAllMailbox]]	*	--	--	4
[read_ops[0xbb]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T7	1		T168	1		T205	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T7	1		T168	1		T205	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T215	1		T342	1		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T215	1		T342	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	54	1			T1	2		T8	2		T32	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	54	1			T1	2		T8	2		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T9	1		T90	2		T46	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T9	1		T90	2		T46	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T249	1		T304	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T249	1		T304	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T310	1		T255	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T310	1		T255	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T284	1		T249	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T284	1		T249	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	48	1			T76	2		T57	1		T94	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	48	1			T76	2		T57	1		T94	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T9	1		T168	1		T90	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T9	1		T168	1		T90	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T312	1		T343	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T312	1		T343	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T198	1		T207	1		T312	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T198	1		T207	1		T312	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T198	1		T255	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T198	1		T255	2		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T1	1		T73	1		T171	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T1	1		T73	1		T171	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T168	1		T249	1		T235	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T168	1		T249	1		T235	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	7	1			T249	2		T234	1		T308	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	7	1			T249	2		T234	1		T308	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T215	1		T308	2		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T215	1		T308	2		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T342	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T342	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	49	1			T1	2		T57	4		T32	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	49	1			T1	2		T57	4		T32	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T284	1		T205	2		T314	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T284	1		T205	2		T314	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T306	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T306	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T310	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T310	2		-	-		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	56	1			T71	2		T57	4		T159	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	57	1			T71	2		T57	4		T159	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T7	2		T168	1		T90	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T7	2		T168	1		T90	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T305	1		T343	1		T255	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T305	1		T343	1		T255	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T344	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T344	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T344	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T344	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T4	1		T76	1		T56	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T4	1		T76	1		T56	1